From: "Emilio G. Cota"
It's been superseded by the atomic helpers.
The use of the atomic helpers provides a significant performance and scalability
improvement. Below is the result of running the atomic_add-test microbenchmark
with:
$ x86_64-linux-user/qemu-x86_64 tests/atomic_add-bench -o 500
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-19-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/tr
From: "Emilio G. Cota"
[rth: Move redundant qemu_load out of cmpxchg loop.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-16-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 38 ++
1 file changed, 3
From: "Emilio G. Cota"
[rth: Avoid qemu_load that's redundant with the atomic op.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-15-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 26 --
1 file changed, 20 ins
From: "Emilio G. Cota"
[rth: Eliminate some unnecessary temporaries.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-13-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 76 +
1 file chang
Add all of cmpxchg, op_fetch, fetch_op, and xchg.
Handle both endian-ness, and sizes up to 8.
Handle expanding non-atomically, when emulating in serial.
Signed-off-by: Richard Henderson
---
Makefile.objs | 2 +-
Makefile.target | 1 +
atomic_template.h | 173 +++
Emulating LL/SC with cmpxchg is not correct, since it can
suffer from the ABA problem. However, portable parallel
code is written assuming only cmpxchg which means that in
practice this is a viable alternative.
Signed-off-by: Richard Henderson
---
linux-user/main.c| 49
From: "Emilio G. Cota"
The diff here is uglier than necessary. All this does is to turn
FOO
into:
if (s->prefix & PREFIX_LOCK) {
BAR
} else {
FOO
}
where FOO is the original implementation of an unlocked cmpxchg.
[rth: Adjust unlocked cmpxchg to use movcond instead of branches.
Adjust he
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
cputlb.c | 21 +
softmmu_template.h | 23 ---
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 5575b73..0c9b77b 100644
--- a/cputlb.c
+++ b/cp
From: "Emilio G. Cota"
The exception is not emitted anymore.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-30-git-send-email-c...@braap.org>
---
linux-user/main.c | 125 ---
Rather than using helpers for physical accesses, use a mmu index.
The primary cleanup is with store-conditional on physical addresses.
Signed-off-by: Richard Henderson
---
target-alpha/cpu.h| 18 +---
target-alpha/helper.c | 8 ++
target-alpha/helper.h | 9 --
t
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index cdd61d6..bb2bfee 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -150,17 +150,7 @@ void tcg_gen_op6(TCGCon
TGT_LE and TGT_BE are not size dependent and do not need to be
redefined. The others are no longer used at all.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
cputlb.c | 8
softmmu_template.h | 22 --
2 files changed, 8 insertions(+), 22 d
From: "Emilio G. Cota"
The exception is not emitted anymore.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-29-git-send-email-c...@braap.org>
---
linux-user/main.c | 93
From: "Emilio G. Cota"
[rth: Move load of reg value to common location.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-17-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletio
Saves 2k code size off of a cold path.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
cputlb.c | 37 +
softmmu_template.h | 52 ++--
2 files changed, 47 insertions(+), 42 deletions(-)
d
We already include exec/address-spaces.h and exec/memory.h in
cputlb.c; the include of qemu/timer.h appears to be a fossil.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
softmmu_template.h | 4
1 file changed, 4 deletions(-)
diff --git a/softmmu_template.h b/softmmu_templa
From: "Emilio G. Cota"
[rth: Avoid redundant qemu_ld in locked case. Fix previously unnoticed
incorrect zero-extension of address in register-offset case.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-18-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
targe
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
cputlb.c | 16
softmmu_template.h | 7 ++-
2 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 3c99c34..5575b73 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -529,16 +52
From: "Emilio G. Cota"
[rth: Merge gen_inc_locked back into gen_inc to share cc update.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-14-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 24 +---
1 file changed, 13
From: Alex Bennée
The variable parallel_cpus controls the generation of thread aware
atomic code. We only need to set it once we clone our first thread.
At this point any existing translations need to be thrown away.
Signed-off-by: Alex Bennée
Signed-off-by: Richard Henderson
---
linux-user/
Force the use of cmpxchg16b on x86_64.
Wikipedia suggests that only very old AMD64 (circa 2004) did not have
this instruction. Further, it's required by Windows 8 so no new cpus
will ever omit it.
If we truely care about these, then we could check this at startup time
and then avoid executing pa
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 135 +-
tests/test-int128.c | 22
2 files changed, 145 insertions(+), 12 deletions(-)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
inde
Allow qemu to build on 32-bit hosts without 64-bit atomic ops.
Even if we only allow 32-bit hosts to multi-thread emulate 32-bit
guests, we still need some way to handle the 32-bit guest using a
64-bit atomic operation. Do so by dropping back to single-step.
Signed-off-by: Richard Henderson
---
From: "Emilio G. Cota"
This paves the way for upcoming work.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-9-git-send-email-c...@braap.org>
---
include/qemu/atomic.h | 17 +
1 file changed, 17 insertions(
Allows Int128 to be used more generally, rather than having to
begin with 64-bit inputs and accumulate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/include/qemu/int1
From: "Emilio G. Cota"
This paves the way for upcoming work.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-8-git-send-email-c...@braap.org>
---
include/qemu/atomic.h | 4
1 file changed, 4 insertions(+)
diff --git
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
exec.c| 4 ++--
include/qemu/int128.h | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index c8389f9..cc2997e 100644
--- a/exec.c
+++ b/exec.c
@@ -320,9 +320,9 @@ static
Hopefully I've (re-)incorporated all of the commentary from v3 and v4.
Please do double-check.
r~
Alex Bennée (1):
linux-user: enable parallel code generation on clone
Emilio G. Cota (18):
atomics: add atomic_xor
atomics: add atomic_op_fetch variants
target-i386: emulate LOCK'ed cmpxch
On Thu, Oct 06, 2016 at 06:00:52PM +0200, Radim Krčmář wrote:
> 2016-10-06 11:51-0300, Eduardo Habkost:
> > On Wed, Oct 05, 2016 at 03:06:56PM +0200, Radim Krčmář wrote:
> >> Signed-off-by: Radim Krčmář
> >> ---
> >> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> >> @@ -2015,6 +2015,
On Wed, Sep 28, 2016 at 10:28:48AM +0800, Yuanhan Liu wrote:
> On Tue, Sep 27, 2016 at 10:56:40PM +0300, Michael S. Tsirkin wrote:
> > On Tue, Sep 27, 2016 at 11:11:58AM +0800, Yuanhan Liu wrote:
> > > On Mon, Sep 26, 2016 at 10:24:55PM +0300, Michael S. Tsirkin wrote:
> > > > On Mon, Sep 26, 2016
On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
+r->element[i] = (~(b->element[i]) + 1) & mask; \
Any reason you're not writing this as a proper negate?
r~
On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
+VEXT_SIGNED(vextsb2w, s32, UINT8_MAX, char, int32_t)
+VEXT_SIGNED(vextsb2d, s64, UINT8_MAX, char, int64_t)
char has target-dependent sign. Use int8_t.
r~
On Thu, Sep 22, 2016 at 01:13:41PM +0100, Felipe Franciosi wrote:
> Vhost-user requires an early GET_FEATURES call to determine if the
> slave supports protocol feature negotiation. An extra GET_FEATURES
> call is made after vhost_backend_init() to actually set the device
> features.
>
> This patc
This patch doesn't seem to be in the main repo yet. Any idea when it might
land?
- Dave
On Thu, Sep 29, 2016 at 8:52 AM, Michael Tokarev wrote:
> 22.09.2016 07:00, David Anderson wrote:
>
>> This makes it easier to parse the schema file for tool generation:
>> each paragraph is either a non-doc
On Sun, Oct 09, 2016 at 11:47:57PM +0300, Michael S. Tsirkin wrote:
> On Sat, Oct 08, 2016 at 01:24:55PM +0800, Peter Xu wrote:
> > On Tue, Oct 04, 2016 at 01:17:28PM +0200, Igor Mammedov wrote:
> > > On Fri, 30 Sep 2016 18:10:08 +0200
> > > Radim Krčmář wrote:
> > >
> > > > The MMIO interface to
On Tue, Sep 20, 2016 at 08:40:41PM +0300, David Kiarie wrote:
> When using IOMMU platform devices like IOAPIC are required to make
> interrupt remapping requests using explicit SID. We associate an MSI
> route with a requester ID and a PCI device if present which ensures
> that platform devices can
On Wed, Sep 21, 2016 at 03:18:47PM +0200, Paolo Bonzini wrote:
> This series started as an attempt to always use the dataplane path
> for virtio-blk and virtio-scsi when ioeventfd is active. The aim
> was three-fold:
>
> 1) to add more coverage for dataplane
>
> 2) to remove virtio_add_queue_aio
On Sat, Oct 08, 2016 at 02:37:59PM +0800, Peter Xu wrote:
> On Wed, Oct 05, 2016 at 03:06:51PM +0200, Radim Krčmář wrote:
> > The MMIO based interface to APIC doesn't work well with MSIs that have
> > upper address bits set (remapped x2APIC MSIs). A specialized interface
> > is a quick and dirty w
On Tue, Oct 04, 2016 at 01:30:48PM +0200, Laurent Vivier wrote:
> This avoids to have logs polluted by "kvm accelerator not found".
>
> Signed-off-by: Laurent Vivier
Acked-by: Michael S. Tsirkin
> ---
> tests/bios-tables-test.c | 2 +-
> tests/postcopy-test.c| 8
> 2 files chan
On Sat, Oct 08, 2016 at 01:24:55PM +0800, Peter Xu wrote:
> On Tue, Oct 04, 2016 at 01:17:28PM +0200, Igor Mammedov wrote:
> > On Fri, 30 Sep 2016 18:10:08 +0200
> > Radim Krčmář wrote:
> >
> > > The MMIO interface to APIC only allowed 8 bit addresses, which is not
> > > enough for 32 bit address
On Tue, Oct 4, 2016 at 11:06 AM, Paolo Bonzini wrote:
>
>
> On 04/10/2016 08:43, Emil Condrea wrote:
>> xen_be_frontend_changed -> xen_fe_frontend_changed
>
> This is not correct. The front-end is implemented in the guest domain,
> while the back-end is implemented in the dom0 or stubdom.
>
You
From: Thorsten Kohfeldt
Date: Sat, 24 Sep 2016 20:43:20 +0200
Subject: [PATCH] vfio: Fix vfio_rtl8168_quirk_data_read address offset
Introductory comment for rtl8168 VFIO MSI-X quirk states:
At BAR2 offset 0x70 there is a dword data register,
offset 0x74 is a dword address register.
vfio
Public bug reported:
hw/dma/pl080.c:354:1: warning: V578 An odd bitwise operation detected:
s->conf & (0x2 | 0x2). Consider verifying it.
Source code is
if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
Maybe better code
if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) {
** Affects
Now that the DMA helpers are byte-aligned they can be called directly from
the macio routines rather than emulating byte-aligned accesses via multiple
block-level accesses.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/macio.c | 213
1 file
This is a follow-up to the thread at
https://lists.gnu.org/archive/html/qemu-devel/2016-09/msg01396.html which
introduces an explicit alignment to the DMA helpers to facilitate conversion
of the macio controller over to use the now byte-aligned DMA helpers.
Patch 1 introduces an alignment paramete
The hard-coded default alignment is BDRV_SECTOR_SIZE, however this is not
necessarily the case for all platforms. Use this as the default alignment for
all current callers.
Signed-off-by: Mark Cave-Ayland
---
dma-helpers.c| 20 +++-
hw/block/nvme.c |6 --
h
On Sun, Oct 09, 2016 at 05:17:27PM +0800, Xu Tian wrote:
> If backing file can not open when do qemu-img rebase, var 'ret' not
> assign a no-zero value, qemu-img process go out with exit code zero.
>
> Signed-off-by: Xu Tian
> ---
> qemu-img.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff
帆，昨天电话里面好像还有个点没清楚，这个点也在这个patch里，不知道我理解
的对不对，有空的时候请帮斧正下：
（已经理解，对于uncorrectable error, driver里是会做reset link的，也就是
设置pci bridge的secondary bus reset的那个bit）
On 07/19/2016 03:38 PM, Zhou Jie wrote:
From: Chen Fan
Due to all devices assigned to VM on the same way as host if enable
aer, so we can eas
At 2016/10/7 20:21, Paolo Bonzini wrote:
Without this change, there is a race condition in tests/test-replication.
Depending on how fast the failover job (active commit) runs, there is a
chance of two bad things happening:
1) replication_done can be called after the secondary has been closed
and
Hello Stefan,
I'm not familiar with the migration. In order not miss something, I think
you can provide this patch.
Thanks.
2016-10-09 0:43 GMT+08:00 Stefan Weil :
> Am 08.10.2016 um 18:19 schrieb Stefan Weil:
>
>> Am 08.10.2016 um 14:07 schrieb Li Qiang:
>>
>>> From: Li Qiang
>>>
>>> The exit
On Sun, Oct 9, 2016 at 3:04 AM, Eric Blake wrote:
> On 10/08/2016 06:32 AM, Anand J wrote:
> > I have replied for the questions inline. Also I'll make changes to the
> > patch as per the review and send the updated one.
> >
> > Thanks,
> > Anand
> >
> > On Fri, Oct 7, 2016 at 8:01 PM, Eric Blake
iSER is a new transport layer supported in Libiscsi,
iSER provides a zero-copy RDMA capable interface that can
improve performance.
In order to use the new iSER transport one need to have RDMA supported HW
and to choose iser as the protocol name in Libiscsi URI.
For now iSER memory buffers are pr
Introducing new transport abstraction, with additional support
in iSER transport layer. Also adding new zero-copy API that is
needed in iSER case.
changes from v1:
- Adding iser as an additional block driver
changes from v2:
- Splitting iser support and new API into two patches
- Removing option
A new API to deploy zero-copy command submission. The new API takes I/O
vectors list and number of I/O vectors to submit as input parameters
when initiating the command. New API must be used if working with
iSER transport option.
Signed-off-by: Roy Shterman
---
block/iscsi.c | 36 +
101 - 155 of 155 matches
Mail list logo
