On Thu, Oct 13, 2016 at 09:10:22PM -0700, no-re...@patchew.org wrote:
> Hi,
>
> Your series seems to have some coding style problems. See output below for
> more information:
checkpatch generates a fair few false positives. However, having had
a look, these don't appear to be so.
>
> Subject:
On Mon, Oct 03, 2016 at 09:24:52AM +0200, Cédric Le Goater wrote:
> and also link the XICS object to each core as it is needed to do the
> CPU setup.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/ppc/pnv.c | 18 ++
> hw/ppc/pnv_core.c| 25 +
>
On Mon, Oct 03, 2016 at 09:24:56AM +0200, Cédric Le Goater wrote:
> The LPC Controller on POWER9 is very similar to the one found on
> POWER8 but accesses are now done via on MMIOs, without the XSCOM and
> ECCB logic. The device tree is populated differently so we add a
> PnvLpcClass and a couple o
On Thu, Oct 13, 2016 at 09:10:38PM -0700, no-re...@patchew.org wrote:
> Hi,
>
> Your series seems to have some coding style problems. See output below for
> more information:
So.. this one is a fairly standard false positive. checkpatch
complains about multiple statements in a macro when it's ac
On Mon, Oct 03, 2016 at 09:24:48AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Useful to debug interrupt problems.
>
> Signed-off-by: Benjamin Herrenschmidt
> [clg: - updated for qemu-2.7
> - added a test on ->irqs as it is not necessarily allocated
> (PHB3_M
On Mon, Oct 03, 2016 at 09:24:51AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> This provides access to the MMIO based Interrupt Presentation
> Controllers (ICP) as found on a POWER8 system.
>
> A new XICSNative class is introduced to hold the MMIO region of the
> ICPs. It a
On Wed, Oct 12, 2016 at 06:13:59PM -0500, Michael Roth wrote:
> From: Bharata B Rao
>
> Add support to hot remove pc-dimm memory devices.
>
> Signed-off-by: Bharata B Rao
> * add hooks to CAS/cmdline enablement of hotplug ACR support
> Signed-off-by: Michael Roth
> ---
> hw/ppc/spapr.c |
On Mon, Oct 03, 2016 at 09:24:49AM +0200, Cédric Le Goater wrote:
> Today, the Interrupt Presentation Controllers (ICP) are stored in an
> array under the base class XICSState. They are simply indexed using
> the CPU index field of CPUState. This made sense for the current
> derived classes, spapr
On 14/10/2016 07:41, David Gibson wrote:
> On Thu, Oct 13, 2016 at 09:10:38PM -0700, no-re...@patchew.org wrote:
>> Hi,
>>
>> Your series seems to have some coding style problems. See output below for
>> more information:
>
> So.. this one is a fairly standard false positive. checkpatch
> compl
On Fri, 2016-10-14 at 17:32 +1100, David Gibson wrote:
> > static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
> > {
> > - /* We don't yet emulate the PSI bridge which provides the external
> > - * interrupt, so just drop interrupts on the floor
> > - */
> > + s
On Mon, Oct 03, 2016 at 09:24:54AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> The OCC is an on-chip microcontroller based on a ppc405 core used
> for various power management tasks. It comes with a pile of additional
> hardware sitting on the PIB (aka XSCOM bus). At this po
On Wed, Oct 12, 2016 at 06:13:50PM -0500, Michael Roth wrote:
> Currently we access individual bytes of an option vector via
> ldub_phys() to test for the presence of a particular capability
> within that byte. Currently this is only done for the "dynamic
> reconfiguration memory" capability bit. I
On Mon, Oct 03, 2016 at 09:24:46AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Instead of an array of fixed sized blocks, use a list, as we will need
> to have sources with variable number of interrupts. SPAPR only uses
> a single entry. Native will create more. If performan
On Mon, Oct 03, 2016 at 09:24:55AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> It adds the Naples chip which supports proper LPC interrupts via the
> LPC controller rather than via an external CPLD.
>
> Signed-off-by: Benjamin Herrenschmidt
> [clg: - updated for qemu-2.7
>
On Mon, Oct 03, 2016 at 09:24:53AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> The PSI (Processor Service Interface) is one of the engines of the
> "Bridge" unit which connects the different interfaces to the Power
> Processor.
>
> This adds just enough of the PSI bridge to
On 14/10/2016 06:07, David Gibson wrote:
> On Thu, Oct 13, 2016 at 06:24:45PM +0200, Laurent Vivier wrote:
>> We have now the cpu_exec_realize() in realize,
>> so the init part must be in init.
>>
>> As cpu_exec_unrealize() is called from cpu_common_finalize(),
>> remove the call from ppc_cpu_unr
On 14/10/2016 01:29, David Gibson wrote:
> From 98f07c09c6d72218800d6cfbf44b973a88ece2aa Mon Sep 17 00:00:00 2001
> From: David Gibson
> Date: Fri, 14 Oct 2016 10:21:00 +1100
> Subject: [PATCH] spapr: Improved placement of PCI host bridges in guest memory
> map
>
> Currently, the MMIO space for
On 13/10/2016 22:26, Thomas Huth wrote:
> On 13.10.2016 21:53, Laurent Vivier wrote:
>> g3beige (pmac_oldworld) and mac99 (pmac_newworld) are missing in
>> boot-serial-test.
>>
>> Perhaps because serial output of OpenBIOS is only enabled with
>> '-nographic'
>
> IIRC clearly, I've left them out
On 10/14/2016 07:32 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:46AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> Instead of an array of fixed sized blocks, use a list, as we will need
>> to have sources with variable number of interrupts. SPAPR only uses
>> a s
On 10/14/2016 07:30 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:48AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> Useful to debug interrupt problems.
>>
>> Signed-off-by: Benjamin Herrenschmidt
>> [clg: - updated for qemu-2.7
>> - added a test on ->irqs a
On 10/14/2016 07:34 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:49AM +0200, Cédric Le Goater wrote:
>> Today, the Interrupt Presentation Controllers (ICP) are stored in an
>> array under the base class XICSState. They are simply indexed using
>> the CPU index field of CPUState. This mad
On 10/14/2016 08:36 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:55AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> It adds the Naples chip which supports proper LPC interrupts via the
>> LPC controller rather than via an external CPLD.
>>
>> Signed-off-by: Benjam
On Thu, Oct 13, 2016 at 05:19:37PM +0100, Peter Maydell wrote:
> On 4 October 2016 at 22:38, Wei Huang wrote:
> > This patchset adds a pmu=[on/off] option to enable/disable vPMU support
> > for guest VM. There are several reasons to justify this option. First,
> > vPMU can be problematic for cross
On 10/13/2016 09:33 PM, Igor Mammedov wrote:
On Wed, 12 Oct 2016 16:20:07 +0800
Xiao Guangrong wrote:
On 10/11/2016 07:49 PM, Igor Mammedov wrote:
On Mon, 10 Oct 2016 21:09:30 +0800
Xiao Guangrong wrote:
On 10/10/2016 08:51 PM, Igor Mammedov wrote:
On Sat, 8 Oct 2016 15:17:14 +0800
Xiao
On Thu, 13 Oct 2016 18:24:43 +0200
Laurent Vivier wrote:
> Extract the realize part to cpu_exec_realize(), update all
> calls to cpu_exec_init() to add cpu_exec_realize() to
> have no functionnal change.
>
> Put in cpu_exec_init() what initializes the CPU,
> in cpu_exec_realize() what adds it to
On Thu, 13 Oct 2016 21:05:54 -0700 (PDT)
no-re...@ec2-52-6-146-230.compute-1.amazonaws.com wrote:
> Hi,
>
> Your series failed automatic build test. Please find the testing commands and
> their output below. If you have docker installed, you can probably reproduce
> it
> locally.
[..]
> /tmp/qem
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -318,15 +318,24 @@ static void ppc_powernv_reset(void)
>> * have a CPLD that will collect the SerIRQ and shoot them as a
>> * single level interrupt to the P8 chip. So let's setup a hook
>> * for doing just that.
>> - *
>> - * Note: The actual
On Fri, 7 Oct 2016 19:54:54 +0200
Laurent Vivier wrote:
> On 07/10/2016 18:38, Greg Kurz wrote:
> > On Sat, 1 Oct 2016 20:56:02 +0200
> > Laurent Vivier wrote:
> >
> >> This patch replaces calls to qtest_start() and qtest_end() by
> >> calls to qtest_pc_boot() and qtest_shutdown().
> >>
> >>
Drew,
On 13/10/2016 17:11, Andrew Jones wrote:
> On Thu, Oct 13, 2016 at 12:55:43PM +0200, Eric Auger wrote:
>> From: Prem Mallappa
>>
>> This patch builds an IORT table that features a root complex node and
>> an ITS node. This complements the ITS description in the ACPI MADT
>> table and allows
* Stefan Weil (s...@weilnetz.de) wrote:
> Instead of allocating a VMStateDescription for each NIC instance,
> the code now uses a single constant VMStateDescription for all
> instances. That implies that the name field is always the same.
Doesn't this break migration compatibility?
You might be a
On Fri, 14 Oct 2016 09:28:35 +1100
David Gibson wrote:
> On Thu, Oct 13, 2016 at 12:57:19PM +0100, Peter Maydell wrote:
> > On 13 October 2016 at 12:54, Peter Maydell
> > wrote:
> > > On 13 October 2016 at 06:15, David Gibson
> > > wrote:
> > >> The following changes since commit
> > >>
On 14/10/2016 10:11, Greg Kurz wrote:
> On Fri, 7 Oct 2016 19:54:54 +0200
> Laurent Vivier wrote:
>
>> On 07/10/2016 18:38, Greg Kurz wrote:
>>> On Sat, 1 Oct 2016 20:56:02 +0200
>>> Laurent Vivier wrote:
>>>
This patch replaces calls to qtest_start() and qtest_end() by
calls to
On Wed, Oct 12, 2016 at 06:13:55PM -0500, Michael Roth wrote:
> This adds machine options of the form:
>
> -machine pseries,legacy-hotplug-events=true
> -machine pseries,legacy-hotplug-events=false
>
> to denote whether or not we wish to force the use of "legacy" style
> hotplug events, which
On Wed, Oct 12, 2016 at 06:13:56PM -0500, Michael Roth wrote:
> Hotplug events were previously delivered using an EPOW interrupt
> and were queued by linux guests into a circular buffer. For traditional
> EPOW events like shutdown/resets, this isn't an issue, but for hotplug
> events there are case
From: Prem Mallappa
This patch builds an IORT table that features a root complex node and
an ITS node. This complements the ITS description in the ACPI MADT
table and allows vhost-net on ACPI guest.
Signed-off-by: Prem Mallappa
Signed-off-by: Eric Auger
---
v1 -> v2:
- its_class_name() || !g
This series completes the support of MSIs for ACPI guest featuring an ITS.
It generates an ACPI IORT table which describes the IO relationship between
the root complex and the ITS. This typically enables vhost-net support on
such guest.
The series applies on top of Drew's series:
[PATCH 0/2] coup
From: Prem Mallappa
ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
introduces the definitions required to describe the IO relationship
between the PCIe root complex and the ITS.
This conforms to:
"IO Remapping Table System Software on ARM Platforms",
Document number: ARM DEN 0
This series enables virtio tests on SPAPR by starting
machines using qtest_pc_boot() or qtest_spapr_boot() to
use the good libqos PCI framework (pc or spapr).
It adds also some byte-swapping in virtio-pci.c as
PCI is always little-endian and the endianness of
the virtio device depends on the endia
vs is allocated in qvirtio_scsi_pci_init() and never freed.
Signed-off-by: Laurent Vivier
---
tests/virtio-scsi-test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/virtio-scsi-test.c b/tests/virtio-scsi-test.c
index 79088bb..94d75b1 100644
--- a/tests/virtio-scsi-test.c
+++ b/tests/
Move the definition to libqos/virtio.h as it must be used
only with virtio functions.
Add a QVirtioDevice parameter as it will be needed to
know if the virtio device is using virtio 1.0 specification
and thus is always little-endian (to do)
Signed-off-by: Laurent Vivier
---
tests/libqos/virtio-
This patch replaces calls to qtest_start() and qtest_end() by
calls to qtest_pc_boot() and qtest_shutdown().
This allows to initialize memory allocator and PCI interface
functions. This will ease to enable virtio tests on other
architectures by only adding a specific qtest_XXX_boot() (like
qtest_s
qtest_spapr_boot()/qtest_pc_boot()/qtest_boot() call qtest_vboot()
and qtest_vboot() calls g_malloc(),
and g_malloc() never fails:
if memory allocation fails, the application is terminated.
Signed-off-by: Laurent Vivier
---
tests/libqos/libqos.c | 1 +
tests/rtas-test.c | 1 -
2 files change
This allows to not have to pass bus and device for every virtio functions.
Signed-off-by: Laurent Vivier
---
tests/libqos/virtio-mmio.c | 1 +
tests/libqos/virtio-pci.c | 2 +
tests/libqos/virtio.c | 77 +++-
tests/libqos/virtio.h | 51 +++-
tests
Throughout the code there are c->listen_channel checks which manage the
listen socket file descriptor (waiting for accept(2), closing the file
descriptor, etc). These checks are currently preceded by explicit
c->method == GA_CHANNEL_UNIX_LISTEN checks.
Explicit GA_CHANNEL_UNIX_LISTEN checks are n
ga_channel_listen_accept() is currently hard-coded to support only
AF_UNIX because the struct sockaddr_un type is used. This function
should work with any address family.
Drop the sockaddr since the client address is unused and is an optional
argument to accept(2).
Signed-off-by: Stefan Hajnoczi
but disable MSI-X tests on SPAPR as we can't check the result
(the memory region used on PC is not readable on SPAPR).
Signed-off-by: Laurent Vivier
---
tests/Makefile.include| 3 ++-
tests/libqos/virtio-pci.c | 24 ++--
tests/virtio-9p-test.c| 12 +++-
tests
Add the AF_VSOCK address family so that qemu-ga will be able to use
virtio-vsock.
The AF_VSOCK address family uses address tuples. The cid is
the unique identifier comparable to an IP address. AF_VSOCK does not
use name resolution so it's easy to convert between struct sockaddr_vm
and strings.
Add AF_VSOCK (virtio-vsock) support as an alternative to virtio-serial.
$ qemu-system-x86_64 -device vhost-vsock-pci,guest-cid=3 ...
(guest)# qemu-ga -m vsock-listen -p 3:1234
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Michael Roth
---
qga/channel-posix.c | 25 +
q
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1476435295-21885-1-git-send-email-eric.au...@redhat.com
Subject: [Qemu-devel] [PATCH v2 0/2] ACPI IOR
v2:
* s/seasy/easy/ typo fix in commit description [Eric]
* Use %n to check for trailing characters in addresses [Eric]
* Added Mike's R-b
This patch series adds virtio-vsock support to the QEMU guest agent.
$ qemu-system-x86_64 -device vhost-vsock-pci,guest-cid=3 ...
(guest)# qemu-ga -m v
Hi all,
I've been trying to get GVA when the memory access instruction is
executed,so I traced a function tcg_qemu_tb_exec() and I found the address
used by ld/st operations is HVA.
I would like to know how can I transform HVA to GVA?
if I record GVA during the TB translation,will I miss some memor
* Jianjun Duan (du...@linux.vnet.ibm.com) wrote:
> Current migration code cannot handle some data structures such as
> QTAILQ in qemu/queue.h. Here we extend the signatures of put/get
> in VMStateInfo so that customized handling is supported.
>
> Signed-off-by: Jianjun Duan
> ---
> hw/display/vi
On Thu, Oct 13, 2016 at 5:12 PM, Kevin Wolf wrote:
> Am 28.09.2016 um 22:55 hat Max Reitz geschrieben:
>> Add a new option "address" to the NBD block driver which accepts a
>> SocketAddress.
>>
>> "path", "host" and "port" are still supported as legacy options and are
>> mapped to their correspond
On 10/14/2016 08:10 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:51AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> This provides access to the MMIO based Interrupt Presentation
>> Controllers (ICP) as found on a POWER8 system.
>>
>> A new XICSNative class is intr
On Thu, 10/13 19:34, Paolo Bonzini wrote:
> Ensure that there are no changes between the last check to
> bdrv_get_dirty_count and the switch to the target.
>
> There is already a bdrv_drained_end call, we only need to ensure
> that bdrv_drained_begin is not called twice.
>
> Cc: qemu-sta...@nongn
The socket(2) and accept(2) syscalls have been extended to take flags
that affect the socket atomically at creation time. This not only
avoids the overhead of additional system calls but also closes the race
condition with forking threads.
This patch adds support for the SOCK_NONBLOCK flag. QEMU
Since the lm32 is a 32 bit architecture, just return a 32 bit value which
is then converted to a 64 bit value.
Spotted by coverity, CID 1005506.
Signed-off-by: Michael Walle
---
hw/misc/milkymist-pfpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/milkymist-pfpu.c
On Thu, Oct 13, 2016 at 07:36:07PM +0100, Peter Maydell wrote:
> On 13 October 2016 at 19:29, Stefan Weil wrote:
> > scripts/tracetool generates a C preprocessor macro from the name of the
> > build directory. Any characters which are possible in a directory name
> > but not allowed in a macro nam
On 13/10/2016 21:29, Emilio G. Cota wrote:
> qht-bench: relax test_start/stop atomic accesses
>
> test_start/stop are used only as flags to loop on. Barriers are
> unnecessary,
> since no dependent data is transferred among threads apart from the flags
> themselves.
>
>
On 14/10/2016 11:43, Fam Zheng wrote:
> On Thu, 10/13 19:34, Paolo Bonzini wrote:
>> Ensure that there are no changes between the last check to
>> bdrv_get_dirty_count and the switch to the target.
>>
>> There is already a bdrv_drained_end call, we only need to ensure
>> that bdrv_drained_begin i
On Thu, Oct 13, 2016 at 08:29:30PM +0200, Stefan Weil wrote:
> scripts/tracetool generates a C preprocessor macro from the name of the
> build directory. Any characters which are possible in a directory name
> but not allowed in a macro name must be substituted, otherwise builds
> will fail.
>
> S
On Thu, 10/13 19:34, Paolo Bonzini wrote:
> bdrv_requests_pending is checking children to also wait until internal
> requests (such as metadata writes) have completed. However, checking
> children is in general overkill. Children requests can be of two kinds:
>
> - requests caused by an operatio
On 14/10/2016 11:53, Stefan Hajnoczi wrote:
> > Why does it need to care about the build directory name at all?
> > Ideally builds should be entirely deterministically reproducible
> > whatever the path to the source or build directory names is...
>
> It's trying to construct the relative path fr
On Thu, 10/13 19:34, Paolo Bonzini wrote:
> From: Fam Zheng
>
> The "need_check_timer" is used to clear the "NEED_CHECK" flag in the
> image header after a grace period once metadata update has finished. To
> comply with the bdrv_drain semantics, we should make sure it remains
> deleted once .bdr
On 10/11/2016 05:47 PM, Paolo Bonzini wrote:
>
>
> On 11/10/2016 11:21, Xiao Guangrong wrote:
>>
>>
>> On 10/11/2016 04:54 PM, Paolo Bonzini wrote:
>>>
>>>
>>> On 11/10/2016 04:39, Xiao Guangrong wrote:
On 10/11/2016 02:32 AM, Paolo Bonzini wrote:
>
>
> On 10/10/2016 20
On 14/10/2016 12:33, Fam Zheng wrote:
>> > +bdrv_aio_flush(s->bs->file->bs, qed_clear_need_check, s);
> If this one has to change, what about the other bdrv_aio_flush(s->bs, ...)
> down
> in this call path:
>
> qed_need_check_timer_cb
> qed_clear_need_check
> qed_wri
On 14/10/2016 12:42, Fam Zheng wrote:
>> > diff --git a/block/qed.c b/block/qed.c
>> > index 1a7ef0a..dcb5fb9 100644
>> > --- a/block/qed.c
>> > +++ b/block/qed.c
>> > @@ -354,7 +354,9 @@ static void qed_start_need_check_timer(BDRVQEDState *s)
>> > static void qed_cancel_need_check_timer(BDRVQED
On Thu, 10/13 19:34, Paolo Bonzini wrote:
> We want the BDS event loop to run exclusively in the iothread that
> owns the BDS's AioContext. This function and macro provides the
> synchronization between the two event loops.
>
> Signed-off-by: Paolo Bonzini
> ---
> block/block-backend.c | 7
On 14/10/2016 12:37, Jike Song wrote:
> Hi Paolo & Alex,
>
> IIUC, passing file descriptors means touching QEMU and the UAPI between
> QEMU and VFIO. Would you guys have a look at below draft patch? If it's
> on the correct direction, I'll send the split ones. Thanks!
>
> --
> Thanks,
> Jike
>
* Jianjun Duan (du...@linux.vnet.ibm.com) wrote:
> Currently we cannot directly transfer a QTAILQ instance because of the
> limitation in the migration code. Here we introduce an approach to
> transfer such structures. We created VMStateInfo vmstate_info_qtailq
> for QTAILQ. Similar VMStateInfo can
On 14/10/2016 12:44, Dr. David Alan Gilbert wrote:
>> > +#define QTAILQ_RAW_INSERT_TAIL(head, elm, entry) do {
>> > \
>> > +*((void **) ((char *) (elm) + (entry) + QTAILQ_NEXT_OFFSET)) =
>> > NULL; \
>> > +*((void **) ((char *) (elm) + (entry) + QTAILQ
Am 30.09.2016 um 21:39 hat Kevin Wolf geschrieben:
> We have been complaining for a long time about how the floppy controller and
> floppy drives are combined in a single qdev device and how this makes the
> device awkward to work with because it behaves different from all other block
> devices.
>
When vfio device is reset(encounter FLR, or bus reset), if need to do
bus reset(vfio_pci_hot_reset_one is called), vfio_pci_pre_reset &
vfio_pci_post_reset will be called twice.
Signed-off-by: Cao jin
---
Also has a little question on vfio_pci_reset. it will be called when encounter
bus reset, or
* Chunguang Li (lichungu...@hust.edu.cn) wrote:
>
>
>
> > -原始邮件-
> > 发件人: "Amit Shah"
> > 发送时间: 2016年9月30日 星期五
> > 收件人: "Chunguang Li"
> > 抄送: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org,
> > pbonz...@redhat.com, stefa...@redhat.com, quint...@redhat.com
> > 主题: Re: Re: [Qemu-deve
Signed-off-by: Igor Mammedov
---
v4:
- restore kvm_has_x2apic_api() and use it to avoid side-effects
of kvm_enable_x2apic(). x2APIC API will be enabled by iommu
if it's present or not enabled at all.
v3:
- drop kvm_has_x2apic_api() and reuse kvm_enable_x2apic() instead
---
target-i386/kvm
it would prevent starting guest with incorrect configs
where interrupts couldn't be delivered to CPUs with
APIC IDs > 255.
Signed-off-by: Igor Mammedov
Reviewed-by: Radim Krčmář
---
v4:
- s/254/255/ in commit message (Radim)
---
hw/i386/pc.c | 13 +
1 file changed, 13 insertions(+)
On Fri, Oct 14, 2016 at 10:54:54AM +0200, Eric Auger wrote:
> From: Prem Mallappa
>
> ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
> introduces the definitions required to describe the IO relationship
> between the PCIe root complex and the ITS.
>
> This conforms to:
> "IO R
On 10/12/2016 4:01 PM, Tian, Kevin wrote:
>> From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
>> Sent: Tuesday, October 11, 2016 4:29 AM
>>
> [...]
>> diff --git a/drivers/vfio/vfio_iommu_type1.c
>> b/drivers/vfio/vfio_iommu_type1.c
>> index 2ba19424e4a1..ce6d6dcbd9a8 100644
>> --- a/drivers/v
On 10/13/16 16:05, Marcel Apfelbaum wrote:
> On 10/13/2016 04:52 PM, Marcel Apfelbaum wrote:
>> Proposes best practices on how to use PCI Express/PCI device
>> in PCI Express based machines and explain the reasoning behind them.
>>
>> Signed-off-by: Marcel Apfelbaum
>> ---
>>
>> Hi,
>>
>> I am sen
The hard-coded default alignment is BDRV_SECTOR_SIZE, however this is not
necessarily the case for all platforms. Use this as the default alignment for
all current callers.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Eric Blake
Acked-by: John Snow
---
dma-helpers.c| 21 -
This is a follow-up to the thread at
https://lists.gnu.org/archive/html/qemu-devel/2016-09/msg01396.html which
introduces an explicit alignment to the DMA helpers to facilitate conversion
of the macio controller over to use the now byte-aligned DMA helpers.
Patch 1 introduces an alignment paramete
Now that the DMA helpers are byte-aligned they can be called directly from
the macio routines rather than emulating byte-aligned accesses via multiple
block-level accesses.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Eric Blake
Reviewed-by: John Snow
---
hw/ide/macio.c | 213
This small patchset fixes the incorrect behaviour of the vCont command
in the gdb stub.
The first patch, as suggested be Paolo, refactors some code. The most
visible change is that it moves vm_start to cpus.c
The second one fixes the incorrect behaviour of the vCont command.
Previously, continu
When GDB issues a "vCont", QEMU was not handling it correctly when
multiple VCPUs are active.
For vCont, for each thread (VCPU), it can be specified whether to
single step, continue or stop that thread. The default is to stop a
thread.
However, when (for example) "vCont;s:2" is issued, all VCPUs co
This patch:
* moves vm_start to cpus.c .
* exports qemu_vmstop_requested, since it's needed by vm_start .
* extracts vm_prepare_start from vm_start; it does what vm_start did,
except restarting the cpus. vm_start now calls vm_prepare_start.
* moves the call to qemu_clock_enable away from resume_
On Fri, Oct 14, 2016 at 10:54:55AM +0200, Eric Auger wrote:
> From: Prem Mallappa
>
> This patch builds an IORT table that features a root complex node and
> an ITS node. This complements the ITS description in the ACPI MADT
> table and allows vhost-net on ACPI guest.
>
> Signed-off-by: Prem Mal
Hi Drew,
On 14/10/2016 13:30, Andrew Jones wrote:
> On Fri, Oct 14, 2016 at 10:54:54AM +0200, Eric Auger wrote:
>> From: Prem Mallappa
>>
>> ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
>> introduces the definitions required to describe the IO relationship
>> between the PCIe
On Fri, 14 Oct 2016 15:43:50 +0800
Xiao Guangrong wrote:
> On 10/13/2016 09:33 PM, Igor Mammedov wrote:
> > On Wed, 12 Oct 2016 16:20:07 +0800
> > Xiao Guangrong wrote:
> >
> >> On 10/11/2016 07:49 PM, Igor Mammedov wrote:
> >>> On Mon, 10 Oct 2016 21:09:30 +0800
> >>> Xiao Guangrong wrote:
Hi Drew,
On 14/10/2016 13:57, Andrew Jones wrote:
> On Fri, Oct 14, 2016 at 10:54:55AM +0200, Eric Auger wrote:
>> From: Prem Mallappa
>>
>> This patch builds an IORT table that features a root complex node and
>> an ITS node. This complements the ITS description in the ACPI MADT
>> table and all
I need to use the SHA functions in migration/ram.c,
and I have included the head file
#include
Furthermore, I need to use flags "-lssl" and
"-lcrypto" when compile qemu, could anyone please
tell me where to add these two flags?
Thanks,
Chunguang
--
On Thu, 13 Oct 2016 18:26:41 -0300
Eduardo Habkost wrote:
> The NULL errp arguments on the property registration calls were
> changed to &error_abort.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Igor Mammedov
> ---
> backends/hostmem.c | 42 ++
> 1
On 14/10/2016 09:56, Greg Kurz wrote:
> On Thu, 13 Oct 2016 18:24:43 +0200
> Laurent Vivier wrote:
>
>> Extract the realize part to cpu_exec_realize(), update all
>> calls to cpu_exec_init() to add cpu_exec_realize() to
>> have no functionnal change.
>>
>> Put in cpu_exec_init() what initialize
On Thu, 13 Oct 2016 18:26:42 -0300
Eduardo Habkost wrote:
> To do the conversion, the file_backend_class_init() was moved
> after the getter/setter functions. The old
> file_backend_instance_init() function was removed because it is
> not needed anymore.
>
> The NULL errp arguments on the proper
Signed-off-by: Wei Wang
---
docs/specs/vhost-user.txt | 127 +++---
1 file changed, 109 insertions(+), 18 deletions(-)
diff --git a/docs/specs/vhost-user.txt b/docs/specs/vhost-user.txt
index 7890d71..195fad6 100644
--- a/docs/specs/vhost-user.txt
+++ b/do
On Thu, 13 Oct 2016 18:26:40 -0300
Eduardo Habkost wrote:
> Signed-off-by: Eduardo Habkost
Reviewed-by: Igor Mammedov
> ---
> hw/i386/pc.c | 56 ++--
> 1 file changed, 26 insertions(+), 30 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i38
In addition to the data path established using vhost-pci-net, this
patch also adds a support of establishing a notification path between
two virtio devices. New registers are added to the virtio device to
record all that's needed for its driver to inject interrupts using
hypercalls to the peer devi
On 10/14/2016 06:43 PM, Paolo Bonzini wrote:
>
>
> On 14/10/2016 12:37, Jike Song wrote:
>> Hi Paolo & Alex,
>>
>> IIUC, passing file descriptors means touching QEMU and the UAPI between
>> QEMU and VFIO. Would you guys have a look at below draft patch? If it's
>> on the correct direction, I'll
> From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
> Sent: Friday, October 14, 2016 7:36 PM
>
>
> On 10/12/2016 4:01 PM, Tian, Kevin wrote:
> >> From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
> >> Sent: Tuesday, October 11, 2016 4:29 AM
> >>
> > [...]
> >> diff --git a/drivers/vfio/vfio_iom
On Fri, 14 Oct 2016 10:54:55 +0200
Eric Auger wrote:
> From: Prem Mallappa
>
> This patch builds an IORT table that features a root complex node and
> an ITS node. This complements the ITS description in the ACPI MADT
> table and allows vhost-net on ACPI guest.
>
> Signed-off-by: Prem Mallappa
On Fri, 14 Oct 2016 10:54:54 +0200
Eric Auger wrote:
> From: Prem Mallappa
>
> ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
> introduces the definitions required to describe the IO relationship
> between the PCIe root complex and the ITS.
>
> This conforms to:
> "IO Remapp
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