On 12/16/2017 01:05 AM, Stefan Hajnoczi wrote:
The vhost-user slave device facilitates vhost-user device emulation
through vhost-user protocol exchanges and access to shared memory.
Software-defined networking, storage, and other I/O appliances can
provide services through this device.
This devi
On 19.12.2017 03:09, Mao Zhongyi wrote:
> When I follow the command line prompts to run
> "$ scripts/git-sbumodule.sh update ui/keycodemapdb dtc capstone"
>
> this is what I got:
> -bash: ./scripts/git-sbumodule.sh: No such file or directory
>
> Cc: Daniel P. Berrange
> Fixes: f62bbee55d503f639
On Sun, Dec 17, 2017 at 12:09 PM, Mark Cave-Ayland
wrote:
> On 19/11/17 11:06, Mark Cave-Ayland wrote:
>
>> On 17/11/17 14:33, Artyom Tarasenko wrote:
>>
>>> On Fri, Nov 17, 2017 at 2:42 PM, Mark Cave-Ayland
>>> wrote:
After the previous refactoring it is now possible to use separate
>>
On 18.12.2017 23:33, Cole Robinson wrote:
> As was last done in 379e21c25, we want to remove .git files for
> submodules here, which we aren't presently doing for capstone and
> keycodemapdb.
>
> Rather than a whitelist use 'find' to future proof this
>
> Signed-off-by: Cole Robinson
> ---
> sc
On 18.12.2017 17:16, Collin L. Walling wrote:
> On 12/18/2017 08:06 AM, Thomas Huth wrote:
>> On 11.12.2017 23:19, Collin L. Walling wrote:
>>> Moved:
>>> memcmp from bootmap.h to libc.h (renamed from _memcmp)
>>> strlen from sclp.c to libc.h (renamed from _strlen)
>>>
>>> Added C standard fu
Richard Henderson writes:
> On 12/11/2017 04:56 AM, Alex Bennée wrote:
>> +static inline float16 float16_set_sign(float16 a, int sign)
>> +{
>> +return make_float16((float16_val(a) & 0x7fff) | (sign << 15));
>> +}
>> +
>
> 1) Do we use this anywhere?
Yes in the target specific helpers
>
>
On Monday, 18 December 2017 22:31:40 CET Richard W.M. Jones wrote:
> On Mon, Dec 18, 2017 at 01:43:39PM -0500, John Snow wrote:
> > Hi, friendly ping:
> >
> > It's been over a month with no replies, so it's safe to say this has
> > gotten lost in the 2.11 release shuffle.
> >
> > Recommend you re
On Tue, 19 Dec 2017 17:02:59 +1100
Alexey Kardashevskiy wrote:
> On 19/12/17 14:40, Alex Williamson wrote:
> > On Tue, 19 Dec 2017 14:07:13 +1100
> > Alexey Kardashevskiy wrote:
> >
> >> On 18/12/17 16:02, Alex Williamson wrote:
> >>> With recently proposed kernel side vfio-pci changes, the
On 12/19/2017 05:46 AM, David Gibson wrote:
> On Sat, Dec 09, 2017 at 09:43:20AM +0100, Cédric Le Goater wrote:
>> Signed-off-by: Cédric Le Goater
>
> Hrm. I know I (indirectly) suggested this, but now that I see it, I'm
> thinking adding return values here but not on the read side (which
> woul
On 19/12/17 04:35, Thomas Huth wrote:
> It's a deprecated dummy device since QEMU v2.6.0. That should have
> been enough time to allow the users to update their scripts in case
> they still use it, so let's remove this legacy code now.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Alexey Kardashev
On 12/18/2017 01:59 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2017-12-14 at 16:24 +0100, Cédric Le Goater wrote:
>> The API between the source and the IVRE is extremely simple :
>>
>> static void spapr_xive_irq(sPAPRXive *xive, int lisn)
>>
>> The IVRE then scans its IVT, finds the EQ, and move
On Thu, Dec 14, 2017 at 02:52:47PM +, Stefan Hajnoczi wrote:
> On Tue, Dec 05, 2017 at 01:51:34PM +0800, Peter Xu wrote:
> > This version is mostly document update, and dropped the single patch
> > that is migration related (will be put into postcopy recovery
> > series).
>
> I've finished rev
On 19/12/17 14:40, Alex Williamson wrote:
> On Tue, 19 Dec 2017 14:07:13 +1100
> Alexey Kardashevskiy wrote:
>
>> On 18/12/17 16:02, Alex Williamson wrote:
>>> With recently proposed kernel side vfio-pci changes, the MSI-X vector
>>> table area can be mmap'd from userspace, allowing direct access
Add disas/xtensa.c and use libisa for instruction decoding/opcode name
lookup.
Signed-off-by: Max Filippov
---
MAINTAINERS | 1 +
disas/Makefile.objs | 1 +
disas/xtensa.c | 133
include/disas/bfd.h | 1 +
target/xtensa/cpu.
const16 is an opcode that shifts 16 lower bits of an address register
to the 16 upper bits and puts its immediate operand into the lower 16
bits. It is not controlled by an Xtensa option and doesn't have a fixed
opcode.
Signed-off-by: Max Filippov
---
Changes v1->v2:
- reimplement translate_const
Hi, guys.
I'm looking for the hot-plug/unplug features of virtio-9p device recently,
and found there's a lack of support.
I am wondering why ? Is there a reason. Actually, I write a qmp command to
support fsdev_add, then a device_add qmp will
successfully add a virtio-9p
GPIO32 is not in the core ISA, but it was widely used in Diamond Cores.
This implementation doesn't do actual I/O and doesn't handle the case of
GPIO32 state being a part of coprocessor.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 1 +
target/xtensa/translate.c | 53
SALT/SALTU are recent additions to the core Xtensa ISA that do
signed/unsigned setcond.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index f644d9fed22a..da1f
Add two special registers: MMID and DDR:
- MMID is write-only and the only side effect of writing to it is output
to the trace port, which is not emulated;
- DDR is only accessible in debug mode, which is not emulated.
Add two debug-mode-only opcodes:
- rfdd and rfdo do return from the debug mod
memctl SR is not available on dc232b, as it was introduced in more
recent hardware release. Now that this information is available through
the libisa the test fails. Fix the test.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_sr.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
It doesn't help much, always-set bit 0 of the LITBASE SR is easy to
compensate with decrement of the l32r immediate argument.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 27 +--
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/target/xtensa/t
Move implementations of core opcodes into separate translation
functions. Introduce data structures for mapping opcode name to
translator function. Make an array of core opcode/translator structures.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 24 +
target/xtensa/translate.c |
Extract xtensa-modules.c from the overlay, fix up known issues, include
it into the core-$NAME.c.
Signed-off-by: Max Filippov
---
Changes v1->v2:
- add sed transformation to target/xtensa/import-core.sh that drops
#include "ansidecl.h" from imported xtensa-modules.c;
target/xtensa/import_core
Replace manual opcode analysis with libisa-based code. This makes it
possible to support variable-encoding instructions of the core ISA, like
const16, and will allow to support advanced Xtensa features, like FLIX
and TIE.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h |3 +
target
Hello,
this series adds libisa to the Xtensa target, changes decoder and
instruction translators to use it, switches existing xtensa cores
to use it, adds support for a number of new instructions and adds
disassembler for Xtensa.
Libisa is the canonical way of dealing with Xtensa instructions
dec
Currently 'entry' opcode helper accepts frame size divided by 8, as it
is encoded in the opcode. Make it more natural and accept actual frame
size instead.
Signed-off-by: Max Filippov
---
target/xtensa/op_helper.c | 2 +-
target/xtensa/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 dele
The canonical way of dealing with Xtensa instructions decoding and
encoding is through the libisa. Libisa is a configuration-independent
library with a stable interface plus generated configuration-specific
xtensa-modules.c file with implementations of decoding and encoding
functions. Libisa is MIT
FPU2000 implements basic single-precision floating point operations and
can be replaced with a different implementation, like DFPU or HiFi. Move
FPU2000 opcode translators into separate functions and list them in a
separate array.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 1 +
On Fri, Dec 15, 2017 at 05:16:53PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Hi,
> Where a channel fails asynchronously during connect, call
> back through the migration code so it can clean up.
> In particular this causes the transition of a 'cancelling'
On Sun, Nov 26, 2017 at 03:59:14PM -0600, Michael Davidsaver wrote:
> Signed-off-by: Michael Davidsaver
Reviewed-by: David Gibson
But will need to be rebased on the other revised patches.
> ---
> tests/Makefile.include | 3 ++-
> tests/ds-rtc-i2c-test.c | 8
> 2 files changed, 10 in
On Sun, Nov 26, 2017 at 03:59:15PM -0600, Michael Davidsaver wrote:
> Exercise some features of the mvme3100 CPLD logic
> and read from the eeprom w/ VPD.
>
> Signed-off-by: Michael Davidsaver
Looks good, but will need a rebase.
> ---
> tests/Makefile.include | 3 ++
> tests/mvme3100-test.c
On Sun, Nov 26, 2017 at 03:59:12PM -0600, Michael Davidsaver wrote:
> split off the remaining board specific parts
> of e500_init() as mpc85xx_init() which
> will be used by the existing
> mpc8544ds and generic e500 boards.
>
> Signed-off-by: Michael Davidsaver
Looks good, but will need a rebase
On Fri, Dec 15, 2017 at 05:29:14PM +1100, Alexey Kardashevskiy wrote:
> This makes use of a new VFIO_REGION_INFO_CAP_MSIX_MAPPABLE capability
> which tells that a region with MSIX data can be mapped entirely, i.e.
> the VFIO PCI driver won't prevent MSIX vectors area from being mapped.
>
> With th
On Fri, Dec 15, 2017 at 11:51:23AM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Calling ram_bytes_remaining during the early part of setup is unsafe
> because the ram_state isn't yet initialised.
>
> This can happen in the sequence:
>migrate
>migrate_ca
On Sat, Dec 09, 2017 at 09:43:20AM +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Hrm. I know I (indirectly) suggested this, but now that I see it, I'm
thinking adding return values here but not on the read side (which
would be awkward since they return the read values) seems l
Previously virtio-net was only tested for ppc64 in "slow" mode. That
doesn't make much sense since virtio-net is used much more often in
practice than the spapr-vlan device which was tested always. So, move
virtio-net to always be tested on ppc64.
We had no tests at all for the q35 machine, whic
All of the x86 and some of the other test cases here use a common test
function, test_pxe_ipv4(), but one ppc and one s390 test use different
functions.
In the s390 case, this is completely pointless, the right parameter to
test_pxe_ipv4() will already do exactly the right thing. For the
spapr-vl
Currently pxe-tests open codes the list of tests for each architecture.
This changes it to use tables of test parameters, somewhat similar to
boot-serial-test.
This adds the machine type into the table as well, giving us the ability
to perform tests on multiple machine types for architectures wher
On Mon, Dec 18, 2017 at 11:34:07AM +0100, Thomas Huth wrote:
> On 18.12.2017 11:04, David Gibson wrote:
> > Currently pxe-tests open codes the list of tests for each architecture.
> > This changes it to use tables of test parameters, somewhat similar to
> > boot-serial-test.
> >
> > This adds the
This series makes several cleanups and enhancements to tests/pxe-test.
In particular it improves its handling of different machine types.
Please apply.
Changes since v2:
* At thuth's suggestion add bootindex=1 on all test cases, removing
the need for per-case device options.
Changes since v
This adds IPv6 net boot testing (in addition to IPv4) when in slow test
mode on ppc64 or s390. IPv6 PXE doesn't seem to work on x86, I'm guessing
our BIOS image doesn't support it.
Signed-off-by: David Gibson
Reviewed-by: Thomas Huth
---
tests/pxe-test.c | 26 --
1 file
From: Cédric Le Goater
The 'pnv' prefix is now used for all and the routines populating the
device tree start with 'pnv_dt'. The handler of the PnvXScomInterface
is also renamed to 'dt_xscom' which should reflect that it is
populating the device tree under the 'xscom@' node of the chip.
Signed-o
Because PAPR is a paravirtual environment access to certain CPU (or other)
facilities can be blocked by the hypervisor. PAPR provides ways to
advertise in the device tree whether or not those features are available to
the guest.
In some places we automatically determine whether to make a feature
From: BALATON Zoltan
Enough to please U-Boot and make it able to detect SDRAM SPD EEPROMs
Signed-off-by: François Revol
Signed-off-by: BALATON Zoltan
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/i2c/ppc4xx_i2c.c | 198 +---
inc
We currently have some conditionals in the spapr device tree code to decide
whether or not to advertise the availability of the VMX (aka Altivec) and
VSX vector extensions to the guest, based on whether the guest cpu has
those features.
This can lead to confusion and subtle failures on migration,
From: BALATON Zoltan
This is a common generic PCI SATA controller that is also used in PCs
but more importantly guests running on the Sam460ex board prefer this
card and have a driver for it (unlike for other SATA controllers
already emulated).
Signed-off-by: BALATON Zoltan
Signed-off-by: David
This adds an spapr capability bit for Hardware Transactional Memory. It is
enabled by default for pseries-2.11 and earlier machine types. with POWER8
or later CPUs (as it must be, since earlier qemu versions would implicitly
allow it). However it is disabled by default for the latest pseries-2.12
From: Greg Kurz
These two are definitely warnings. Let's use the appropriate API.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr_pci.c | 6 +++---
hw/ppc/spapr_pci_vfio.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw
Decimal Floating Point has been available on POWER7 and later (server)
cpus. However, it can be disabled on the hypervisor, meaning that it's
not available to guests.
We currently handle this by conditionally advertising DFP support in the
device tree depending on whether the guest CPU model supp
Now that the "pseries" machine type implements optional capabilities (well,
one so far) there's the possibility of having different capabilities
available at either end of a migration. Although arguably a user error,
it would be nice to catch this situation and fail as gracefully as we can.
This
From: "pbonz...@redhat.com"
We know that only one bit (in addition to SO) is going to be set in
the condition register, so do two movconds instead of three setconds,
three shifts and two ORs.
For ppc64-linux-user, the code size reduction is around 5% and the
performance improvement slightly less
From: BALATON Zoltan
These are not really implemented (just return zero or default values)
but add these so guests accessing them can run.
Signed-off-by: BALATON Zoltan
Signed-off-by: David Gibson
---
hw/display/sm501.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw
From: BALATON Zoltan
These were forgotten when adding panel layer support in ffd39257018
"SM501 emulation for R2D-SH4".
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
[dwg: Added reference to earlier commit in message]
Signed-off-by: David Gibson
---
hw/display/sm501.c | 1
When constructing the "host" cpu class we modify whether the VMX and VSX
vector extensions and DFP (Decimal Floating Point) are available
based on whether KVM can support those instructions. This can depend on
policy in the host kernel as well as on the actual host cpu capabilities.
However, the
The following changes since commit eaefea537b476cb853e2edbdc68e969ec777e4bb:
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into
staging (2017-12-18 14:17:42 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20171219
f
On 19/12/17 14:56, Alex Williamson wrote:
> On Tue, 19 Dec 2017 14:44:51 +1100
> Alexey Kardashevskiy wrote:
>
>> On 18/12/17 16:02, Alex Williamson wrote:
>>> Add one more layer to our stack of MemoryRegions, this base region
>>> allows us to register BARs independently of the vfio region or to
Hi Eduardo,
At 12/19/2017 06:09 AM, Eduardo Habkost wrote:
On Thu, Dec 14, 2017 at 12:08:53PM +0800, Dou Liyang wrote:
These are the patches left over from the pull request:
[Qemu-devel] [PULL 0/9] x86 and machine queue, 2017-10-05
because of some errors when tested by "make check" command
On Tue, 19 Dec 2017 14:44:51 +1100
Alexey Kardashevskiy wrote:
> On 18/12/17 16:02, Alex Williamson wrote:
> > Add one more layer to our stack of MemoryRegions, this base region
> > allows us to register BARs independently of the vfio region or to
> > extend the size of BARs which do map to a reg
On 18/12/17 16:02, Alex Williamson wrote:
> Add one more layer to our stack of MemoryRegions, this base region
> allows us to register BARs independently of the vfio region or to
> extend the size of BARs which do map to a region. This will be
> useful when we want hypervisor defined BARs or secti
On Tue, 19 Dec 2017 14:07:13 +1100
Alexey Kardashevskiy wrote:
> On 18/12/17 16:02, Alex Williamson wrote:
> > With recently proposed kernel side vfio-pci changes, the MSI-X vector
> > table area can be mmap'd from userspace, allowing direct access to
> > non-MSI-X registers within the host page
Signed-off-by: Haozhong Zhang
---
hw/i386/pc_piix.c| 15 ---
hw/i386/pc_q35.c | 13 +++--
include/hw/i386/pc.h | 3 +++
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 5e47528993..f235ee12c2 100644
--- a/hw/i
CPUID_7_0_EBX_CLFLUSHOPT is missed in current "Skylake-Server" cpu
model. Add it to "Skylake-Server" cpu model on pc-i440fx-2.12 and
pc-q35-2.12. Keep it disabled in "Skylake-Server" cpu model on older
machine types.
Signed-off-by: Haozhong Zhang
---
include/hw/i386/pc.h | 5 +
target/i386/c
Changes in v3:
* Rebase on QEMU 2.12.
* Add 2.12 PC machine types. Denis V. Lunev has already posted a
similar patch [1]. If that one is merged first, please ignore patch 1
in this patch series.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2017-12/msg02961.html
Haozhong Zhang (2):
On Mon, Dec 18, 2017 at 02:09:36PM +, Stefan Hajnoczi wrote:
> On Mon, Dec 18, 2017 at 05:44:19PM +0800, Peter Xu wrote:
> > On Thu, Dec 14, 2017 at 02:30:19PM +, Stefan Hajnoczi wrote:
> > > On Tue, Dec 05, 2017 at 01:51:58PM +0800, Peter Xu wrote:
> > > > diff --git a/docs/devel/qapi-code
On 18/12/17 16:02, Alex Williamson wrote:
> With recently proposed kernel side vfio-pci changes, the MSI-X vector
> table area can be mmap'd from userspace, allowing direct access to
> non-MSI-X registers within the host page size of this area. However,
> we only get that direct access if QEMU isn
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1513621179-26689-1-git-send-email-nutar...@ornl.gov
Subject: [Qemu-devel] [PATCH V9] qqq: module for synchronizing with a simulation
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BA
When I follow the command line prompts to run
"$ scripts/git-sbumodule.sh update ui/keycodemapdb dtc capstone"
this is what I got:
-bash: ./scripts/git-sbumodule.sh: No such file or directory
Cc: Daniel P. Berrange
Fixes: f62bbee55d503f639ee9498878ebf42ff4f4299a
Signed-off-by: Mao Zhongyi
---
On 19/12/17 01:28, Alex Williamson wrote:
> On Tue, 19 Dec 2017 00:55:32 +1100
> Alexey Kardashevskiy wrote:
>
>> On 19/12/17 00:28, Alex Williamson wrote:
>>> On Mon, 18 Dec 2017 20:04:23 +1100
>>> Alexey Kardashevskiy wrote:
>>>
On 18/12/17 16:02, Alex Williamson wrote:
> With re
On Mon, Dec 18, 2017 at 01:33:07PM -0500, John Snow wrote:
>
>
> On 12/18/2017 07:30 AM, BALATON Zoltan wrote:
> > On Mon, 18 Dec 2017, David Gibson wrote:
> >> On Sat, Dec 16, 2017 at 11:42:39PM +0100, BALATON Zoltan wrote:
> >>> This is a common generic PCI SATA controller that is also used in
On Thu, Dec 14, 2017 at 7:15 PM, Philippe Mathieu-Daudé wrote:
> From: Andrey Smirnov
>
> Cc: Peter Maydell
> Cc: Jason Wang
> Cc: Philippe Mathieu-Daudé
> Cc: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org
> Cc: yurov...@gmail.com
> Reviewed-by: Peter Maydell
> Signed-off-by: Andrey Smirnov
On Thu, Dec 14, 2017 at 7:15 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/sd/sdhci.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 53c1f11855
On Thu, Dec 14, 2017 at 7:15 PM, Philippe Mathieu-Daudé wrote:
> This makes the code slightly safer, also easier to review.
>
> Signed-off-by: Philippe Mathieu-Daudé
I just looked at the surrounding code and realised what mask actually
is set to. Now I understand what you mean.
Reviewed-by: Ali
On Thu, Dec 14, 2017 at 7:15 PM, Philippe Mathieu-Daudé wrote:
> add sysbus/pci/sdbus separator comments to keep it clearer
>
> Signed-off-by: Philippe Mathieu-Daudé
I'm still unsure about this. Won't this leave us with properties that
have no impact on the device? That seems very confusing to m
On Mon, Dec 18, 2017 at 12:10:41PM +0100, Greg Kurz wrote:
> On Mon, 18 Dec 2017 20:20:20 +1100
> David Gibson wrote:
>
> > This adds an spapr capability bit for Hardware Transactional Memory. It is
> > enabled by default for pseries-2.11 and earlier machine types. with POWER8
> > or later CPUs
On Mon, Dec 18, 2017 at 08:20:18PM +1100, David Gibson wrote:
> This series is a first draft to add the notion of optional
> capabilities to the "pseries" machine type. A default set of
> capabilities is selected based on the machine type version and
> selected cpu model, but this can be overridde
On Mon, Dec 18, 2017 at 04:58:02PM +0100, Greg Kurz wrote:
> These two are definitely warnings. Let's use the appropriate API.
>
> Signed-off-by: Greg Kurz
Applied to ppc-for-2.12, thanks.
> ---
> hw/ppc/spapr_pci.c |6 +++---
> hw/ppc/spapr_pci_vfio.c |2 +-
> 2 files changed, 4
On Mon, 18 Dec 2017, John Snow wrote:
On 12/18/2017 07:30 AM, BALATON Zoltan wrote:
On Mon, 18 Dec 2017, David Gibson wrote:
On Sat, Dec 16, 2017 at 11:42:39PM +0100, BALATON Zoltan wrote:
This is a common generic PCI SATA controller that is also used in PCs
but more importantly guests running
From f57cdc7ec2d5a5e906fa8b795eeede2d7b66aa56 Mon Sep 17 00:00:00 2001
From: Antonio Huete Jimenez
Date: Fri, 15 Dec 2017 01:08:10 +0100
Subject: [PATCH] sockets: Fix test for DragonFly BSD
DragonFly BSD does not implement AI_V4MAPPED for its getaddrinfo() so
probe and discard that flag instead
On 18 December 2017 at 14:35, Stefan Hajnoczi wrote:
> The following changes since commit 411ad78115ebeb3411cf4b7622784b93dfabe259:
>
> Merge remote-tracking branch
> 'remotes/stefanberger/tags/pull-tpm-2017-12-15-1' into staging (2017-12-17
> 15:27:41 +)
>
> are available in the Git repos
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1513606078-728-1-git-send-email-stef...@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH] tpm: Fix linker error when using --disable-tpm
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On 12/11/2017 04:57 AM, Alex Bennée wrote:
> +if (a.cls == float_class_zero || b.cls == float_class_zero) {
> +if (a.cls == float_class_normal) {
> +return a.sign ? float_relation_less : float_relation_greater;
> +} else if (b.cls == float_class_normal) {
> +
On 12/11/2017 04:57 AM, Alex Bennée wrote:
> +static decomposed_parts minmax_decomposed(decomposed_parts a,
> + decomposed_parts b,
> + bool ismin, bool ieee, bool ismag,
> + f
On 12/15/2017 12:15 AM, Philippe Mathieu-Daudé wrote:
> +static const struct sdhci_t {
> +const char *arch;
> +const char *machine;
> +struct {
> +uintptr_t addr;
> +uint8_t version;
> +} sdhci;
> +} models[] = {
> +{ "arm","smdkc210",
> +{0x1251,
On 12/11/2017 04:57 AM, Alex Bennée wrote:
> This is one of the simpler manipulations you could make to a floating
> point number.
>
> Signed-off-by: Alex Bennée
> ---
> fpu/softfloat.c | 104
> +++-
> include/fpu/softfloat.h | 1 +
> 2 file
On 12/11/2017 04:57 AM, Alex Bennée wrote:
> These are considerably simpler as the lower order integers can just
> use the higher order conversion function. As the decomposed fractional
> part is a full 64 bit rounding and inexact handling comes from the
> pack functions.
>
> Signed-off-by: Alex B
On 12/11/2017 04:57 AM, Alex Bennée wrote:
> +}
> +if (p.exp < DECOMPOSED_BINARY_POINT) {
> +return p.frac >> (DECOMPOSED_BINARY_POINT - p.exp);
> +} else if (p.exp < 64) {
> +return p.frac << (p.exp - DECOMPOSED_BINARY_POINT);
> +} else {
> +
Linux crashes right now if maxmem > mem is specified on the command line.
On s390x, the guest can hotplug memory itself right now - very weird -
and e.g. Fedora 27 will simply add all memory it can when booting.
So now, we have at least the same behavior on TCG and KVM.
Signed-off-by: David Hild
On 12/11/2017 04:57 AM, Alex Bennée wrote:
> We can now add float16_round_to_int and use the common round_decomposed and
> canonicalize functions to have a single implementation for
> float16/32/64 round_to_int functions.
>
> Signed-off-by: Alex Bennée
> ---
> fpu/softfloat.c | 304
> ++
Linux uses TEST PROTECTION to sense for available memory locations.
Let's implement what we can for now (just as for the other instructions,
excluding AR mode and special protection mechanisms).
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 +-
target/s390x/mem_helper.c |
While trying to fix TCG so I can properly detect memory in kvm-unit-tests
... looks like I accidentally made memory hotplug under TCG work (whoops).
qemu-system-s390x ... -m 2048,maxmem=4096M,slots=4 ...
[root@localhost ~]# cat /proc/meminfo
MemTotal:4143632 kB
MemFree: 3845248 kB
From: Richard Henderson
If we've already raised an exception (and set NORETURN),
do not emit unreachable code to raise a debug exception.
Note that gen_goto_tb takes single-stepping into account.
Signed-off-by: Richard Henderson
Message-Id: <20170907185057.23421-4-richard.hender...@linaro.org>
From: Richard Henderson
Signed-off-by: Richard Henderson
[aurel32: fix whitespace]
Message-Id: <20170907185057.23421-5-richard.hender...@linaro.org>
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 154 +
1 file changed, 78 insertions(+
From: Alex Bennée
This fixes bug #1735384 while running java under qemu-sh4. When debug
was enabled it showed a problem with TCG temps. Once fixed I was able
to run java -version normally.
Cc: qemu-sta...@nongnu.org
Reported-by: John Paul Adrian Glaubitz
Suggested-by: Richard Henderson
Signed-
From: Richard Henderson
As for other targets, cmpxchg isn't quite right for ll/sc,
suffering from an ABA race, but is sufficient to implement
portable atomic operations.
Signed-off-by: Richard Henderson
Message-Id: <20170907185057.23421-2-richard.hender...@linaro.org>
[aurel32: fix whitespace]
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-Id: <20170907185057.23421-3-richard.hender...@linaro.org>
[aurel32: fix whitespace]
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 65 +++---
1 file changed, 30 insertions(+
The following changes since commit eaefea537b476cb853e2edbdc68e969ec777e4bb:
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into
staging (2017-12-18 14:17:42 +)
are available in the Git repository at:
git://git.aurel32.net/qemu.git tags/pull-target-sh
From: Philippe Mathieu-Daudé
missed in c55497ecb8c and 852d481faf7.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20171205170013.22337-3-f4...@amsat.org>
Reviewed-by: Aurelien Jarno
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --
On 12/11/2017 04:56 AM, Alex Bennée wrote:
> +if (flags & float_muladd_halve_result) {
> +p_exp -= 1;
> +}
Indent. Otherwise, I was involved in writing this, so
Signed-off-by: Richard Henderson
r~
As was last done in 379e21c25, we want to remove .git files for
submodules here, which we aren't presently doing for capstone and
keycodemapdb.
Rather than a whitelist use 'find' to future proof this
Signed-off-by: Cole Robinson
---
scripts/make-release | 2 +-
1 file changed, 1 insertion(+), 1
On 12/11/2017 04:56 AM, Alex Bennée wrote:
> We can now add float16_div and use the common decompose and
> canonicalize functions to have a single implementation for
> float16/32/64 versions.
>
> Signed-off-by: Alex Bennée
> ---
> fpu/softfloat-macros.h | 44 +
> fpu/softfloat.c
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