[Qemu-devel] [PATCH v4 08/20] sdcard: use the registerfields API for the CARD_STATUS register masks

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- hw/sd/sd.c | 48 +--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index

[Qemu-devel] [PATCH v4 04/20] sdcard: clean the SCR register and add few comments

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sd.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 14c1cb1332..41fac9a4aa 100644 --- a/hw/sd/sd.c +++

[Qemu-devel] [PATCH v4 07/11] sdcard: define SDMMC_CMD_MAX instead of using the magic '64'

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- Since v3: add "sdmmc-internal.h" hw/sd/sdmmc-internal.h | 15 +++ hw/sd/sd.c | 22 -- 2 files changed, 31 insertions(+), 6

[Qemu-devel] [PATCH v4 10/11] sdcard: use G_BYTE from cutils

code is now easier to read. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 6760815045..28837768d4 100644 ---

[Qemu-devel] [PATCH v4 02/20] sdcard: update the CSD CRC register regardless the CSD structure version

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 9dfbd65ac8..c1ba098d86 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@

[Qemu-devel] [PATCH v4 05/11] sdcard: add more trace events

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- hw/sd/sd.c | 32 ++-- hw/sd/trace-events | 13 + 2 files changed, 39 insertions(+), 6 deletions(-) diff --git a/hw/sd/sd.c

[Qemu-devel] [PATCH v2 3/3] ppc: Add aCube Sam460ex board

Add emulation of aCube Sam460ex board based on AMCC 460EX embedded SoC. This is not a complete implementation yet with a lot of components still missing but enough for the U-Boot firmware to start and to boot a Linux kernel or AROS. Signed-off-by: François Revol Signed-off-by:

[Qemu-devel] [PATCH v4 06/11] sdcard: do not trace CMD55 when expecting ACMD

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- hw/sd/sd.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 564f7a9bfd..af4df2b104 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c

[Qemu-devel] [PATCH v2 2/3] ppc440: Add emulation of plb-pcix controller found in some 440 SoCs

This is the PCIX controller found in newer 440 core SoCs e.g. the AMMC 460EX. The device tree refers to this as plb-pcix compared to the plb-pci controller in older 440 SoCs. Signed-off-by: BALATON Zoltan --- v2: - Replace debug printfs with trace functions - Fix access of

[Qemu-devel] [PATCH v4 02/11] sdcard: replace DPRINTF() by trace events

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 32 ++-- hw/sd/trace-events | 6 ++ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index ce1f2fdf76..72e9b47e34 100644 --- a/hw/sd/sd.c +++

[Qemu-devel] [PATCH v4 03/11] sdcard: add a trace event for command responses

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 27 --- hw/sd/trace-events | 1 + 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 72e9b47e34..8f72cde534 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c

[Qemu-devel] [PATCH v4 11/11] sdcard: use the registerfields API to access the OCR register

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- include/hw/sd/sd.h | 1 - hw/sd/sd.c | 21 + 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h

[Qemu-devel] [PATCH v4 00/11] SDCard: housekeeping, add tracing (part 4)

Since v3: - use assert() in sd_state_name() and sd_response_name() (Alistair review) - added sdmmc-internal.h & sdmmc-common.c to reuse helpers with hw/sd/core.c Since v2: - split again in 2... this part is cleanup/tracing - add more tracepoints - move some code reusable by sdbus in

[Qemu-devel] [PATCH v4 01/11] sdcard: reorder SDState struct members

place card registers first, this will ease further code movements. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sd.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/sd/sd.c

[Qemu-devel] [PATCH v4 04/11] sdcard: replace fprintf() by qemu_hexdump()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sd.c | 16 +--- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 8f72cde534..ceab263970 100644 --- a/hw/sd/sd.c +++

Re: [Qemu-devel] [PATCH 2/9] nbd: change indenting in nbd.h

On 02/15/2018 07:51 AM, Vladimir Sementsov-Ogievskiy wrote: Prepared indenting for the following patch. Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/block/nbd.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) -#define

Re: [Qemu-devel] [PATCH 1/9] nbd/server: add nbd_opt_invalid helper

On 02/15/2018 07:51 AM, Vladimir Sementsov-Ogievskiy wrote: NBD_REP_ERR_INVALID is often parameter to nbd_opt_drop and it would be used more in following patches. So, let's add a helper. Signed-off-by: Vladimir Sementsov-Ogievskiy --- nbd/server.c | 50

Re: [Qemu-devel] [PATCH 6/6] sdhci-test: fix leaks

On 02/15/2018 06:25 PM, Marc-André Lureau wrote: > Fix the following ASAN reports: > > ==20125==ERROR: LeakSanitizer: detected memory leaks > > Direct leak of 24 byte(s) in 1 object(s) allocated from: > #0 0x7f0faea03a38 in __interceptor_calloc (/lib64/libasan.so.4+0xdea38) > #1

[Qemu-devel] [PATCH 6/6] sdhci-test: fix leaks

Fix the following ASAN reports: ==20125==ERROR: LeakSanitizer: detected memory leaks Direct leak of 24 byte(s) in 1 object(s) allocated from: #0 0x7f0faea03a38 in __interceptor_calloc (/lib64/libasan.so.4+0xdea38) #1 0x7f0fae450f75 in g_malloc0 ../glib/gmem.c:124 #2 0x562fffd526fc in

[Qemu-devel] [PATCH 3/6] vhost-user-test: add back memfd check

This revert commit fb68096da3d35e64c88cd610c1fa42766c58e92a, and modify test_read_guest_mem() to use different chardev names, when using memfd (_test_server_free(), where the chardev is removed, runs in idle). Signed-off-by: Marc-André Lureau ---

[Qemu-devel] [PATCH 1/6] build-sys: fix -fsanitize=address check

Since 218bb57dd79d6843e0592c30a82ea8c1fddc74a5, the -fsanitize=address check fails with: config-temp/qemu-conf.c:3:20: error: integer overflow in expression [-Werror=overflow] return INT32_MIN / -1; Interestingly, UBSAN check doesn't produce a compile time warning. Use a test that doesn't

[Qemu-devel] [PATCH 5/6] ahci-test: fix opts leak of skip tests

Fixes the following ASAN report: Direct leak of 128 byte(s) in 8 object(s) allocated from: #0 0x7fefce311850 in malloc (/lib64/libasan.so.4+0xde850) #1 0x7fefcdd5ef0c in g_malloc ../glib/gmem.c:94 #2 0x559b976faff0 in create_ahci_io_test /home/elmarco/src/qemu/tests/ahci-test.c:1810

[Qemu-devel] [PATCH 0/6] vhost-user-test and leak fixes

Hi, The following patches fix a regression introduced in commit 218bb57dd79d that prevent ASAN from being detected & used. There is also a works around for a GCC ASAN optimization bug. A few test leaks are fixed, and a few patches reenable vhost-user memfd test fixing the recent race bug that

[Qemu-devel] [PATCH 4/6] vhost-user-test: do not hang if chardev creation failed

Before the chardev name fix, the following error may happen: "attempt to add duplicate property 'chr-test' to object (type 'container')", due to races. Sadly, error_vprintf() uses g_test_message(), so you have to use read the cryptic --debug-log to see it. Later, it would make sense to use

[Qemu-devel] [PATCH 2/6] lockable: workaround GCC link issue with ASAN

Current GCC has an optimization bug when compiling with ASAN. See also GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84307 Signed-off-by: Marc-André Lureau --- include/qemu/lockable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Qemu-devel] [PATCH v4 1/2] qmp: adding 'wakeup-suspend-support' in query-target

Quoting Daniel Henrique Barboza (2018-01-05 07:03:13) > When issuing the qmp/hmp 'system_wakeup' command, what happens in a > nutshell is: > > - qmp_system_wakeup_request set runstate to RUNNING, sets a wakeup_reason > and notify the event > - in the main_loop, all vcpus are paused, a system

Re: [Qemu-devel] [PATCH 01/02] fix issue where a branch to pc+4 confuses GDB because pc and npc are set to the same value

Oh, let me also add that this assertion fails in gdb: Thread 1 hit Breakpoint 3, 0x40f102d8 in ?? () (gdb) si ./../../src/gdb-8.1/gdb/sparc-tdep.c:1737: internal-error: std::vector sparc_software_single_step(regcache*): Assertion `nnpc != npc || orig_npc == 0' failed. I had this assertion

Re: [Qemu-devel] [PATCH 01/02] fix issue where a branch to pc+4 confuses GDB because pc and npc are set to the same value

On Thursday, February 15, 2018 2:39:34 PM EST Peter Maydell wrote: > On 15 February 2018 at 19:15, Steven Seeger > These changes look rather odd -- are you sure they're right? > This is the code for unconditional taken branch, not annulled, and > my copy of the sparc architecture manual says that

Re: [Qemu-devel] [PULL 00/10] migration queue

* Peter Maydell (peter.mayd...@linaro.org) wrote: > On 14 February 2018 at 15:39, Dr. David Alan Gilbert (git) > wrote: > > From: "Dr. David Alan Gilbert" > > > > The following changes since commit bec9c64ef7be8063f1192608b83877bc5c9ea217: > > > >

Re: [Qemu-devel] [PATCH 11/27] block: x-blockdev-create QMP command

On 02/08/2018 01:23 PM, Kevin Wolf wrote: This adds a synchronous x-blockdev-create QMP command that can create qcow2 images on a given node name. We don't want to block while creating an image, so this is not the final interface in all aspects, but BlockdevCreateOptionsQcow2 and

[Qemu-devel] [PATCH 2/2] target/ppc: convert to TranslatorOps

A few changes worth noting: - Didn't migrate ctx->exception to DISAS_* since the exception field is in many cases architecturally relevant. - Moved the cross-page check from the end of translate_insn to tb_start. - Removed the exit(1) after a TCG temp leak; changed the fprintf there to

Re: [Qemu-devel] [PATCH 10/27] qcow2: Use visitor for options in qcow2_create()

On 02/08/2018 01:23 PM, Kevin Wolf wrote: Signed-off-by: Kevin Wolf --- block/qcow2.c | 219 - tests/qemu-iotests/049.out | 8 +- tests/qemu-iotests/112.out | 4 +- 3 files changed, 84 insertions(+), 147

[Qemu-devel] [PATCH 1/2] target/ppc: convert to DisasContextBase

A couple of notes: - removed ctx->nip in favour of base->pc_next. Yes, it is annoying, but didn't want to waste its 4 bytes. - ctx->singlestep_enabled does a lot more than base.singlestep_enabled; this confused me at first. Reviewed-by: Richard Henderson

[Qemu-devel] [PATCHv2 0/2] target/ppc: convert to generic translation loop

Changes from v1: - Removed use of translator_loop_temp_check; call tcg_check_temp_count directly. - Add R-b's. Thanks, Emilio

Re: [Qemu-devel] [PULL 0/7] Qio next patches

On 15 February 2018 at 17:50, Daniel P. Berrangé wrote: > The following changes since commit 8c5e7bddc22dac9d4dc3526996babce4c7242d9d: > > Merge remote-tracking branch 'remotes/huth/tags/pull-request-2018-02-14' > into staging (2018-02-15 13:00:44 +) > > are available

Re: [Qemu-devel] [PULL 00/20] target-arm queue

> > Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' > into staging (2018-02-15 15:45:33 +) > > are available in the Git repository at: > > git://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20180215-1 > > for you

Re: [Qemu-devel] [PATCH 09/27] qdict: Introduce qdict_rename_keys()

On 02/08/2018 01:23 PM, Kevin Wolf wrote: A few block drivers will need to rename .bdrv_create options for their QAPIfication, so let's have a helper function for that. Signed-off-by: Kevin Wolf --- include/qapi/qmp/qdict.h | 6 ++ qobject/qdict.c | 30

Re: [Qemu-devel] [PATCH 01/02] fix issue where a branch to pc+4 confuses GDB because pc and npc are set to the same value

On 15 February 2018 at 19:15, Steven Seeger wrote: > From ef3183a1648f45c705b55704de3755f84e9bcf80 Mon Sep 17 00:00:00 2001 > From: Steven Seeger > Date: Thu, 15 Feb 2018 13:20:04 -0500 > Subject: [PATCH 1/2] fix issue where a

[Qemu-devel] [PATCH 1/6] block: Support byte-based aio callbacks

We are gradually moving away from sector-based interfaces, towards byte-based. Add new sector-based aio callbacks for read and write, to match the fact that bdrv_aio_pdiscard is already byte-based. Ideally, drivers should be converted to use coroutine callbacks rather than aio; but that is not

Re: [Qemu-devel] [PATCH 08/27] util: Add qemu_opts_to_qdict_filtered()

On 02/08/2018 01:23 PM, Kevin Wolf wrote: This allows, given a QemuOpts for a QemuOptsList that was merged from multiple QemuOptsList, to only consider those options that exist in one specific list. Block drivers need this to separate format-layer create options from protocol-level options.

[Qemu-devel] [PATCH 3/6] null: Switch to byte-based read/write

We are gradually moving away from sector-based interfaces, towards byte-based. Make the change for the last few sector-based callbacks in the null-co and null-aio drivers. Note that since the null driver does nothing on writes, it trivially supports the BDRV_REQ_FUA flag (all writes have already

[Qemu-devel] [PATCH 5/6] vxhs: Switch to byte-based callbacks

We are gradually moving away from sector-based interfaces, towards byte-based. Make the change for the last few sector-based callbacks in the vxhs driver. Note that the driver was already using byte-based calls for performing actual I/O, so this just gets rid of a round trip of scaling; however,

[Qemu-devel] [PATCH 6/6] block: Drop last of the sector-based aio callbacks

We are gradually moving away from sector-based interfaces, towards byte-based. Now that all drivers with aio callbacks are using the byte-based interfaces, we can remove the sector-based versions. Signed-off-by: Eric Blake --- include/block/block_int.h | 6 --

[Qemu-devel] [PATCH 0/6] block: byte-based AIO read/write

While we would prefer that block drivers use coroutines instead of aio callbacks, it is a fairly easy exercise to prove that all existing drivers with aio callbacks are merely scaling from bytes into sectors and back to bytes. So, even though I am not set up to completely run (or even

[Qemu-devel] [PATCH 4/6] rbd: Switch to byte-based callbacks

We are gradually moving away from sector-based interfaces, towards byte-based. Make the change for the last few sector-based callbacks in the rbd driver. Note that the driver was already using byte-based calls for performing actual I/O, so this just gets rid of a round trip of scaling; however,

[Qemu-devel] [PATCH 2/6] file-win32: Switch to byte-based callbacks

We are gradually moving away from sector-based interfaces, towards byte-based. Make the change for the last few sector-based callbacks in the file-win32 driver. Note that the driver was already using byte-based calls for performing actual I/O, so this just gets rid of a round trip of scaling;

[Qemu-devel] [RFC PATCH 02/02] handle case of delayed control transfer couple with leading branch being conditional. need to correctly take the new branch if conditional is untaken

This patch attempts to address a crash caused by a branch in a delay slot of antoher branch causing qemu to generate an unaligned exception due to loading the instruction at 2 (aka JUMP_PC). This is RFC because I am not sure if I'm handling this correctly. The goal here is to have a delayed

[Qemu-devel] [PATCH 01/02] fix issue where a branch to pc+4 confuses GDB because pc and npc are set to the same value

>From ef3183a1648f45c705b55704de3755f84e9bcf80 Mon Sep 17 00:00:00 2001 From: Steven Seeger Date: Thu, 15 Feb 2018 13:20:04 -0500 Subject: [PATCH 1/2] fix issue where a branch to pc+4 confuses GDB because pc and npc are set to the same value Signed-off-by:

Re: [Qemu-devel] [PATCH v3 02/12] sdcard: replace DPRINTF() by trace events

Hi Alistair, On 01/31/2018 01:12 PM, Alistair Francis wrote: > On Mon, Jan 22, 2018 at 7:21 PM, Philippe Mathieu-Daudé > wrote: >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/sd/sd.c | 33 ++--- >> hw/sd/trace-events

Re: [Qemu-devel] [PATCH 2/3] qapi: Rename QMP and QGA schema files

Quoting Eric Blake (2018-02-12 10:12:11) > On 02/11/2018 03:49 AM, Markus Armbruster wrote: > > Eric Blake writes: > > > >> Having two files in the tree both named qapi-schema.json just adds > >> confusion. Rename these files, and relocate them into the common > >> qapi/

Re: [Qemu-devel] [Resend][PATCH] qga: unset frozen state if no mount points are frozen

Quoting Chen Hanxiao (2018-02-08 19:35:42) > From: Chen Hanxiao > > If we set mountpoints to qmp_guest_fsfreeze_freeze_list, > we may got nothing to freeze as all mountpoints are > not valid. > Call ga_unset_frozen in this senario. > > Cc: Michael Roth

[Qemu-devel] [PULL 19/20] bcm2836: Make CPU type configurable

From: Pekka Enberg This patch adds a "cpu-type" property to BCM2836 SoC in preparation for reusing the code for the Raspberry Pi 3, which has a different processor model. Signed-off-by: Pekka Enberg Reviewed-by: Peter Maydell

[Qemu-devel] [PULL 12/20] hw/intc/armv7m_nvic: Implement cache ID registers

M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection

[Qemu-devel] [PULL 11/20] hw/intc/armv7m_nvic: Implement v8M CPPWR register

The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no

[Qemu-devel] [PULL 07/20] target/arm: Handle SVE registers when using clear_vec_high

From: Richard Henderson When storing to an AdvSIMD FP register, all of the high bits of the SVE register are zeroed. Therefore, call it more often with is_q as a parameter. Signed-off-by: Richard Henderson Message-id:

Re: [Qemu-devel] [PATCH v3] hw/char: remove legacy interface escc_init()

On 14/02/18 04:58, David Gibson wrote: David, would you be willing to take this via ppc-for-2.12 since it covers the ESCC used in the PPC Mac machines? Short term: Yes, I can stage this. I've lost track of this thread though. Laurent, can you please resend with the various R-bs collated

[Qemu-devel] [PULL 10/20] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops

For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them.

Re: [Qemu-devel] [RFC PATCH] capstone: fix building using system package

Hi Sergei, On 02/15/2018 03:21 PM, Sergei Trofimovich wrote: > On Thu, 15 Feb 2018 14:35:39 -0300 > Philippe Mathieu-Daudé wrote: > >> #else >> +#include > > I think it's incorrect. 'pkg-config' already reports 'capstone/' path: > $ pkg-config --cflags capstone >

[Qemu-devel] [PULL 09/20] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling

The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs.

[Qemu-devel] [PULL 16/20] target/arm: Add AIRCR to vmstate struct

In commit commit 3b2e934463121 we added support for the AIRCR register holding state, but forgot to add it to the vmstate structs. Since it only holds r/w state if the security extension is implemented, we can just add it to vmstate_m_security. Signed-off-by: Peter Maydell

[Qemu-devel] [PULL 08/20] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC

Instead of hardcoding the values of M profile ID registers in the NVIC, use the fields in the CPU struct. This will allow us to give different M profile CPU types different ID register values. This commit includes the addition of the missing ID_ISAR5, which exists as RES0 in both v7M and v8M.

[Qemu-devel] [PULL 13/20] hw/intc/armv7m_nvic: Implement SCR

We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell Reviewed-by: Richard

[Qemu-devel] [PULL 01/20] hw/arm/aspeed: directly map the serial device to the system address space

From: Philippe Mathieu-Daudé (qemu) info mtree address-space: cpu-memory-0 - (prio 0, i/o): system -07ff (prio 0, rom): aspeed.boot_rom 1e60-1e7f (prio -1, i/o): aspeed_soc.io -

[Qemu-devel] [PULL 18/20] target/arm: Implement v8M MSPLIM and PSPLIM registers

The v8M architecture includes hardware support for enforcing stack pointer limits. We don't implement this behaviour yet, but provide the MSPLIM and PSPLIM stack pointer limit registers as reads-as-written, so that when we do implement the checks in future this won't break guest migration.

Re: [Qemu-devel] [PATCH] docker: dump 'config.log' if ./configure fails

On 02/15/2018 03:26 PM, Eric Blake wrote: > On 02/15/2018 11:41 AM, Philippe Mathieu-Daudé wrote: >> On 02/15/2018 02:34 PM, Daniel P. Berrangé wrote: >>> On Thu, Feb 15, 2018 at 02:23:06PM -0300, Philippe Mathieu-Daudé wrote: Suggested-by: Eric Blake Signed-off-by:

[Qemu-devel] [PULL 04/20] target/arm: Enforce FP access to FPCR/FPSR

From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20180211205848.4568-3-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell ---

[Qemu-devel] [PULL 06/20] target/arm: Enforce access to ZCR_EL at translation

From: Richard Henderson This also makes sure that we get the correct ordering of SVE vs FP exceptions. Signed-off-by: Richard Henderson Message-id: 20180211205848.4568-5-richard.hender...@linaro.org Reviewed-by: Peter Maydell

[Qemu-devel] [PULL 17/20] target/arm: Migrate v7m.other_sp

In commit abc24d86cc0364f we accidentally broke migration of the stack pointer value for the mode (process, handler) the CPU is not currently running as. (The commit correctly removed the no-longer-used v7m.current_sp flag from the VMState but also deleted the still very much in use v7m.other_sp

[Qemu-devel] [PULL 20/20] raspi: Raspberry Pi 3 support

From: Pekka Enberg This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The differences to Pi 2 are: - Firmware address - Board ID - Board revision The CPU is different too, but that's going to be configured as part of the machine default CPU when we introduce a new

[Qemu-devel] [PULL 03/20] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers

From: Richard Henderson Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. Signed-off-by: Richard Henderson Message-id: 20180211205848.4568-2-richard.hender...@linaro.org Reviewed-by: Peter Maydell

[Qemu-devel] [PULL 02/20] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io

From: Philippe Mathieu-Daudé (qemu) info mtree address-space: cpu-memory-0 - (prio 0, i/o): system -07ff (prio 0, rom): aspeed.boot_rom -1e60-1e7f (prio -1, i/o): aspeed_soc.io +

[Qemu-devel] [PULL 15/20] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions

In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR, NVIC_ISER, NVIC_ICPR, NVIC_ICER, NVIC_IABR -- in all these cases we

[Qemu-devel] [PULL 14/20] target/arm: Implement writing to CONTROL_NS for v8M

In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson

[Qemu-devel] [PULL 05/20] target/arm: Suppress TB end for FPCR/FPSR

From: Richard Henderson Nothing in either register affects the TB. Signed-off-by: Richard Henderson Message-id: 20180211205848.4568-4-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by:

[Qemu-devel] [PULL 00/20] target-arm queue

it repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180215-1 for you to fetch changes up to bade58166f4466546600d824a2695a00269d10eb: raspi: Raspberry Pi 3 support (2018-02-15 18:33:46 +) --

Re: [Qemu-devel] [PATCH v2] docs: document our stable process

On 12 February 2018 at 12:40, Cornelia Huck wrote: > Some pointers on how to get a patch into stable. > > [contains some suggestions by mdroth] > Signed-off-by: Cornelia Huck > --- > RFC/D->v2: added mdroth's suggestions > --- > docs/stable-process.rst | 67

Re: [Qemu-devel] [PATCH] docker: dump 'config.log' if ./configure fails

On 02/15/2018 11:41 AM, Philippe Mathieu-Daudé wrote: On 02/15/2018 02:34 PM, Daniel P. Berrangé wrote: On Thu, Feb 15, 2018 at 02:23:06PM -0300, Philippe Mathieu-Daudé wrote: Suggested-by: Eric Blake Signed-off-by: Philippe Mathieu-Daudé ---

Re: [Qemu-devel] [PATCH] vnc: remove bogus object_unref on client socket

Daniel P. Berrangé writes: > vnc_listen_io() does not own the reference on the 'cioc' parameter is it > passed, so should not be unref'ing it. > > Reported-by: Bandan Das > Signed-off-by: Daniel P. Berrangé Daniel, wouldn't a Fixes:

Re: [Qemu-devel] [PATCH] tests: dump config.log when configure fails in docker job

On 02/15/2018 11:16 AM, Daniel P. Berrangé wrote: When configure fails inside a docker job it is not easy to get access to the config.log file. It is nicer for developers if we just splatter the contents of config.log to stdout upon failure Suggested-by: Eric Blake

[Qemu-devel] [PATCH] target/arm: Fix register definitions for VMIDR and VMPIDR

The register definitions for VMIDR and VMPIDR have separate reginfo structs for the AArch32 and AArch64 registers. However the 32-bit versions are wrong: * they use offsetof instead of offsetoflow32 to mark where the 32-bit value lives in the uint64_t CPU state field * they don't mark

Re: [Qemu-devel] [RFC PATCH] capstone: fix building using system package

On Thu, 15 Feb 2018 14:35:39 -0300 Philippe Mathieu-Daudé wrote: > #else > +#include I think it's incorrect. 'pkg-config' already reports 'capstone/' path: $ pkg-config --cflags capstone -I/usr/include/capstone $ ls /usr/include/capstone/capstone.h

Re: [Qemu-devel] [Qemu-arm] [PATCH 2/3] hw/arm/boot: Honour CPU's address space for image loads

On 02/15/2018 03:06 PM, Peter Maydell wrote: > On 15 February 2018 at 17:57, Peter Maydell wrote: >> Instead of loading kernels, device trees, and the like to >> the system address space, use the CPU's address space. This >> is important if we're trying to load the file

Re: [Qemu-devel] [PATCH v2] docs: document our stable process

Quoting Cornelia Huck (2018-02-12 06:40:08) > Some pointers on how to get a patch into stable. > > [contains some suggestions by mdroth] > Signed-off-by: Cornelia Huck > --- > RFC/D->v2: added mdroth's suggestions > --- > docs/stable-process.rst | 67 >

Re: [Qemu-devel] [Qemu-arm] [PATCH 1/3] loader: Add new load_ramdisk_as()

On 02/15/2018 02:57 PM, Peter Maydell wrote: > Add a function load_ramdisk_as() which behaves like the existing > load_ramdisk() but allows the caller to specify the AddressSpace > to use. This matches the pattern we have already for various > other loader functions. > > Signed-off-by: Peter

Re: [Qemu-devel] [PATCH 2/3] hw/arm/boot: Honour CPU's address space for image loads

On 15 February 2018 at 17:57, Peter Maydell wrote: > Instead of loading kernels, device trees, and the like to > the system address space, use the CPU's address space. This > is important if we're trying to load the file to memory or > via an alias memory region that is

Re: [Qemu-devel] [Qemu-arm] [PATCH 3/3] hw/arm/armv7m: Honour CPU's address space for image loads

On 02/15/2018 02:57 PM, Peter Maydell wrote: > Instead of loading guest images to the system address space, use the > CPU's address space. This is important if we're trying to load the > file to memory or via an alias memory region that is provided by an > SoC object and thus not mapped into the

[Qemu-devel] [PATCH 0/3] Arm: honour CPU address space for image loads

This patchset makes the Arm code for loading kernels, initrds, etc etc honour the CPU's address space rather than loading everything via the system address space. This makes a difference when the image is being loaded to memory or via an alias memory region which is implemented by an SoC container

[Qemu-devel] [PATCH 3/3] hw/arm/armv7m: Honour CPU's address space for image loads

Instead of loading guest images to the system address space, use the CPU's address space. This is important if we're trying to load the file to memory or via an alias memory region that is provided by an SoC object and thus not mapped into the system address space. Signed-off-by: Peter Maydell

[Qemu-devel] [PATCH 2/3] hw/arm/boot: Honour CPU's address space for image loads

Instead of loading kernels, device trees, and the like to the system address space, use the CPU's address space. This is important if we're trying to load the file to memory or via an alias memory region that is provided by an SoC object and thus not mapped into the system address space.

[Qemu-devel] [PULL 7/7] allow to build with older sed

From: Jan Beulich sed's -E option may not be supported by older distros. As there's no point using sed here at all, use just shell mechanisms to establish the variable values, starting from the stem instead of the full target. Signed-off-by: Jan Beulich

[Qemu-devel] [PATCH 1/3] loader: Add new load_ramdisk_as()

Add a function load_ramdisk_as() which behaves like the existing load_ramdisk() but allows the caller to specify the AddressSpace to use. This matches the pattern we have already for various other loader functions. Signed-off-by: Peter Maydell --- include/hw/loader.h |

[Qemu-devel] [PULL 6/7] io/channel-command: Do not kill the child process after closing the pipe

From: Thomas Huth We are currently facing some migration failure on s390x when running certain avocado-vt tests, e.g. when running the test type_specific.io-github-autotest-qemu.migrate.with_reboot.exec.gzip_exec. This test is using 'migrate -d "exec:nc localhost 5200"' for the

[Qemu-devel] [PULL 3/7] io: Fix QIOChannelFile when creating and opening read-write

From: Ross Lagerwall The code wrongly passes the mode to open() only if O_WRONLY is set. Instead, the mode should be passed when O_CREAT is set (or O_TMPFILE on Linux). Fix this by always passing the mode since open() will correctly ignore the mode if it is not needed.

[Qemu-devel] [PULL 0/7] Qio next patches

The following changes since commit 8c5e7bddc22dac9d4dc3526996babce4c7242d9d: Merge remote-tracking branch 'remotes/huth/tags/pull-request-2018-02-14' into staging (2018-02-15 13:00:44 +) are available in the Git repository at: ssh://g...@github.com/berrange/qemu

[Qemu-devel] [PULL 5/7] io: Add /dev/fdset/ support to QIOChannelFile

From: Ross Lagerwall Add /dev/fdset/ support to QIOChannelFile by calling qemu_open() instead of open() and qemu_close() instead of close(). There is a subtle semantic change since qemu_open() automatically sets O_CLOEXEC, but this doesn't affect any of the users of

[Qemu-devel] [PULL 4/7] io: Don't call close multiple times in QIOChannelFile

From: Ross Lagerwall If the file descriptor underlying QIOChannelFile is closed in the io_close() method, don't close it again in the finalize() method since the file descriptor number may have been reused in the meantime. Signed-off-by: Ross Lagerwall

[Qemu-devel] [PULL 1/7] io: fix QIONetListener memory leak

From: Paolo Bonzini The sources array does not escape out of qio_net_listener_wait_client, so we have to free it. Reported by Coverity. Signed-off-by: Paolo Bonzini Signed-off-by: Daniel P. Berrange --- io/net-listener.c | 1 +

[Qemu-devel] [PULL 2/7] io/channel-websock: handle continuous reads without any data

From: Edgar Kaziakhmedov According to the current implementation of websocket protocol in QEMU, qio_channel_websock_handshake_io tries to read handshake from the channel to start communication over socket. But this approach doesn't cover scenario when socket was

Re: [Qemu-devel] [PATCH 02/11] linux-user/strace: improve sendto() output

Le 24/01/2018 à 14:01, Philippe Mathieu-Daudé a écrit : > Signed-off-by: Philippe Mathieu-Daudé > --- > linux-user/strace.c| 16 > linux-user/strace.list | 2 +- > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/linux-user/strace.c

Re: [Qemu-devel] [PATCH] docker: dump 'config.log' if ./configure fails

On 02/15/2018 02:34 PM, Daniel P. Berrangé wrote: > On Thu, Feb 15, 2018 at 02:23:06PM -0300, Philippe Mathieu-Daudé wrote: >> Suggested-by: Eric Blake >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> tests/docker/common.rc | 4 +++- >> 1 file changed, 3

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