Thanks Luke.
I tried the same from the deb of libc for arm in bionic.
Down from
real0m2.031s
to
real0m0.002s
So confirmed as well.
** Changed in: qemu (Ubuntu)
Status: Triaged => In Progress
--
You received this bug notification because you are a member of qemu-
devel-ml, which
** Changed in: qemu (Debian)
Status: Confirmed => Fix Released
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1245703
Title:
LD_PREFIX option reads directories recursively in an endless loop
Bharata B Rao wrote:
> On Thu, Apr 05, 2018 at 10:35:22AM -0400, Serhii Popovych wrote:
>> This reverts commit b556854bd8524c26b8be98ab1bfdf0826831e793.
>>
>> Leave change @node type from uint32_t to to int from reverted commit
>> because node < 0 is always false.
>>
>> Signed-off-by: Serhii Popovy
When migrating from a pre-2.9 QEMU, no clock_is_reliable flag is
transferred. We should assume that the source host has an unreliable
KVM_GET_CLOCK, rather than using whatever was determined locally, to
ensure that any drift from the TSC-based value calculated by the guest
is corrected.
Signed-off
On 25/03/18 22:11, Mark Cave-Ayland wrote:
Just to follow up on this, I spent a bit looking at what this register
is trying to do and from the Darwin source I can see that in fact it is
simply a hard-wired hardware register which should return the revision
of the UniNorth hardware.
So in fac
When migrating from a pre-2.9 QEMU, no clock_is_reliable flag is
transferred. We should assume that the source host has an unreliable
KVM_GET_CLOCK, rather than using whatever was determined locally, to
ensure that any drift from the TSC-based value calculated by the guest
is corrected.
Signed-off
On 5/4/18 6:44 pm, KONRAD Frederic wrote:
>
>
> On 04/05/2018 03:22 AM, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> Sadly I'm missing something, this does not work.
>
> Hmmm is that supposed to work dynamically?
>
> If so I think you might need to call
> me
On Thu, Apr 05, 2018 at 02:06:19PM +0200, Greg Kurz wrote:
> On Thu, 5 Apr 2018 12:14:33 +1000
> David Gibson wrote:
>
> > Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
> > MMU types, with various flag bits as well. This makes which bits of the
> > field should be c
On Thu, Apr 05, 2018 at 10:35:22AM -0400, Serhii Popovych wrote:
> This reverts commit b556854bd8524c26b8be98ab1bfdf0826831e793.
>
> Leave change @node type from uint32_t to to int from reverted commit
> because node < 0 is always false.
>
> Signed-off-by: Serhii Popovych
> ---
> hw/ppc/spapr.c
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1522980788-1252-1-git-send-email-c...@braap.org
Subject: [Qemu-devel] [PATCH v2 00/17] tcg: tb_lock_removal redux v2
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
tota
On Fri, Apr 06, 2018 at 11:00:15 +1000, Richard Henderson wrote:
> A mistake in the type passed to sizeof, that happens to work
> when the out-of-line fallback itself is using host vectors,
> but fails when using only the base types.
>
> Reported-by: Emilio G. Cota
> Signed-off-by: Richard Hender
Use mmap_lock in user-mode to protect TCG state and the page
descriptors.
In !user-mode, each vCPU has its own TCG state, so no locks
needed. Per-page locks are used to protect the page descriptors.
Per-TB locks are used in both modes to protect TB jumps.
Some notes:
- tb_lock is removed from no
Groundwork for supporting parallel TCG generation.
Instead of using a global lock (tb_lock) to protect changes
to pages, use fine-grained, per-page locks in !user-mode.
User-mode stays with mmap_lock.
Sometimes changes need to happen atomically on more than one
page (e.g. when a TB that spans acr
Use the recently-gained QHT feature of returning the matching TB if it
already exists. This allows us to get rid of the lookup we perform
right after acquiring tb_lock.
Suggested-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
docs/devel/multi-thread-tcg.txt | 3 +++
accel/tcg/cpu-exec
qht_lookup now uses the default cmp function. qht_lookup_custom is defined
to retain the old behaviour, that is a cmp function is explicitly provided.
qht_insert will gain use of the default cmp in the next patch.
Note that we move qht_lookup_custom's @func to be the last argument,
which makes th
This is only compiled under CONFIG_DEBUG_TCG to avoid
bloating the binary.
In user-mode, assert_page_locked is equivalent to assert_mmap_lock.
Note: There are some tb_lock assertions left that will be
removed by later patches.
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/
This commit does several things, but to avoid churn I merged them all
into the same commit. To wit:
- Use uintptr_t instead of TranslationBlock * for the list of TBs in a page.
Just like we did in (c37e6d7e "tcg: Use uintptr_t type for
jmp_list_{next|first} fields of TB"), the rationale is the
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the d
The acquisition of tb_lock was added when the async tlb_flush
was introduced in e3b9ca810 ("cputlb: introduce tlb_flush_* async work.")
tb_lock was there to allow us to do memset() on the tb_jmp_cache's.
However, since f3ced3c5928 ("tcg: consistently access cpu->tb_jmp_cache
atomically") all acces
This paves the way for enabling scalable parallel generation of TCG code.
Instead of tracking TBs with a single binary search tree (BST), use a
BST for each TCG region, protecting it with a lock. This is as scalable
as it gets, since each TCG thread operates on a separate region.
The core of this
The appended adds assertions to make sure we do not longjmp with page
locks held. Some notes:
- user-mode has nothing to check, since page_locks are !user-mode only.
- The checks only apply to page collections, since these have relatively
complex callers.
- Some simple page_lock/unlock callers
So that we pass a same-page range to tb_invalidate_phys_page_range,
instead of always passing an end address that could be on a different
page.
As discussed with Peter Maydell on the list [1], tb_invalidate_phys_page_range
doesn't actually do much with 'end', which explains why we have never
hit a
Thereby making it per-TCGContext. Once we remove tb_lock, this will
avoid an atomic increment every time a TB is invalidated.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/exec/tb-context.h | 1 -
tcg/tcg.h | 3 +++
accel/tc
The meaning of "existing" is now changed to "matches in hash and
ht->cmp result". This is saner than just checking the pointer value.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/qemu/qht.h| 7 +--
accel/tcg/translate-al
tb_lock was needed when the function did retranslation. However,
since fca8a500d519 ("tcg: Save insn data and use it in
cpu_restore_state_from_tb") we don't do retranslation.
Get rid of the comment.
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 4 +---
1 file changed, 1 insertio
v1: http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg06499.html
Changes since v1:
- Add R-b's
- Rebase onto master
- qht_lookup_custom: move @func to be the last argument, which
simplifies the new qht_lookup function. (I've kept R-b's tags
here because this is a very simple change.)
This greatly simplifies next commit's diff.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 77 ---
1 file changed, 39 insertions(+), 38 deletions(-)
diff --git a/accel/tcg/transl
Groundwork for supporting parallel TCG generation.
We never remove entries from the radix tree, so we can use cmpxchg
to implement lockless insertions.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
docs/devel/multi-thread-tcg.txt | 4 ++--
accel/tc
Groundwork for supporting parallel TCG generation.
Move the hole to the end of the struct, so that a u32
field can be added there without bloating the struct.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 2 +-
1 file cha
On Thu, Mar 29, 2018 at 17:06:56 +0100, Alex Bennée wrote:
>
> Emilio G. Cota writes:
>
> > tb_lock was needed when the function did retranslation. However,
> > since fca8a500d519 ("tcg: Save insn data and use it in
> > cpu_restore_state_from_tb") we don't do retranslation.
> >
> > Get rid of th
preadv/pwritev accept low and high parts of file offset in two separate
parameters. When host bitness doesn't match guest bitness these parts
must be appropriately recombined.
Introduce target_to_host_low_high that does this recombination and use
it in preadv/pwritev syscalls.
This fixes glibc tes
On Thu, Apr 05, 2018 at 03:27:34PM +0200, Cornelia Huck wrote:
> On Thu, 5 Apr 2018 15:12:55 +0200
> Greg Kurz wrote:
>
> > On Thu, 5 Apr 2018 12:14:37 +1000
> > David Gibson wrote:
>
> > > @@ -4000,7 +4000,12 @@ DEFINE_SPAPR_MACHINE(2_13, "2.13", true);
> > > * pseries-2.12
> > > */
> > >
On 04/03/2018 07:16 PM, Alex Bennée wrote:
>> +/* Set the cpu flags as per a return from an SVE helper. */
>> +static void do_pred_flags(TCGv_i32 t)
>> +{
>> +tcg_gen_mov_i32(cpu_NF, t);
>> +tcg_gen_andi_i32(cpu_ZF, t, 2);
>> +tcg_gen_andi_i32(cpu_CF, t, 1);
>> +tcg_gen_movi_i32(cp
On Thu, Mar 29, 2018 at 16:19:39 +0100, Alex Bennée wrote:
>
> Emilio G. Cota writes:
>
> > Use the recently-gained QHT feature of returning the matching TB if it
> > already exists. This allows us to get rid of the lookup we perform
> > right after acquiring tb_lock.
> >
> > Suggested-by: Richa
On 04/03/2018 07:26 PM, Alex Bennée wrote:
> You don't use it yet but probably worth a:
>
> static inline int ffr_full_reg_offset(DisasContext *s)
> {
> return pred_full_reg_offset(s, 16);
> }
>
> here when you get to it to avoid the magic 16 appearing in the main code.
Hum. Most of the pla
On Thu, Apr 05, 2018 at 10:32:04PM +0200, Daniel Vetter wrote:
> Pulling this out of the shadows again.
>
> We now also have xen-zcopy from Oleksandr and the hyper dmabuf stuff
> from Matt and Dongwong.
>
> At least from the intel side there seems to be the idea to just have 1
> special device th
On Thu, Apr 05, 2018 at 03:12:55PM +0200, Greg Kurz wrote:
> On Thu, 5 Apr 2018 12:14:37 +1000
> David Gibson wrote:
>
> > The env->slb_nr field gives the size of the SLB (Segment Lookaside Buffer).
> > This is another static-after-initialization parameter of the specific
> > version of the 64-b
A mistake in the type passed to sizeof, that happens to work
when the out-of-line fallback itself is using host vectors,
but fails when using only the base types.
Reported-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime-gvec.c | 2 +-
1 file changed, 1 insertion(+)
On 04/05/2018 03:06 PM, Thomas Huth wrote:
> On 05.04.2018 02:54, Richard Henderson wrote:
>> On 04/05/2018 10:07 AM, Richard Henderson wrote:
>>> On 04/05/2018 02:49 AM, Emilio G. Cota wrote:
1. grab this binary:
http://cs.columbia.edu/~cota/qemu/nbench-aarch64
2. run it on a Powe
On Thu, Mar 29, 2018 at 15:55:13 +0100, Alex Bennée wrote:
>
> Emilio G. Cota writes:
(snip)
> > +/* lock the page(s) of a TB in the correct acquisition order */
> > +static inline void page_lock_tb(const TranslationBlock *tb)
> > +{
> > +if (likely(tb->page_addr[1] == -1)) {
> > +pag
Hi,
On 04/05/2018 01:23 PM, Paolo Bonzini wrote:
This is my version of Daniel's patch. In order to keep the
RD/WRPROTECT check for emulated SCSI disks, I've added a new property
to scsi-disk/hd/cd devices as well. The property, similar to the
earlier versions posted by Daniel, is available to
We only emulate timer running at CPU frequency which is what most
guests expect so set the frequency to match real hardware. This also
allows setting clock multipliers which caused slowdown previously due
to wrong timer frequency.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 3 +--
hw/
On 04/05/2018 01:23 PM, Paolo Bonzini wrote:
We would like to have different behavior for passthrough devices
depending on the SCSI version they expose. To prepare for that,
allow the user of emulated devices to specify the desired SCSI
level, and adjust the emulation according to the property
I'm not on a Debian/Ubuntu-ish system, but extracting
qemu-user-static_2.11+dfsg-1ubuntu6~ppa3_amd64.deb : data.tar.xz :
usr/bin/qemu-arm-static
and testing with that binary:
$ time usr/bin/qemu-arm-static
/var/lib/archbuild/dbscripts@armv7h/luke/usr/bin/ldconfig --help
Usage: ldcon
Quoting Laszlo Ersek (2018-03-23 13:42:07)
> Michael, Peter,
>
> On 02/08/18 20:09, Michael S. Tsirkin wrote:
> > From: Laszlo Ersek
> >
> > The "i82801b11-bridge" device model is a descendant of "base-pci-bridge"
> > (TYPE_PCI_BRIDGE). However, unlike other similar devices, such as
> >
> > - p
"Peter Maydell" wrote on 04/05/2018 12:28:01
PM:
> From: "Peter Maydell"
> To: alar...@ddci.com
> Cc: "QEMU Developers"
> Date: 04/05/2018 12:28 PM
> Subject: Re: [Qemu-devel] -icount changes physical address assignments
in QEMU 2.10/2.11
>
> On 5 April 2018 at 17:44, wrote:
> > "Peter May
Unless you are using SRIOV or DPDK which both need hardware support. If
could support SRIOV, then using IOMMU+VFIO, and pass-through to VM, this
will get a close number. Or DPDK, using a user-space driver + vhost-net,
will also get a pretty good value.
--
You received this bug notification becaus
Pulling this out of the shadows again.
We now also have xen-zcopy from Oleksandr and the hyper dmabuf stuff
from Matt and Dongwong.
At least from the intel side there seems to be the idea to just have 1
special device that can handle cross-gues/host sharing for all kinds
of hypervisors, so I gues
On 28/03/2018 15:31, Laurent Vivier wrote:
> configure tries to detect if the compiler
> supports 16-byte vector operations.
>
> As stated in the comment of the detection
> program, there is a problem with the system
> compiler on GCC on Centos 7.
>
> This program doesn't actually detect the prob
- Original Message -
> From: "Peter Maydell"
> To: "Paolo Bonzini"
> Cc: "QEMU Developers" , "Alex Bennée"
> , "Richard Henderson"
> , "Emilio G. Cota" , "Pavel Dovgalyuk"
>
> Sent: Thursday, April 5, 2018 7:35:56 PM
> Subject: Re: TCG icount interaction with timer deadlines
>
> On
On Thu, 5 Apr 2018 20:46:55 +0100
"Dr. David Alan Gilbert" wrote:
> * Alex Williamson (alex.william...@redhat.com) wrote:
> > On Fri, 23 Mar 2018 15:39:39 +
> > "Dr. David Alan Gilbert (git)" wrote:
> >
> > > From: "Dr. David Alan Gilbert"
> > >
> > > My rework of section adding combine
* Alex Williamson (alex.william...@redhat.com) wrote:
> On Fri, 23 Mar 2018 15:39:39 +
> "Dr. David Alan Gilbert (git)" wrote:
>
> > From: "Dr. David Alan Gilbert"
> >
> > My rework of section adding combines overlapping or adjoining regions,
> > but checks they're actually the same underly
From: Eric Auger
Commit 567b5b309abe ("vfio/pci: Relax DMA map errors for MMIO regions")
added an error message if a passed memory section address or size
is not aligned to the page size and thus cannot be DMA mapped.
This patch fixes the trace by printing the region name and the
memory region s
The following changes since commit 0e87fdc966d05f4e5ad868034fcd8ee2a08ca62d:
Update version for v2.12.0-rc2 release (2018-04-04 20:37:20 +0100)
are available in the Git repository at:
git://github.com/awilliam/qemu-vfio.git tags/vfio-fixes-20180405.0
for you to fetch changes up to 5c0860054
On Fri, 23 Mar 2018 15:39:39 +
"Dr. David Alan Gilbert (git)" wrote:
> From: "Dr. David Alan Gilbert"
>
> My rework of section adding combines overlapping or adjoining regions,
> but checks they're actually the same underlying RAM block.
> Fix the case where two blocks adjoin but don't over
From: Jan Kiszka
Only signal MSI/MSI-X events on rising edges. So far we re-triggered the
interrupt sources even if the guest did no consumed the pending one,
easily causing interrupt storms.
Issue was observable with Linux 4.16 e1000e driver when MSI-X was used.
Vector 2 was causing interrupt s
On 5 April 2018 at 18:07, Paolo Bonzini wrote:
> On 05/04/2018 18:01, Peter Maydell wrote:
>> * however, if the guest reprograms the clock during the tcg_cpu_exec()
>>run, we don't do anything to cause us to stop earlier
>
> Anything that does this from the vCPU thread should be between
> gen
On 04/05/2018 02:25 PM, Peter Maydell wrote:
> Currently our PMSAv7 and ARMv7M MPU implementation cannot handle
> MPU region sizes smaller than our TARGET_PAGE_SIZE. However we
> report that in a slightly confusing way:
>
> DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 1
Hi Paolo,
On 04/05/2018 02:02 PM, Paolo Bonzini wrote:
> On 26/03/2018 17:05, Eduardo Otubo wrote:
>> QEMU fails when used with the following command line:
>>
>> ./ppc64-softmmu/qemu-system-ppc64 -S -machine 40p,accel=tcg -device
>> i82374
>> qemu-system-ppc64: hw/isa/isa-bus.c:110: isa_b
On 5 April 2018 at 17:44, wrote:
> "Peter Maydell" wrote on 04/05/2018 09:05:53
> AM:
>> I've just tried your attached test image ...
>
> Curious. I just downloaded qemu-2.12.0-rc2.tar.xz and built it using
> Cygwin (a version from about a month ago) using mingw compilers
> (mingw64-i686-gcc-g+
Currently our PMSAv7 and ARMv7M MPU implementation cannot handle
MPU region sizes smaller than our TARGET_PAGE_SIZE. However we
report that in a slightly confusing way:
DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10
The problem is not the alignment of the region, but
On Thu, Mar 29, 2018 at 11:06:07 +0100, Alex Bennée wrote:
> Emilio G. Cota writes:
(snip)
> > diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> > index 3a51d49..20ad3fc 100644
> > --- a/accel/tcg/translate-all.c
> > +++ b/accel/tcg/translate-all.c
> > @@ -1072,7 +1072,8 @@ void
On 04/05/2018 06:38 PM, Tony Krowiak wrote:
>> Hard to really give good advice without access to the documentation, but:
>> - If we tell the guest that the feature is available, but it does not
>> get any cards to use, returning an empty matrix makes the most sense
>> to me.
>> - I would no
On Wed, Mar 28, 2018 at 17:33:09 +0100, Alex Bennée wrote:
> Emilio G. Cota writes:
> > -bool qht_insert(struct qht *ht, void *p, uint32_t hash);
> > +void *qht_insert(struct qht *ht, void *p, uint32_t hash);
>
> Hmm this seems needlessly counter intuitive. I realise the potential
> efficiency in
On 05/04/2018 18:01, Peter Maydell wrote:
> * however, if the guest reprograms the clock during the tcg_cpu_exec()
>run, we don't do anything to cause us to stop earlier
Anything that does this from the vCPU thread should be between
gen_icount_start and gen_icount_end. (In fact, it's the ent
The legacy command line syntax supports a "password-secret" option that
allows to pass an authentication key to Ceph. This was not supported in
QMP so far.
This patch introduces authentication options in the QAPI schema, makes
them do the corresponding rados_conf_set() calls and adds compatibility
On 05/04/2018 18:09, Daniel Henrique Barboza wrote:
>>>
>> This also has to check for "s->qdev.scsi_version != -1" so that the
>> behavior of emulated SCSI isn't changed (they claim SPC-3). I made this
>> change and queued the patch.
>
> Good catch.
Since there were some more changes for emulate
On 26/03/2018 17:05, Eduardo Otubo wrote:
> QEMU fails when used with the following command line:
>
> ./ppc64-softmmu/qemu-system-ppc64 -S -machine 40p,accel=tcg -device i82374
> qemu-system-ppc64: hw/isa/isa-bus.c:110: isa_bus_dma: Assertion
> `!bus->dma[0] && !bus->dma[1]' failed.
>
On 04/05/2018 11:07 AM, Viktor Mihajlovski wrote:
Operating systems may request an IPL from a virtio-scsi device
by specifying an IPL parameter type of CCW. In this case QEMU
won't set up the IPLB correctly. The BIOS will still detect
it's a SCSI device to boot from, but it will now have to sea
"Peter Maydell" wrote on 04/05/2018 09:05:53
AM:
> From: "Peter Maydell"
> To: alar...@ddci.com
> Cc: "QEMU Developers"
> Date: 04/05/2018 09:06 AM
> Subject: Re: [Qemu-devel] -icount changes physical address assignments
in QEMU 2.10/2.11
>
> On 22 March 2018 at 05:31, wrote:
> > Your patc
On 04/03/2018 05:36 AM, Cornelia Huck wrote:
On Mon, 2 Apr 2018 12:36:27 -0400
Tony Krowiak wrote:
On 03/26/2018 05:03 AM, Pierre Morel wrote:
On 26/03/2018 10:32, David Hildenbrand wrote:
On 16.03.2018 00:24, Tony Krowiak wrote:
+/*
+ * The Query Configuration Information (QCI) fun
Le 05/04/2018 à 18:27, Max Filippov a écrit :
> On Thu, Apr 5, 2018 at 8:52 AM, Laurent Vivier wrote:
>> Why don't you try to de-construct then re-construct the offset?
>
> It would require 128-bit arithmetic on 64-bit host.
>
>> Kernel commit
>> 601cc11d054a "Make non-compat preadv/pwritev us
On 04/05/2018 11:07 AM, Viktor Mihajlovski wrote:
Splitting out the the CCW device extraction allows reuse.
Signed-off-by: Viktor Mihajlovski
---
hw/s390x/ipl.c | 81 --
1 file changed, 51 insertions(+), 30 deletions(-)
Reviewed-by:
Public bug reported:
I am using qemu-aarch64-static to run the arm64v8/openjdk official image
on my x86 machine. Using QEMU master, I immediately hit a bug which
hangs the container. With Ubuntu default version qemu-aarch64 version
2.5.0 (Debian 1:2.5+dfsg-5ubuntu10.24) and qemu-aarch64 version 2.
On Thu, Apr 5, 2018 at 8:52 AM, Laurent Vivier wrote:
> Why don't you try to de-construct then re-construct the offset?
It would require 128-bit arithmetic on 64-bit host.
> Kernel commit
> 601cc11d054a "Make non-compat preadv/pwritev use native register size"
> is interesting.
>
> static inli
On 04/05/2018 01:22 PM, Philippe Mathieu-Daudé wrote:
> On 04/05/2018 06:32 AM, Thomas Huth wrote:
>> The instance_init function of devices should always succeed to be able
>> to introspect the device. However, the instance_init function of the
>> "openprom" device can currently fail, for example l
From: Daniel Henrique Barboza
QEMU SCSI code makes assumptions about how the PROTECT and BYTCHK
works in the protocol, denying support for PI (Protection
Information) in case the guest OS requests it. However, in SCSI versions 2
and older, there is no PI concept in the protocol.
This means that
We would like to have different behavior for passthrough devices
depending on the SCSI version they expose. To prepare for that,
allow the user of emulated devices to specify the desired SCSI
level, and adjust the emulation according to the property value.
The next patch will set the level for scs
This is my version of Daniel's patch. In order to keep the
RD/WRPROTECT check for emulated SCSI disks, I've added a new property
to scsi-disk/hd/cd devices as well. The property, similar to the
earlier versions posted by Daniel, is available to the user, but for
scsi-disk/hd/cd it affects the INQ
On 04/05/2018 06:32 AM, Thomas Huth wrote:
> The instance_init function of devices should always succeed to be able
> to introspect the device. However, the instance_init function of the
> "openprom" device can currently fail, for example like this:
>
> $ echo "{'execute':'qmp_capabilities'}"\
>
On 04/05/2018 12:56 PM, Paolo Bonzini wrote:
On 27/03/2018 23:14, Daniel Henrique Barboza wrote:
/* We get here only for BYTCHK == 0x01 and only for scsi-block.
* As far as DMA is concerned, we can treat it the same as a write;
* scsi_block_do_sgio will send VER
Does anybody understand how icount TCG is supposed to arrange to
respect timer deadlines?
https://bugs.launchpad.net/qemu/+bug/1754038 has a test case which
shows that we don't get this right.
At the moment what happens is:
* when we're about to call tcg_cpu_exec(), we call
prepare_icount_for
On 27/03/2018 23:14, Daniel Henrique Barboza wrote:
> /* We get here only for BYTCHK == 0x01 and only for scsi-block.
> * As far as DMA is concerned, we can treat it the same as a write;
> * scsi_block_do_sgio will send VERIFY commands.
> + *
> + * For s
Le 05/04/2018 à 15:47, Max Filippov a écrit :
> preadv/pwritev accept low and high parts of file offset in two separate
> parameters. When host bitness doesn't match guest bitness these parts
> must be appropriately recombined.
> Introduce target_to_host_low_high that does this recombination and us
On 27/03/2018 18:41, Fam Zheng wrote:
> Some backends report big max_io_sectors. Making min_io_size the same
> value in this case will make it impossible for guest to align memory,
> therefore the disk may not be usable at all.
>
> Do not enlarge them when they are zero.
>
> Reported-by: David Gi
On 27/03/2018 17:09, Thomas Huth wrote:
> We forgot to mention --with-git, --libexecdir and --with-pkgversion
> so far.
>
> Signed-off-by: Thomas Huth
> ---
> configure | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/configure b/configure
> index 4d0e92c..a473609 100755
> --- a/conf
On 30/03/2018 19:02, Roman Kagan wrote:
> In order to guarantee compatibility on migration, QEMU should have
> complete control over the features it announces to the guest via CPUID.
>
> However, a number of Hyper-V-related features happen to depend on the
> support in the underlying KVM, with no
On 28/03/2018 22:48, Justin Terry (VM) wrote:
> 1. (As the code is doing now). At partition creation time you can
> register for specific CPUID exits and then respond to the CPUID with
> your custom answer or with the Hypervisor defaults that were forwarded
> to you. Unfortunately, QEMU has no way
On 28/03/2018 14:18, Marc-André Lureau wrote:
> On RHEL7, memfd is not supported, and vhost-user-test fails:
> TEST: tests/vhost-user-test... (pid=10248)
> /x86_64/vhost-user/migrate:
> qemu-system-x86_64: -object memory-backend-memfd,id=mem,size=2M,: failed to
> create memfd
> FAIL
>
> There
On 05.04.2018 17:11, David Hildenbrand wrote:
> On 05.04.2018 17:07, Viktor Mihajlovski wrote:
>> IPL over a virtio-scsi device requires special handling not
>> available in the real architecture. For this purpose the IPL
>> type 0xFF has been chosen as means of communication between
>> QEMU and th
On 05.04.2018 17:07, Viktor Mihajlovski wrote:
> IPL over a virtio-scsi device requires special handling not
> available in the real architecture. For this purpose the IPL
> type 0xFF has been chosen as means of communication between
> QEMU and the pc-bios. However, a guest OS could be confused
> b
Splitting out the the CCW device extraction allows reuse.
Signed-off-by: Viktor Mihajlovski
---
hw/s390x/ipl.c | 81 --
1 file changed, 51 insertions(+), 30 deletions(-)
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index fdeaec3..58e33c5 1
IPL over a virtio-scsi device requires special handling not
available in the real architecture. For this purpose the IPL
type 0xFF has been chosen as means of communication between
QEMU and the pc-bios. However, a guest OS could be confused
by seeing an unknown IPL type.
This change sets the IPL p
Operating systems may request an IPL from a virtio-scsi device
by specifying an IPL parameter type of CCW. In this case QEMU
won't set up the IPLB correctly. The BIOS will still detect
it's a SCSI device to boot from, but it will now have to search
for the first LUN and attempt to boot from there.
IPL from virtio-scsi currently uses a non-standard parameter
type definition to pass boot parameters from QEMU to the
BIOS.
There are two potential issues with this approach:
o If the guest operating systems requests a re-ipl of type CCW
where the boot device is a virtio-scsi HBA, this goes unno
Now PowerPC Linux kernel supports hot-add to NUMA nodes not populated
initially with memory we can enable such support in qemu. This requires
two changes:
o Add device tree property "ibm,max-associativity-domains" to let
guest kernel chance to find max possible NUMA node
o Revert commit
Now recent kernels (i.e. since linux-stable commit a346137e9142
("powerpc/numa: Use ibm,max-associativity-domains to discover possible nodes")
support this property to mark initially memory-less NUMA nodes as "possible"
to allow further memory hot-add to them.
Advertise this property for pSeries m
This reverts commit b556854bd8524c26b8be98ab1bfdf0826831e793.
Leave change @node type from uint32_t to to int from reverted commit
because node < 0 is always false.
Signed-off-by: Serhii Popovych
---
hw/ppc/spapr.c | 22 --
1 file changed, 22 deletions(-)
diff --git a/hw/pp
On Wed, Apr 04, 2018 at 05:55:57PM +0200, Thomas Huth wrote:
> On 04.04.2018 17:49, Paolo Bonzini wrote:
> > On 04/04/2018 17:33, Thomas Huth wrote:
> >> The 'vlan' term caused a lot of confusion in the past, so let's try
> >> to switch to the better word "hub" everywhere where it is appropriate.
>
On 29 March 2018 at 11:54, Peter Maydell wrote:
> On 23 March 2018 at 12:08, Peter Maydell wrote:
>> On 21 March 2018 at 08:00, Shannon Zhao wrote:
>>> On 2018/3/20 19:54, Peter Maydell wrote:
Can you still successfully migrate a VM from a QEMU version
without this bugfix to one with t
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