On 05/11/2018 06:59 AM, Peter Xu wrote:
> On Fri, May 11, 2018 at 12:02:48AM +0200, Cédric Le Goater wrote:
>> On the POWER9 processor, the XIVE interrupt controller can control
>> interrupt sources using MMIO to trigger events, to EOI or to turn off
>> the sources. Priority management and interrup
On 11.05.2018 05:52, Richard Henderson wrote:
> Also do not dump both "fpu" and "vector" registers
> as the former overlaps the latter.
>
> Cc: Alexander Graf
> Cc: David Hildenbrand
> Signed-off-by: Richard Henderson
> ---
> target/s390x/helper.c | 23 ---
> 1 file changed
On 11.05.2018 02:43, Richard Henderson wrote:
> This is now handled properly by the generic softfloat code.
>
> Cc: Alexander Graf
> Cc: David Hildenbrand
> Signed-off-by: Richard Henderson
> ---
> target/s390x/fpu_helper.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
Richard Henderson writes:
> Move the ifdef inside the relevant functions instead of
> duplicating the function declarations.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
> ---
> fpu/softfloat-specialize.h | 100 +++--
> 1 file changed, 40 inse
Hello David,
Yesterday evening, I forgot to add the quote requested by Peter and
to add the MIPS maintainers.
Could you please add the paragraph below if the patch is accepted ?
I think it's worth resending a v4 for that.
Thanks,
C.
On 05/11/2018 12:02 AM, Cédric Le Goater wrote:
> On the PO
On Wed, 05/09 10:17, Eric Blake wrote:
> On 05/09/2018 09:58 AM, Fam Zheng wrote:
> > Just pass down to ->file.
> >
> > Signed-off-by: Fam Zheng
> > Reviewed-by: Stefan Hajnoczi
> > ---
> > block/raw-format.c | 20
> > 1 file changed, 20 insertions(+)
> >
> > diff --git
'test.hex' file is a bare metal ARM software stored in Hexadecimal
Object Format. When it's loaded by QEMU, it will print "Hello world!\n"
on console.
`pre_store` array in 'hexloader-test.c' file, stores the binary format
of 'test.hex' file, which is used to verify correctness.
Reviewed-by: Stefa
These series of patchs implement Intel Hexadecimal File loader and
add QTest testcase to verify the correctness of Loader.
v1:
-- Basic version.
v2:
-- Replace `do{}while(cond);` block with `for(;;)` block.
v3:
-- Add two new files information in MAINTAINERS.
v4:
-- Correct the 'test.hex' p
This patch adds Intel Hexadecimal Object File format support to
the loader. The file format specification is available here:
http://www.piclist.com/techref/fileext/hex/intel.htm
The file format is mainly intended for embedded systems
and microcontrollers, such as Micro:bit Arduino, ARM, STM32, et
On Fri, May 11, 2018 at 12:02:48AM +0200, Cédric Le Goater wrote:
> On the POWER9 processor, the XIVE interrupt controller can control
> interrupt sources using MMIO to trigger events, to EOI or to turn off
> the sources. Priority management and interrupt acknowledgment is also
> controlled by MMIO
On Thu, May 10, 2018 at 8:52 PM, Richard Henderson
wrote:
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/translate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Acked-by: Max Filippov
--
Thanks.
-- Max
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 66e493220e..3866106bf6 100644
--- a/target/openrisc/transl
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 116 +--
target/openrisc/insns.decode | 12
2 files changed, 70 insertions(+), 58 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 359 +--
target/openrisc/insns.decode | 21 ++
2 files changed, 149 insertions(+), 231 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 120 +--
target/openrisc/insns.decode | 15 +
2 files changed, 73 insertions(+), 62 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 322 +++
target/openrisc/insns.decode | 76 ++---
2 files changed, 229 insertions(+), 169 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/tra
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 41
target/openrisc/insns.decode | 3 +++
2 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 279 +++
target/openrisc/insns.decode | 35 -
2 files changed, 151 insertions(+), 163 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/transla
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 55 +++-
target/openrisc/insns.decode | 5
2 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 62 +++-
target/openrisc/insns.decode | 6
2 files changed, 32 insertions(+), 36 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
From: Richard Henderson
The architecture manual is unclear about this, but the or1ksim
does writeback before the exception. This requires splitting
the helpers in half, with the exception raised by the second.
Acked-by: Stafford Horne
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Hen
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 275 +--
target/openrisc/insns.decode | 24 +++
2 files changed, 160 insertions(+), 139 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 149 +--
target/openrisc/insns.decode | 12 +++
2 files changed, 83 insertions(+), 78 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
Stafford Horne has acked and asked that I send the pull-request.
r~
The following changes since commit e5cd695266c5709308aa95b1baae499e4b5d4544:
Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into
staging (2018-05-08 17:05:58 +0100)
are available in the Git repository
Begin with the 0x08 major opcode, the system instructions.
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 79 +--
target/openrisc/Makefile.objs | 9
target/openrisc/insns.decode | 28 +
3 files cha
Cc: Guan Xuetao
Signed-off-by: Richard Henderson
---
target/unicore32/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 5b51f2166d..63619e7d2c 100644
--- a/target/unicore32/translate.c
+++ b/target
Cc: Alexander Graf
Cc: David Gibson
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2a4140f420..fd66c80cc7 100644
--- a/target/ppc/translat
Cc: Aurelien Jarno
Cc: Yongbok Kim
Signed-off-by: Richard Henderson
---
target/mips/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d05ee67e63..136947adc5 100644
--- a/target/mips/translate.c
+++ b/target/
Cc: Max Filippov
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 4f6d03059f..2afe395ecf 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/tran
Cc: Mark Cave-Ayland
Cc: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target/sparc/cpu.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ff6ed91f9a..0f090ece54 100644
--- a/target/sparc/cpu.c
+++ b/tar
Also do not dump both "fpu" and "vector" registers
as the former overlaps the latter.
Cc: Alexander Graf
Cc: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/helper.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target/s390x/h
Signed-off-by: Richard Henderson
---
target/alpha/helper.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 8a6a948572..57e2c212b3 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -442,20 +44
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target/riscv/cpu.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e5a56d4e3..4612f324c9 1
With Peter's new patch for "-d fpu", it makes sense to honor
this setting in as many targets as currently dump the fpu.
r~
Richard Henderson (9):
target/alpha: Honor CPU_DUMP_FPU
target/mips: Honor CPU_DUMP_FPU
target/ppc: Honor CPU_DUMP_FPU
target/riscv: Introduce cpu_riscv_get_fcsr
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h| 1 +
target/riscv/fpu_helper.c | 6 ++
target/riscv/op_helper.c | 3 +--
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target
From: Alex Bennée
All the hard work is already done by vfp_expand_imm, we just need to
make sure we pick up the correct size.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Alex Bennée
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
Signed-off-by: Richar
From: Alex Bennée
We are meant to explicitly pass fpst, not cpu_env.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/targ
From: Alex Bennée
These where missed out from the rest of the half-precision work.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Alex Bennée
[rth: Diagnose lack of FP16 before fp_access_check]
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 2 +
targ
From: Alex Bennée
These were missed out from the rest of the half-precision work.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Alex Bennée
[rth: Fix erroneous check vs type]
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 31 +
No sense in emitting code after the exception.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 10d3856351..edb4dc243f 100644
--- a/target/arm/translat
We missed all of the scalar fp16 binary operations.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 65 ++
1 file changed, 65 insertions(+)
diff --git a/target/arm/translate-a64.c b/target
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 6 +++
target/arm/helper.c| 38 ++-
target/arm/translate-a64.c | 96 +++---
3 files changed, 122 insertions(+), 18 deletions(
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 14f35e878a..eb69a548e1 100644
-
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 30 ++
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index eb69a548e1..031
We missed all of the scalar fp16 fma operations.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/ar
Changes since v2:
* Rebased vs target-arm.next.
* Merged Peter's review.
* Split out return fix as a separate patch.
Changes since v1:
* Rebased vs master instead of tgt-arm-sve-9.
* Alex did some additional digging through the ARM xhtml
and came up with some additional missing instr
Adding the fp16 moves to/from general registers.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b0471c842e..10d3856
On 04/27/2018 10:22 AM, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> When running the gcc testsuite with current aarch64-linux-user,
>> the testsuite detects the presence of the fp16 extension and
>> enables lots of extra tests for builtins.
>>
>> Quite a few of these new tests fail bec
For each operand, pass a single enumeration instead of a pair of booleans.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 70 +++---
fpu/softfloat.c| 11 +++---
2 files changed, 31 insertions(+), 50 deletions(-)
diff --git a/fpu/sof
This is now handled properly by the generic softfloat code.
Cc: Alexander Graf
Cc: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/fpu_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_help
This is now handled properly by the generic softfloat code.
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target/riscv/fpu_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/f
For each operand, pass a single enumeration instead of a pair of booleans.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 168 ++---
fpu/softfloat.c| 35
2 files changed, 98 insertions(+), 105 deletions(-)
diff --git a/fpu
This is now handled properly by the generic softfloat code.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 1 -
target/arm/helper.c | 12 ++--
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 976e
Cc: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/softfloat.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c
index e41b07d042..6ec227e20f 100644
--- a/target/m68k/softfloat.c
+++ b/target/m68k/softfloat.c
This is now handled properly by the generic softfloat code.
Signed-off-by: Richard Henderson
---
target/hppa/op_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index a3af62daf7..912e8d5be4 100644
--- a/target/hppa/op_helper.c
+++ b/
Only MIPS requires snan_bit_is_one to be variable. While we are
specializing softfloat behaviour, allow other targets to eliminate
this runtime check.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h| 57 ---
include/fpu/softfloat-types.h | 1
With a canonical representation of NaNs, we can return the
default nan directly rather than delay the expansion until
the final format is known.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 37 +
fpu/softfloat.c| 38 +++
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 6 +++---
target/arm/helper.c | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index afb25ad20c..976eaba37a 100644
--- a/target/arm/helper-a64.c
+
With a canonical representation of NaNs, we can silence an SNaN
immediately rather than delay until the final format is known.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 23 +
fpu/softfloat.c| 51 +++---
2 files c
These functions are now unused.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 63 --
include/fpu/softfloat.h| 5 ---
2 files changed, 68 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 08ab8181d
The new function assumes that the input is an SNaN and
does not double-check.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 174 +
include/fpu/softfloat.h| 5 ++
2 files changed, 123 insertions(+), 56 deletions(-)
diff --git a/fpu/so
We have already checked the arguments for SNaN;
we don't need to do it again.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 44 +-
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-sp
We want to be able to specialize on the canonical representation.
Signed-off-by: Richard Henderson
---
fpu/softfloat.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index e7c8213a5e..5e4982b035 100644
--- a/fpu/softfl
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 15 +++
fpu/softfloat.c| 12 ++--
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index b59356f6a5..82d7a030e7 100644
--- a/fp
This is now handled properly by the generic softfloat code.
Cc: Aurelien Jarno
Cc: Yongbok Kim
Signed-off-by: Richard Henderson
---
target/mips/msa_helper.c | 4
target/mips/op_helper.c | 2 --
2 files changed, 6 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helpe
Move the ifdef inside the relevant functions instead of
duplicating the function declarations.
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 100 +++--
1 file changed, 40 insertions(+), 60 deletions(-)
diff --git a/fpu/softfloat-specialize.h b
This is intended to address Peter's comments wrt Alex's float-to-float
conversion patches. In particular, the handling of NaNs therein, where
some SNaN get converted to Inf instead of the appropriate QNaN.
I canonicalize NaNs within FloatParts much like we do with the original
softfpu commonNaNT.
Shift the NaN fraction to a canonical position, much like we do
for the fraction of normal numbers. Immediately, this simplifies
the float-to-float conversion. Later, this will facilitate
manipulation of NaNs within the shared code paths.
Signed-off-by: Richard Henderson
---
fpu/softfloat.c |
Hi there,
my name is Steffen. I am a master candidate in electrical engineering at
RWTH University in Aachen, Germany.
Together with Julia Suvorova i will work on Cortex-M0 / BBC micro:bit
support in QEMU this summer. This endeavor will supervised by Stefan
Hajnoczi, Jim Mussared and Joel Stanley.
The F10 key is used in various applications, disable it unconditionally
(do not limit it to grab mode). Note that this property is deprecated
and might be removed in the future (GTK+ commit b082fb598d).
Fixes: https://bugs.launchpad.net/qemu/+bug/1726910
Signed-off-by: Peter Wu
---
ui/gtk.c | 6
Saves some space and disables the F10 button as side-effect.
Fixes: https://bugs.launchpad.net/qemu/+bug/1726910
Signed-off-by: Peter Wu
---
ui/gtk.c | 46 +-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/ui/gtk.c b/ui/gtk.c
index bb321
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180510222601.19944-1-laur...@vivier.eu
Subject: [Qemu-devel] [PATCH 0/5] linux-user: move socket.h definitions to CPU
directories
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BA
No code change.
Signed-off-by: Laurent Vivier
---
linux-user/socket.h | 44 +---
linux-user/sparc/sockbits.h | 94 +++
linux-user/sparc64/sockbits.h | 1 +
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644
No code change.
Signed-off-by: Laurent Vivier
---
linux-user/alpha/sockbits.h | 113
linux-user/socket.h | 106 +
2 files changed, 114 insertions(+), 105 deletions(-)
create mode 100644 linux-user/alpha
No code change.
Signed-off-by: Laurent Vivier
---
linux-user/ppc/sockbits.h | 58 +++
linux-user/socket.h | 11 +
2 files changed, 59 insertions(+), 10 deletions(-)
create mode 100644 linux-user/ppc/sockbits.h
diff --git a/linux-user/pp
Values defined for sparc are not correct.
Copy the content of "arch/sparc/include/uapi/asm/socket.h"
to fix them.
Signed-off-by: Laurent Vivier
---
linux-user/sparc/sockbits.h | 161
1 file changed, 89 insertions(+), 72 deletions(-)
diff --git a/linu
No code change.
Signed-off-by: Laurent Vivier
---
linux-user/mips/sockbits.h | 110 +++
linux-user/mips64/sockbits.h | 1 +
linux-user/socket.h | 106 +
3 files changed, 113 insertions(+), 104 deletions(
Splitting out socket.h definitions helps to read the code
and to fix the bugs...
No code change, except for the last one that ports
definitions from linux for sparc as the values are not the
correct ones.
Laurent Vivier (5):
linux-user: move mips socket.h definitions to mips/sockbits.h
linux-
Hi,
My name is Julia. I am a bachelor of mathematics from Moscow who is
interested in system programming. I've been selected for Outreachy this
year to work on the micro:bit project.
The project is divided between two people - me and Steffen.
We will develop support for the micro:bit board and the
On the POWER9 processor, the XIVE interrupt controller can control
interrupt sources using MMIO to trigger events, to EOI or to turn off
the sources. Priority management and interrupt acknowledgment is also
controlled by MMIO in the presenter sub-engine.
These MMIO regions are exposed to guests in
Hello David,
On 05/10/2018 09:15 PM, Dr. David Alan Gilbert wrote:
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
>> On 9 May 2018 at 12:08, Dr. David Alan Gilbert wrote:
>>> This thread seems to have stalled; we've got the list of potential
>>> migration breaks that Peter found and only som
On Mon, Apr 23, 2018 at 20:31:15 -0400, Emilio G. Cota wrote:
> On Fri, Apr 13, 2018 at 17:42:45 -1000, Richard Henderson wrote:
> > On 04/05/2018 04:13 PM, Emilio G. Cota wrote:
> > > +static __thread bool page_collection_locked;
> > > +
> > > +void assert_page_collection_locked(bool val)
> > > +{
On Mon, Apr 23, 2018 at 20:27:36 -0400, Emilio G. Cota wrote:
> On Fri, Apr 13, 2018 at 17:31:20 -1000, Richard Henderson wrote:
> > On 04/05/2018 04:13 PM, Emilio G. Cota wrote:
> > > +#ifdef CONFIG_DEBUG_TCG
> > > +
> > > +struct page_lock_debug {
> > > +const PageDesc *pd;
> > > +QLIST_E
On Thu, May 10, 2018 at 10:08:50AM +0800, junyan...@gmx.com wrote:
> From: Junyan He
>
> As more flag parameters besides the existing 'share' are going to be
> added to following functions
> memory_region_init_ram_from_file
> qemu_ram_alloc_from_fd
> qemu_ram_alloc_from_file
> let's switch
On Tue, May 8, 2018 at 10:57 PM, Fam Zheng wrote:
> On Mon, 05/07 13:09, Alistair Francis wrote:
>> Avocado is not trivial to setup on non-Fedora systems. To simplfying
>> future testing add a docker test image that runs Avocado tests.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> tests/docker
On Tue, May 8, 2018 at 8:49 AM, Philippe Mathieu-Daudé wrote:
> Hi Alistair,
>
> On 05/07/2018 09:02 PM, Philippe Mathieu-Daudé wrote:
>>> On 05/07/2018 05:09 PM, Alistair Francis wrote:
> [...]>>> +++ b/tests/docker/test-avocado
@@ -0,0 +1,28 @@
+#!/bin/bash -e
+#
+# Avocado t
On Mon, May 7, 2018 at 5:02 PM, Philippe Mathieu-Daudé wrote:
> On 05/07/2018 07:44 PM, Philippe Mathieu-Daudé wrote:
>> Hi Alistair,
>>
>> On 05/07/2018 05:09 PM, Alistair Francis wrote:
>>> Avocado is not trivial to setup on non-Fedora systems. To simplfying
>>> future testing add a docker test
This is a follow up
of patch:
commit c2e3dee6e03527baf8698698cce76b1a3174969a
Author: Laurent Vivier
Date: Sun Feb 13 23:37:34 2011 +0100
linux-user: Define target alignment size
In my case m68k aligns "int" on 2 not 4. You can check this with the
following
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 15
This series enables the TOPOEXT feature for AMD CPUs. This is required to
support hyperthreading on kvm guests.
This addresses the issues reported in these bugs:
https://bugzilla.redhat.com/show_bug.cgi?id=1481253
https://bugs.launchpad.net/qemu/+bug/1703506
v8:
Addressed feedback from Eduardo.
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-
From: Eduardo Habkost
Instead of having a collection of macros that need to be used in
complex expressions to build CPUID data, define a CPUCacheInfo
struct that can hold information about a given cache. Helper
functions will take a CPUCacheInfo struct as input to encode
CPUID leaves for a cache
The property legacy-cache will be used to control the cache information.
If user passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information. Otherwise
use the statically loaded cache definitions if available.
Signed-off-by: Babu Moger
Tested-
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
---
target/i386/cpu.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d97b290b08.
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 1 +
target/i386/cpu.h | 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 188
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
---
include/hw/i386/topology.h
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
Current QEMU code (at least, v2.12.0-329-ge5cd695266) does not grab the
F10 key ("menubar activate"), accelerators (Ctrl-Alt-1) or menu bar
"mnemonic"s (such as Alt-V for _V_iew).
This comment nicely summarizes what kind of grabs is needed:
https://bugzilla.redhat.com/show_bug.cgi?id=499362#c1
Thi
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On 9 May 2018 at 12:08, Dr. David Alan Gilbert wrote:
> > This thread seems to have stalled; we've got the list of potential
> > migration breaks that Peter found and only some minor comments on the
> > actual patch.
> >
> > I'd like to get it go
Hi Paolo,
On 04/24/2018 10:01 PM, Philippe Mathieu-Daudé wrote:
> Hi Christian,
>
> On 04/09/2018 04:18 AM, Christian Ehrhardt wrote:
>> Re-Ping for consideration?
>>
>> On Mon, Jan 22, 2018 at 3:03 PM, Christian Ehrhardt <
>> christian.ehrha...@canonical.com> wrote:
>>
>>> Hi,
>>> maybe I missed
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