> From: Samuel Thibault [mailto:samuel.thiba...@gnu.org]
> Pavel Dovgalyuk, le jeu. 26 juil. 2018 11:37:57 +0300, a ecrit:
> > > From: Samuel Thibault [mailto:samuel.thiba...@gnu.org]
> > > Pavel Dovgalyuk, le jeu. 26 juil. 2018 10:08:29 +0300, a ecrit:
> > > > virtual clock should be used by the v
> From: Dr. David Alan Gilbert [mailto:dgilb...@redhat.com]
> * Pavel Dovgalyuk (pavel.dovga...@ispras.ru) wrote:
> > This patch introduces 'info replay' monitor command and
> > corresponding qmp request.
> > These commands request the current record/replay mode, replay log file name,
> > and the e
On Mon, 30 Jul 2018 11:58:13 -0500
Michael Roth wrote:
> Quoting Christian Borntraeger (2018-07-30 10:31:12)
> > Are we still able to get things into 2.12.1 or are we too late?
>
> Freeze is EOD today, but I can grab them if they hit master/rc3 tomorrow.
OK, I just sent a pull request with th
From: Christian Borntraeger
We clamp down ram_size to match the sclp increment size. We do
not do the same for maxram_size, which means for large guests
with some sizes (e.g. -m 5) maxram_size differs from ram_size.
This can break other code (e.g. CMMA migration) which uses maxram_size
to cal
The following changes since commit 18a398f6a39df4b08ff86ac0d38384193ca5f4cc:
Update version for v3.0.0-rc2 release (2018-07-24 22:06:31 +0100)
are available in the Git repository at:
git://github.com/cohuck/qemu tags/s390x-20180731
for you to fetch changes up to 408e5ace517ff18c9c7cd918fc93
On Tue, Jul 31, 2018 at 06:57:31AM +0200, Sebastian Bauer wrote:
> Am 2018-07-31 02:18, schrieb David Gibson:
> > > David, can you please drop this patch, we'll come up with a
> > > different fix.
> > Done. Should have looked at that patch a bit closer.
>
> I created a follow up patch, unfortunat
Eric Blake writes:
> On 07/30/2018 03:34 AM, Markus Armbruster wrote:
>> Eric Blake writes:
>>
>> [...]
>>> (We really want to assert that any % interpolations in our JSON parser
>>> are NOT embedded in '').
>>
>> I'll look into that, but it'll be in a separate series.
>
> Agreed. In fact, my m
r11 is a volatile register on PPC as per calling conventions.
The safe_syscall code uses it to check if the signal_pending
is set during the safe_syscall. When a syscall is interrupted
on return from signal handling, the r11 might be corrupted
before we retry the syscall leading to a crash. The reg
Eric Blake writes:
> On 07/25/2018 11:17 AM, Markus Armbruster wrote:
>
>>>
>>> the output was produced by bash, which uses waitpid() - and therefore
>>> the fact that bash reports the core dump even when no core file is
>>> created is promising.
>>
>> Proof beats plausibility argument:
>>
>> $ c
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180730162458.23186-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH 0/5] mps2: Implement FPGAIO counters and dual-timer
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=b
Am 2018-07-31 01:15, schrieb Peter Maydell:
It would work. But creating an OR gate is half a dozen lines or so of
code, so it's not much more work than changing the PCI controller.
So we should prefer whichever is closest to what the real hardware
does, assuming we can determine that.
The real
Am 2018-07-31 02:18, schrieb David Gibson:
David, can you please drop this patch, we'll come up with a different
fix.
Done. Should have looked at that patch a bit closer.
I created a follow up patch, unfortunately, based on the previous patch,
as I did not spot your mail earlier than now. No
This is done by unfolding the sysbus_create_varargs() call and by
announcing that only a single irq is needed before connecting the irqs
before the bus is initialized.
This should model the design of the SAM board better, which is that all
PCI interrupts are connected to a single interrupt pin, in
This can be done by using the newly introduced num_irqs property. In
particular, this change introduces a special case if num_irqs is 1 in which
case any interrupt pin will be connected to the single irq. The default
case is untouched (but note that the only client is the Sam460ex board for
which t
The previous change 70a8ff3fd0c27e69a598e7603112de9d0fec5380 fixed
the interrupt connection not properly as the IRQ levels would not
be logcical or'ed. While other PCI cards already have worked with
that change, it didn't model the expected hardware behaviour
close enough.
This patch series is an
On Mon, Jul 30, 2018 at 10:41:45AM +0200, Greg Kurz wrote:
> On Mon, 30 Jul 2018 15:57:15 +1000
> David Gibson wrote:
>
> > On Fri, Jul 27, 2018 at 09:54:52AM +0200, Greg Kurz wrote:
> > > On Fri, 27 Jul 2018 15:27:24 +1000
> > > David Gibson wrote:
> > >
> > > > On Wed, Jul 25, 2018 at 04:45
On Mon, Jul 30, 2018 at 11:59:00AM +0200, Greg Kurz wrote:
> On Mon, 30 Jul 2018 10:41:45 +0200
> Greg Kurz wrote:
>
> > On Mon, 30 Jul 2018 15:57:15 +1000
> > David Gibson wrote:
> [...]
> > > > > I'm pretty sure trying to change the accelerator on a qtest test just
> > > > > doesn't make sense
Add an example on how to use the create command. I believe this will make
qemu-img easier to use.
Signed-off-by: John Arbuckle
---
qemu-img-cmds.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-img-cmds.hx b/qemu-img-cmds.hx
index 69758fb6e8..92f7437944 100644
--- a/q
Hi,
This series failed docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180730192955.14291-1-programmingk...@gmail.com
Subject: [Qemu-devel] [PATCH] Add intera
Yeah, I suspect (but haven't tested) that this applies to all BSDs. We
could switch CONFIG_DARWIN to CONFIG_BSD (happy to resend the patch, just
LMK).
Agreed that platform-specific ifdefs are gross, but I don't see a better
way here :/ One option would be to look at the packet length and content
When the user uses the --help option in qemu-img, the output for the commands
is very hard to read due to being so close to each other. With this patch the
help for the commands is double spaced making things easier to read.
Signed-off-by: John Arbuckle
---
qemu-img.c | 2 +-
1 file changed, 1 i
On Mon, 30 Jul 2018 21:16:35 +0200
Laurent Vivier wrote:
> Le 30/07/2018 à 14:44, Richard Henderson a écrit :
> [...]
> [...]
> [...]
> [...]
> [...]
> [...]
> [...]
>
> Tested-by: Laurent Vivier
> Reviewed-by: Laurent Vivier
>
> I think this patch should go into the next
On Tue, Jul 31, 2018 at 01:31:46AM +0200, BALATON Zoltan wrote:
> On Tue, 31 Jul 2018, Peter Maydell wrote:
> > On 30 July 2018 at 23:37, BALATON Zoltan wrote:
> > QEMU's implementation of qemu_irq signal lines is that the destination
> > end provides the qemu_irq, which under the hood is a pointe
On Tue, 31 Jul 2018, Peter Maydell wrote:
On 30 July 2018 at 23:37, BALATON Zoltan wrote:
QEMU's implementation of qemu_irq signal lines is that the destination
end provides the qemu_irq, which under the hood is a pointer to a
struct containing a pointer to the function in the destination device
On 31 July 2018 at 00:00, BALATON Zoltan wrote:
> On Mon, 30 Jul 2018, Peter Maydell wrote:
>>
>> On 30 July 2018 at 12:06, BALATON Zoltan wrote:
>>> I don't understand QOM. Does this really work? It will ultimately do
>>>
>>> qdev_connect_gpio_out_named(dev, SYSBUS_DEVICE_GPIO_IRQ, 0, uic[1][0])
If a vfio assigned device makes use of a physical IOMMU, then memory
ballooning is necessarily inhibited due to the page pinning, lack of
page level granularity at the IOMMU, and sufficient notifiers to both
remove the page on balloon inflation and add it back on deflation.
However, not all devices
Remove KVM specific tests in balloon_page(), instead marking
ballooning as inhibited without KVM_CAP_SYNC_MMU support.
Signed-off-by: Alex Williamson
---
accel/kvm/kvm-all.c|4
hw/virtio/virtio-balloon.c |4 +---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a
We use a VFIOContainer to associate an AddressSpace to one or more
VFIOGroups. The VFIOContainer represents the DMA context for that
AdressSpace for those VFIOGroups and is synchronized to changes in
that AddressSpace via a MemoryListener. For IOMMU backed devices,
maintaining the DMA context for
A simple true/false internal state does not allow multiple users. Fix
this within the existing interface by converting to a counter, so long
as the counter is elevated, ballooning is inhibited.
Signed-off-by: Alex Williamson
---
balloon.c | 13 ++---
1 file changed, 10 insertions(+),
v2:
- Use atomic ops for balloon inhibit counter (Peter)
- Allow endpoint driver opt-in for ballooning, vfio-ccw opt-in by
default, vfio-pci opt-in by device option, only allowed for mdev
devices, no support added for platform as there are no platform
mdev devices.
See patch 3/4 for det
On Mon, 30 Jul 2018, Peter Maydell wrote:
On 30 July 2018 at 12:06, BALATON Zoltan wrote:
On Mon, 30 Jul 2018, Sebastian Bauer wrote:
The four interrupts of the PCI bus are connected to the same UIC pin on
the
real Sam460ex. Evidence for this can be found in the UBoot source for the
Sam460ex
On 30 July 2018 at 23:37, BALATON Zoltan wrote:
> I think the number of irq lines could be set, the functions have an nirq or
> num_irq parameters so the 4 lines is only assumed because PCI defines that
> and this is what's modelled but we could use different value here. Sam460ex
> seems to connec
On 30 July 2018 at 12:06, BALATON Zoltan wrote:
> On Mon, 30 Jul 2018, Sebastian Bauer wrote:
>>
>> The four interrupts of the PCI bus are connected to the same UIC pin on
>> the
>> real Sam460ex. Evidence for this can be found in the UBoot source for the
>> Sam460ex in the Sam460ex.c file where P
On Mon, 30 Jul 2018, Sebastian Bauer wrote:
Am 2018-07-30 13:06, schrieb BALATON Zoltan:
On Mon, 30 Jul 2018, Sebastian Bauer wrote:
The four interrupts of the PCI bus are connected to the same UIC pin on
the
real Sam460ex. Evidence for this can be found in the UBoot source for the
Sam460ex in
On Mon, Jul 30, 2018 at 9:24 AM, Peter Maydell wrote:
> In the MPS2 FPGAIO, PSCNTR is a free-running downcounter with
> a reload value configured via the PRESCALE register, and
> COUNTER counts up by 1 every time PSCNTR reaches zero.
> Implement these counters.
>
> We can just increment the counte
In kill_qemu() we have an assert that checks that the QEMU process
didn't dump core:
assert(!WCOREDUMP(wstatus));
Unfortunately the WCOREDUMP macro here means the resulting message
is not very easy to comprehend on at least some systems:
ahci-test: tests/libqtest.c:113: kill_qemu: Ass
On 07/30/2018 09:43 AM, Alex Bennée wrote:
> I've slightly re-organised the check to more closely match the
> sequence that the kernel uses in do_mmap(). We check for both the zero
> case (EINVAL) and the overflow length case (ENOMEM).
>
> Signed-off-by: Alex Bennée
> Cc: umarcor <1783...@bugs.la
On 07/24/2018 01:44 AM, Thomas Huth wrote:
Furthermore, we are NOT detecting EINTR (while EINTR shouldn't be
happening if we didn't install signal handlers, it's still better
to always be robust), and also want to log unexpected non-zero status
that was not accompanied by a core dump.
On Sat, Jul 28, 2018 at 09:50:05AM +0200, Niels de Vos wrote:
> On Sat, Jul 28, 2018 at 12:18:39AM -0400, Jeff Cody wrote:
> > On Fri, Jul 27, 2018 at 08:24:05AM -0500, Eric Blake wrote:
> > > On 07/27/2018 03:19 AM, Niels de Vos wrote:
> > > >From: Prasanna Kumar Kalever
> > > >
> > > >New versio
On 07/25/2018 11:17 AM, Markus Armbruster wrote:
the output was produced by bash, which uses waitpid() - and therefore
the fact that bash reports the core dump even when no core file is
created is promising.
Proof beats plausibility argument:
$ cat wcordump.c
$ gcc -Wall -g -O wcordump.c
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180730162458.23186-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH 0/5] mps2: Implement FPGAIO counters and dual-timer
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=b
Tested by booting linux 4.18 (built using imx_v6_v7_defconfig) on the
emulated board.
Signed-off-by: Jean-Christophe Dubois
---
Changes in V3:
* None
Changes in V2:
* use object_initialize_child instead of several funcions
hw/arm/Makefile.objs | 2 +-
hw/arm/mcimx6ul-evk.c | 85 ++
Signed-off-by: Jean-Christophe Dubois
---
Changes in V3:
* Fix coding style issue with indent.
Changes in V2:
* use object_initialize_child instead of several funcions
* use sysbus_init_child_obj instead for several functions
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs
This series adds the i.MX6UL SOC from NXP/Freescale and the reference
evaluation board.
This series was tested by booting linux 4.18 (built using imx_v6_v7_defconfig)
on the emulated board (with the appropriate device tree).
Jean-Christophe Dubois (3):
i.MX6UL: Add i.MX6UL specific CCM device
Signed-off-by: Jean-Christophe Dubois
---
Changes in V3:
* None
Changes in V2:
* move all CCM "debug" to the "trace" framework for i.MX6UL
* remove unecessary breaks
* prevent g_assert_not_reached triggered by guest.
* Add assert to help static analyzer.
* use FIELD_EX32 from hw/registerfi
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> case NM_P16_LB:
> +rd = extract32(ctx->opcode, 0, 2);
> +switch (extract32(ctx->opcode, 2, 2)) {
...
> case NM_P16_LH:
> +rd = extract32(ctx->opcode, 1, 2) << 1;
> +switch ((extract32(ctx->opcode, 3, 1) <
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Add emulation of misc nanoMIPS 16-bit instructions.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 41 +++
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Add emulation of nanoMIPS 16-bit shift instructions.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 15 +++
> 1 file
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Add emulation of nanoMIPS 16-bit branch instructions.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 36 +
> On Jul 30, 2018, at 3:48 PM, Eric Blake wrote:
>
> On 07/30/2018 02:14 PM, John Arbuckle wrote:
>> Changes qemu-img so if the user runs it without any
>> arguments, it will walk the user thru making an image
>> file.
>
> Please remember to cc qemu-devel on ALL patches, as suggested by
> ./s
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> +case NM_P16_A2:
> +switch (extract32(ctx->opcode, 3, 1)) {
> +case NM_ADDIUR2:
> +rd = extract32(ctx->opcode, 0, 3) << 2;
> +gen_arith_imm(ctx, OPC_ADDIU, rt, rs, rd);
> +break;
> +
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add some basic utility functions and macros for nanoMIPS decoding
> engine.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add empty body and invocation of decode_nanomips_opc() if the bit
> ISA_NANOMIPS32 is set in ctx->insn_flags.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Mark switch fallthroughs with comments, in cases fallthroughs
> are intentional.
>
> The comments "/* fall through */" are interpreted by compilers and
> other tools, and they will not issue warnings in such cases
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Fix two instances of shadow variables. This cleans up entire file
> translate.c from shadow variables.
>
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 4
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Stefan Markovic
>
> Add gen_op_addr_addi(). This function will be used in emulation of
> some nanoMIPS instructions.
>
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 12
Hello Richard,
the signed overflow computation for 64-bit saturated subtraction in
do_sat_addsub_64 looks wrong: I think the second xor should use t1
instead of t0.
Thanks,
Laurent
On Mon, Jul 30, 2018 at 11:41:41AM +0200, Igor Mammedov wrote:
> Commit 848a1cc1e (hw/acpi-build: build SRAT memory affinity structures for
> DIMM devices)
> broke the first dimm hotplug in following cases:
>
> 1: there is no coldplugged dimm in the last numa node
> but there is a coldplugge
Implementing clone for sparc requires that we make modifications
to both the parent and child cpu state. In all other cases, the
new argument can be ignored.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_cpu.h| 3 ++-
linux-user/alpha/target_cpu.h | 3 ++-
linux-user/a
Or really, just clone devolving into fork. This should not ever happen
in practice. We do want to reserve calling cpu_clone_regs for the case
in which we are actually performing a clone.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 7 +--
1 file changed, 5 insertions(+), 2 d
As seen as the very first instruction of sys_clone in the kernel.
Ideally this would be done in or before cpu_copy, and not with a
separate explicit test vs the syscall number, but this is a more
minimal solution.
Signed-off-by: Richard Henderson
---
linux-user/sparc/cpu_loop.c | 3 +++
1 file
There are at least 4 separate bugs preventing clone from working.
(1) cpu_copy left both cpus sharing the same register window (!)
(2) cpu_clone_regs did not initialize %o1, so the new thread path
in the guest __clone was always taken, even for the parent
(old %o1 value was newsp, and so
We failed to set the secondary return value in %o1
we failed to advance the PC past the syscall, and
we failed to adjust regwptr into the new structure.
Signed-off-by: Richard Henderson
---
linux-user/sparc/target_cpu.h | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
On Mon, Jul 30, 2018 at 11:16:38AM +0200, David Hildenbrand wrote:
> On 27.07.2018 14:55, Cornelia Huck wrote:
> > On Wed, 25 Jul 2018 11:12:33 +0200
> > David Hildenbrand wrote:
> >
> >> The "max" CPU model behaves like "-cpu host" when KVM is enabled, and like
> >> a CPU with the maximum possib
On 07/30/2018 02:14 PM, John Arbuckle wrote:
Changes qemu-img so if the user runs it without any
arguments, it will walk the user thru making an image
file.
Please remember to cc qemu-devel on ALL patches, as suggested by
./scripts/getmaintainer.pl.
Signed-off-by: John Arbuckle
---
qemu
Changes qemu-img so if the user runs it without any
arguments, it will walk the user thru making an image
file.
Signed-off-by: John Arbuckle
---
qemu-img.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 9b7506b8a
On Mon, Jul 30, 2018 at 10:07:27AM -0500, Eric Blake wrote:
> On 07/28/2018 02:50 AM, Niels de Vos wrote:
> >>
> >>Part of me wishes that libgfapi had just created a new function
> >>'glfs_ftruncate2', so that existing users don't need to handle the api
> >>change. But I guess in the grand scheme,
Le 30/07/2018 à 14:44, Richard Henderson a écrit :
> On 07/30/2018 06:09 AM, Shivaprasad G Bhat wrote:
>> r11 is a volatile register on PPC as per calling conventions.
>> The safe_syscall code uses it to check if the signal_pending
>> is set during the safe_syscall. When a syscall is interrupted
>>
Fix committed and sent upstream:
https://github.com/qemu/qemu/commit/73bb753d24a702b37913ce4b5ddb6dca40dab067
** Changed in: qemu
Status: New => Fix Committed
** Changed in: qemu
Assignee: (unassigned) => Tristan Burgess (tburgessdev)
--
You received this bug notification because yo
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: cover.1532963204.git@tribudubois.net
Subject: [Qemu-devel] [PATCH v2 0/3] i.MX: Add the i.MX6UL SOC and a reference
board.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=ba
Ping
On 07/05/2018 05:08 PM, Daniel Henrique Barboza wrote:
changes in v8:
- created 'query-current-machine' API to hold the wakeup-suspend-support
flag
- wake-up flag now considers the --no-acpi config option for PC archs
- fixes in patch 3 proposed by Markus.
Previous series link:
https://l
Sorry, I should have been clearer. Please can you provide a test case
binary and QEMU command line that reproduces the problem (including what
the expected output is and what the actual output is)?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscrib
On 30 July 2018 at 19:20, Philippe Mathieu-Daudé wrote:
> Before this patch:
>
> $ ./configure
>
> ERROR: Unsupported CPU = riscv64, try --enable-tcg-interpreter
>
> $ ./configure --enable-tcg-interpreter
> Unsupported CPU = riscv64, will use TCG with TCI (experimental)
>
> [...]
>
> WARNING: SUPP
On 30 July 2018 at 18:24, Alistair Francis wrote:
> On Sun, Jul 29, 2018 at 4:28 AM, Peter Maydell
> wrote:
>>> Another piece that even Michael Clark does not have is
>>> linux-user/host/*/safe-syscall.S.
>>
>> It might be nice to complete the safe-syscall stuff for all hosts,
>> and then remove
Hello,
Let me explain a bit how to reproduce the problem. I'm developing a RTOS
with qemu (and boards,etc) -
https://sourceforge.net/projects/rtospharos/. The first version used
ARM926 with the versatilepb board and I used the qemu 2.5 version.
In my test (to check that the RTOS is working correc
On 07/27/2018 08:49 PM, Alistair Francis wrote:
> Allow QEMU to be built to run on a RISC-V host.
>
> QEMU does not yet have a RISC-V TCG or user mode target port, but
> running other architectures on RISC-V using TCI does work.
>
> Signed-off-by: Alistair Francis
> ---
> configure | 18 +++
The following changes since commit 6d9dd5fb9d0e9f4a174f53a0e20a39fbe809c71e:
>
> Merge remote-tracking branch
> 'remotes/armbru/tags/pull-qobject-2018-07-27-v2' into staging (2018-07-30
> 09:55:47 +0100)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-a
On 25 July 2018 at 06:30, Hongbo Zhang wrote:
> The fw_cfg value returned from fw_cfg_find() may be NULL, so check it
> before using.
>
> Signed-off-by: Hongbo Zhang
> ---
> hw/arm/boot.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
Use an int64_t as a return type to restore
the negative check for arm_load_as.
Signed-off-by: Adam Lackorzynski
---
hw/arm/boot.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index e09201cc97..ca9467e583 100644
--- a/hw/arm/boot.c
+++
On 25 July 2018 at 09:59, Stefan Hajnoczi wrote:
> From: Su Hang
>
> This patch adds Intel Hexadecimal Object File format support to the
> loader. The file format specification is available here:
> http://www.piclist.com/techref/fileext/hex/intel.htm
>
> This file format is often used with micro
> From: Aleksandar Markovic
>
> v4->v5:
>
> - merged series "Mips maintenance and misc fixes and improvements"
> and this one for easier handling (there are build dependencies)
> - eliminated shadow variables from translate.c
> - replaced shift/mask combination with extract32()
> - a
From: Aleksandar Rikalo
Add signal trampoline support for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/signal.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/linux-user/mip
On Sun, Jul 29, 2018 at 4:28 AM, Peter Maydell wrote:
> On 28 July 2018 at 17:36, Richard Henderson
> wrote:
>> On 07/27/2018 04:49 PM, Alistair Francis wrote:
>>> Allow QEMU to be built to run on a RISC-V host.
>>>
>>> QEMU does not yet have a RISC-V TCG or user mode target port, but
>>> running
Quoting John Snow (2018-07-23 17:22:03)
> This is an updated version of Vladimir's proposal for fixing the
> handling around migration and persistent dirty bitmaps.
Are these still being considered for 3.0 rc3/rc4? 2.12.1 releases this week
and I'm not sure how badly these are needed.
>
> Patche
From: Benjamin Herrenschmidt
This is a model of the PCIe Host Bridge (PHB3) found on a Power8
processor. It includes the PowerBus logic interface (PBCQ), IOMMU
support, a single PCIe Gen.3 Root Complex, and support for MSI and LSI
interrupt sources as found on a Power8 system using the XICS inter
From: Dimitrije Nikolic
This header includes common elf header, and adds cpu_get_model()
function.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_elf.h | 14 ++
1 file changed, 14 insertions(+)
cr
From: Dimitrije Nikolic
Add target_structs.h header for nanoMIPS, that redirects to the
corresponding MIPS header.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_structs.h | 1 +
1 file changed, 1 insertion(+)
On 27 July 2018 at 10:54, Luc Michel wrote:
> v5:
> - Patch 7: dropped unreachable 'return NULL' [Peter]
> - Patch 12: reworked the way invalid vIRQ are handled. The
> specification being uncleared, I used real hardware to check our
> previous hypothesises. See commit message for the a
From: Aleksandar Rikalo
Amend sigaction syscall support for nanoMIPS. This must be done
since nanoMIPS' signal handling is different than MIPS' signal
handling.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall.c | 2 +-
On 25 July 2018 at 09:59, Stefan Hajnoczi wrote:
> Define a "cortex-m0" ARMv6-M CPU model.
>
> Most of the register reset values set by other CPU models are not
> relevant for the cut-down ARMv6-M architecture.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> target/arm/cpu.c | 11 +++
> 1 fil
On 07/30/2018 01:06 PM, Michael Roth wrote:
> Quoting John Snow (2018-07-23 17:22:03)
>> This is an updated version of Vladimir's proposal for fixing the
>> handling around migration and persistent dirty bitmaps.
>
> Are these still being considered for 3.0 rc3/rc4? 2.12.1 releases this week
>
On Mon, Jul 30, 2018 at 10:42:05AM -0600, Alex Williamson wrote:
> On Mon, 30 Jul 2018 18:49:58 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Mon, Jul 30, 2018 at 09:01:37AM -0600, Alex Williamson wrote:
> > > > > but I don't think it can be done
> > > > > atomically with respect to inflight DMA o
From: Aleksandar Rikalo
Add termbits.h header for nanoMIPS. Reuse MIPS' termbits.h as
the functionalities are almost identical.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/termbits.h | 4
linux-user/nanomips/
Le 30/07/2018 à 18:11, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> Add MIPS machine variants ELF flags so that the emulation behavior
> can be adjusted if needed.
>
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> Reviewed-by: Richard Henderson
> ---
>
Quoting Christian Borntraeger (2018-07-30 10:31:12)
> Are we still able to get things into 2.12.1 or are we too late?
Freeze is EOD today, but I can grab them if they hit master/rc3 tomorrow.
>
>
> On 07/30/2018 04:09 PM, Christian Borntraeger wrote:
> > We clamp down ram_size to match the sclp
On 25 July 2018 at 09:59, Stefan Hajnoczi wrote:
> ARMv6-M and ARMv8-M need the same kernel loading functionality as
> ARMv7-M. Rename armv7m_load_kernel() to arm_m_profile_load_kernel() so
> it's clear that this function isn't specific to ARMv7-M.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> hw/
On 27 July 2018 at 06:26, Philippe Mathieu-Daudé wrote:
> Hi Stefan,
>
> On 07/25/2018 05:59 AM, Stefan Hajnoczi wrote:
>> Define a "cortex-m0" ARMv6-M CPU model.
>>
>> Most of the register reset values set by other CPU models are not
>> relevant for the cut-down ARMv6-M architecture.
>>
>> Signed
From: Aleksandar Markovic
Update constants and structures related to syscall support in
nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall_defs.h | 57 ++-
1 file chan
From: Aleksandar Rikalo
Add nanoMIPS-related values in ELF header fields as specified in
nanoMIPS' "ELF ABI Supplement".
Acked-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 20
1 file changed, 20 insertions(+)
On 25 July 2018 at 09:59, Stefan Hajnoczi wrote:
> The TYPE_ARMV7M class is really a container for an ARM M Profile CPU,
> NVIC, and related pieces. It can also be used for ARMv6-M and ARMv8-M.
> Rename the class since it is not exclusive to ARMv7-M.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> h
1 - 100 of 342 matches
Mail list logo
