On Mon, Aug 13, 2018 at 08:00:19PM +0100, Dr. David Alan Gilbert wrote:
> cc'ing in Mike*2
> * Denis Plotnikov (dplotni...@virtuozzo.com) wrote:
> >
> >
> > On 26.07.2018 12:23, Peter Xu wrote:
> > > On Thu, Jul 26, 2018 at 10:51:33AM +0200, Paolo Bonzini wrote:
> > > > On 25/07/2018 22:04,
Max Reitz writes:
> On 2018-08-13 08:15, Markus Armbruster wrote:
>> Max Reitz writes:
>>
>>> On 2018-08-10 08:28, Markus Armbruster wrote:
Marc-André Lureau writes:
> Spotted by ASAN:
>
> =
>
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1463143
Title:
Kernel
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1463463
Title:
PCI
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1462944
Title:
vpc file
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1437367
Title:
Qemu guest
Hi Su, Stefan,
On 08/13/2018 03:46 PM, Stefan Hajnoczi wrote:
> From: Su Hang
>
> 'test.hex' file is a memory test pattern stored in Hexadecimal Object
> Format. It loads at 0x1 in RAM and contains values from 0 through
> 255.
Please add this comment in the source file.
>
> The test
On Mon, Aug 13, 2018 at 04:19:52AM +0200, Max Reitz wrote:
> Signed-off-by: Max Reitz
Reviewed-by: Jeff Cody
> ---
> block/mirror.c | 54 +-
> 1 file changed, 36 insertions(+), 18 deletions(-)
>
> diff --git a/block/mirror.c b/block/mirror.c
>
On Mon, Aug 13, 2018 at 04:19:50AM +0200, Max Reitz wrote:
> Currently, we never test whether we can read from the source while
> mirroring (that means, whether we can read from the mirror BDS). Add
> such a test to 156 because it fits well.
>
> Signed-off-by: Max Reitz
Reviewed-by: Jeff Cody
On Mon, Aug 13, 2018 at 04:19:51AM +0200, Max Reitz wrote:
> mirror_wait_for_any_operation() calls qemu_co_queue_wait(), which is a
> coroutine_fn (technically it is a macro which resolves to a
> coroutine_fn). Therefore, this function needs to be a coroutine_fn as
> well.
>
> This patch makes
2018-08-13 19:30 GMT+08:00 Dr. David Alan Gilbert :
> * Li Qiang (liq...@gmail.com) wrote:
> > 2018-08-13 17:35 GMT+08:00 Dr. David Alan Gilbert :
> >
> > > * Li Qiang (liq...@gmail.com) wrote:
> > > > Hello Dave, Juan and all,
> > > >
> > > > It is useful to get the dirty page rates in guest to
On Thu, 08/09 21:22, Fam Zheng wrote:
> v3: Fix commit message's bug description. [Paolo]
If there's no objection, I'm queuing this for 3.1.
Fam
On Mon, 08/13 16:43, Paolo Bonzini wrote:
> bdrv_io_plug/bdrv_io_unplug take care of keeping a nesting count,
> so change s->plugged to just a bool.
>
> Signed-off-by: Paolo Bonzini
Queued, thanks.
Fam
On Wed, 08/08 13:52, Greg Edwards wrote:
> Unify the get_features functions for vhost-scsi and vhost-user-scsi, including
> their use of host_features, and expose a new 't10_pi' property to enable
> negotiation of the VIRTIO_SCSI_F_T10_PI feature bit with the backend.
>
> Greg Edwards (3):
>
On Mon, 08/13 16:43, Paolo Bonzini wrote:
> nvme_poll_queues is already protected by q->lock, and
> AIO callbacks are invoked outside the AioContext lock.
> So remove the acquire/release pair in nvme_handle_event.
>
> Remove unnecessary variable in in nvme_poll_cb.
>
> Signed-off-by: Paolo
Signed-off-by: Emilio G. Cota
---
hw/i386/pc.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 83a72b..7371cd9960 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -158,7 +158,18 @@ static uint64_t ioportF0_read(void *opaque,
Signed-off-by: Emilio G. Cota
---
configure | 1 +
1 file changed, 1 insertion(+)
diff --git a/configure b/configure
index 2a7796ea80..db216bafb1 100755
--- a/configure
+++ b/configure
@@ -6935,6 +6935,7 @@ case "$target_name" in
TARGET_BASE_ARCH=i386
gdb_xml_files="i386-64bit.xml
With this series I can boot a busybox image and several Ubuntu images
with various -smp's.
The speedup we get is in line with what we get with other ISAs, e.g.
-smp 4 takes 34s instead of 1min with thread=single.
I've run this through the Valgrind race detectors, and the remaining
races reported
Needed for MTTCG.
Signed-off-by: Emilio G. Cota
---
target/i386/translate.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 07d185e7b6..f4c2a41f8f 100644
--- a/target/i386/translate.c
+++
Signed-off-by: Emilio G. Cota
---
cpus.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/cpus.c b/cpus.c
index b5844b7103..b23bf6fef7 100644
--- a/cpus.c
+++ b/cpus.c
@@ -308,6 +308,8 @@ int64_t cpu_get_ticks(void)
{
int64_t ticks;
+g_assert(qemu_mutex_iothread_locked());
+
On Mon, Aug 13, 2018 at 12:38:58PM -0400, Emilio G. Cota wrote:
> This paves the way for implementing the CPU list with an RCU QLIST,
> which cannot be traversed in reverse order.
>
> Note that this is the only caller of CPU_FOREACH_REVERSE.
>
> Signed-off-by: Emilio G. Cota
Acked-by: David
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 29 +
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 61454a77ec..38439a2ee8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 56
fpu/softfloat.c | 188 +---
2 files changed, 179 insertions(+), 65 deletions(-)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 85 ++---
fpu/softfloat.c | 391
2 files changed, 379 insertions(+), 97 deletions(-)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 038e375e71..cc1b58b029
In 88808a022c0, I tried to fix an overflow problem that affected float16
scaling by coverting first to float64 and then rounding after that.
However, Laurent reported that -0x3ff401 converted to float16
resulted in 0xfbfe instead of the expected 0xfbff. This is caused by
the inexact
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 101 ++--
1 file changed, 51 insertions(+), 50 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 38439a2ee8..e4a7d97805 100644
--- a/target/arm/helper.c
+++
On Mon Aug 13 18:27:27 2018, ja...@google.com wrote:
> On Mon, Aug 13, 2018 at 11:21 PM Red Hat Product Security
> wrote:
> > Hi Jann,
> >
> > Thanks for reporting this. I've asked our analysis team to check this.
> > I'll update you on any progress.
> >
> >
> > Regards
> > --
> > Laura Pardo,
Hi Jann,
Thanks for reporting this. I've asked our analysis team to check this.
I'll update you on any progress.
Regards
--
Laura Pardo, Red Hat Product Security
3867 E074 DC5C FFA9 1AA7 EB7F 35A2 69F0 0073 71B6
Ah got it, thanks for the replies / info!
We're using a modified QEMU 2.12, and I don't see the migratable-only loops
and field, so it either got missed in the rebase or was added after 2.12.
Frank
On Mon, Aug 13, 2018 at 9:45 AM Dr. David Alan Gilbert
wrote:
> * Paolo Bonzini
Well my gmake finally went all the way to the end building all of the
guest architectures but I didn't see a qemu executable (unless it isn't
called qemu). I ran gmake again to see what happened and all I got was
this:
# gmake
mkdir -p dtc/libfdt
mkdir -p dtc/tests
Bad string
#
I then ran
Am Fri, 10 Aug 2018 14:29:28 +0200
schrieb Paolo Bonzini :
> On 10/08/2018 12:32, Olaf Hering wrote:
> > Am Fri, 10 Aug 2018 12:25:09 +0200
> > schrieb Paolo Bonzini :
> > So you mean that function must not return NULL?
> > Or should the caller check for the result?
> Either, but the former
On Mon, Jun 11, 2018 at 21:48:46 -0400, Emilio G. Cota wrote:
> Sending this respin (little more than a rebase) in case there's
> reviewer bandwidth available until the soft-freeze in 3 weeks.
*ping*
Would be great to get this in for 3.1.
BTW I have a paper under submission that covers this
On 08-13-2018 6:08 AM, Peter Tribble wrote:
From the point of view of software such as qemu, divergences should be
slight
(there are going to be changes around packaging, shipped compilers,
but that's
true for different Linux distros in the same family). If it builds and
works on
Solaris,
On 08-13-2018 4:34 AM, Daniel P. Berrangé wrote:
Copying Peter, as he would need access to a Solaris host to do GIT pre-merge
build testing.
Then there's the question of what ordinary developers would use for their own
testing if they needed to work on some portability issue. We've got support
cc'ing in Mike*2
* Denis Plotnikov (dplotni...@virtuozzo.com) wrote:
>
>
> On 26.07.2018 12:23, Peter Xu wrote:
> > On Thu, Jul 26, 2018 at 10:51:33AM +0200, Paolo Bonzini wrote:
> > > On 25/07/2018 22:04, Andrea Arcangeli wrote:
> > > >
> > > > It may look like the uffd-wp model is
On Fri, Aug 10, 2018 at 01:26:08AM -0300, Philippe Mathieu-Daudé wrote:
> On 08/03/2018 11:47 AM, Stefan Hajnoczi wrote:
> Can you add a comment providing the .S asm source and how to
> build/generate this blob? (I think this is required to respect the GPLv2
> license in your header).
I have
From: Su Hang
'test.hex' file is a memory test pattern stored in Hexadecimal Object
Format. It loads at 0x1 in RAM and contains values from 0 through
255.
The test case verifies that the expected memory test pattern was loaded.
Reviewed-by: Stefan Hajnoczi
Suggested-by: Steffen Gortz
Some ARM CPUs have bitbanded IO, a memory region that allows convenient
bit access via 32-bit memory loads/stores. This eliminates the need for
read-modify-update instruction sequences.
This patch makes this optional feature an ARMv7MState qdev property,
allowing boards to choose whether they
Define a "cortex-m0" ARMv6-M CPU model.
Most of the register reset values set by other CPU models are not
relevant for the cut-down ARMv6-M architecture.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 11 +++
1
On 08-13-2018 4:14 AM, Thomas Huth wrote:
> For providing a Solaris build machine, you best get in touch with Peter
> Maydell (see MAINTAINERS file for his mail address).
I notice he already checked in later in my inbox. I'll reply to that there.
>
> Now for your build problems, it seems like
> From: Aleksandar Markovic
> Sent: Monday, August 13, 2018 7:52 PM
> To: qemu-devel@nongnu.org
>
> Subject: [PATCH v8 10/87] target/mips: Fix MT ASE instructions' availability
> control
>
> From: Aleksandar Rikalo
>
> Use bits from configuration registers for availability control
> of MT ASE
From: Stefan Markovic
Add XML support files for GDB for nanoMIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
MAINTAINERS| 3 ++-
gdb-xml/nanomips-cp0.xml | 13 +
gdb-xml/nanomips-cpu.xml | 44
Image file loaders may add a series of roms. If an error occurs partway
through loading there is no easy way to drop previously added roms.
This patch adds a transaction mechanism that works like this:
rom_transaction_begin();
...call rom_add_*()...
rom_transaction_end(ok);
If ok is
From: James Hogan
nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit
of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being
read as e.g. 0xbfc1, and prevents writing to the PC clearing
MIPS_HFLAG_M16.
Signed-off-by: James Hogan
Signed-off-by: Yongbok
Hi!
I have noticed that when a QEMU build from git master is started with
"-seccomp on", the seccomp policy is only applied to the main thread,
the vcpu worker thread and the VNC thread (I'm using VNC in my
config); the seccomp policy is not applied to e.g. the RCU thread
because it is created
On 08/13/2018 11:56 AM, Max Reitz wrote:
Ah, hm, so much for that. Hm... I don't quite know what to think of
this. It does indeed improve legibility. But the question is whether
--help should be as condensed as possible, and if the user finds it hard
to read, whether they should not just
From: Aleksandar Rikalo
Add target_syscall.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_syscall.h | 30 ++
1 file changed, 30 insertions(+)
create mode
The next patch will need to free a rom. There is already code to do
this in rom_add_file().
Note that rom_add_file() uses:
rom = g_malloc0(sizeof(*rom));
...
if (rom->fw_dir) {
g_free(rom->fw_dir);
g_free(rom->fw_file);
}
The conditional is unnecessary since g_free(NULL) is
> From: Aleksandar Markovic
> Sent: Monday, August 13, 2018 7:52 PM
>
> Subject: [PATCH v8 09/87] target/mips: Add support for availability control
> via bit MT
>
> From: Aleksandar Rikalo
>
> Add a field in hflags for MT bit, and functions check_mt() and
> check_cp0_mt().
>
>
From: Su Hang
This patch adds Intel Hexadecimal Object File format support to the
generic loader device. The file format specification is available here:
http://www.piclist.com/techref/fileext/hex/intel.htm
This file format is often used with microcontrollers such as the
micro:bit, Arduino,
From: Aleksandar Rikalo
Add signal trampoline support for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/signal.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git
v5:
* Implemented Phil's hex loader suggestions
* Replaced Su Hang's test hex file with a simple memory test pattern,
eliminating the need to distribute source [Phil]
v4:
* Drop ARMv7MState to ARMMProfileState rename because it causes a lot of code
churn and is incomplete. Other parts of
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 556
1 file changed, 556
From: Dimitrije Nikolic
Amend regular MIPS' cpu_loop.c to include nanoMIPS support.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 8 +++-
linux-user/nanomips/cpu_loop.c | 1 +
2 files changed, 8
From: Aleksandar Markovic
Update constants and structures related to linux user syscall support
in nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall_defs.h | 57 ++-
From: Paul Burton
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
From: Aleksandar Rikalo
Add syscall numbers for nanoMIPS. nanoMIPS redefines its ABI
compared to preceding MIPS architectures, and its set of
supported system calls is significantly different.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
From: Aleksandar Rikalo
Add fcntl-related constants and structures for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_fcntl.h | 38 ++
1 file changed, 38
From: Dimitrije Nikolic
This header includes common elf header, and adds cpu_get_model()
function.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_elf.h | 14 ++
1 file changed, 14 insertions(+)
From: Dimitrije Nikolic
Add signal.c as a redirection to regular mips' signal.c, but at the
same time amend regular mips' signal.c with bits and pieces specific
for nanoMIPS. This was done this way to avoid duplication of large
pieces of code.
Signed-off-by: Aleksandar Rikalo
Signed-off-by:
From: Yongbok Kim
Fix ERET/ERETNC so that ADEL exception can be raised.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/op_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
From: Aleksandar Rikalo
Implement support for nanoMIPS LLWP/SCWP instruction pair.
Signed-off-by: Dimitrije Nikolic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 25
target/mips/cpu.h | 2 ++
From: Stefan Markovic
Add new linux user mode configuration for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
configure | 13 -
default-configs/nanomips-linux-user.mak | 1 +
2
From: Aleksandar Rikalo
Implement support for translation of system call statx(). The
implementation includes invoking other (more mature) syscalls
(from the same 'stat' family) on the host side. This way,
problems of availability of statx() on the host side are
avoided.
Signed-off-by:
From: Aleksandar Rikalo
Add termbits.h header for nanoMIPS. Reuse MIPS' termbits.h as
the functionalities are almost identical.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/termbits.h | 4
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 5.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 142
1 file changed, 142
From: Aleksandar Rikalo
Add support for nanomips[eb] variant in scripts/qemu-binfmt-conf.sh.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
scripts/qemu-binfmt-conf.sh | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git
From: Aleksandar Rikalo
nanoMIPs core files require value EF_NANOMIPS_ABI_P32 to be passed
to the e_flags part of the core's elf header.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
From: Dimitrije Nikolic
Add target_structs.h header for nanoMIPS, that in fact only redirects
to the corresponding MIPS header.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_structs.h | 1 +
1 file changed,
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 6.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 62 +
1 file changed, 62
From: Aleksandar Markovic
Add nanoMIPS-related items in qemu-doc.texi
Reviewed-by: Thomas Huth
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
qemu-doc.texi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 8ea6bfa..ab2471d
From: Aleksandar Rikalo
Amend sigaction syscall support for nanoMIPS. This must be done
since nanoMIPS' signal handling is different than MIPS' signal
handling.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall.c | 2 +-
From: Aleksandar Rikalo
nanoMIPS signal handling is much closer to the signal handling in
other mainstream platforms than to the signal handling in preceding
MIPS platforms.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Stefan Markovic
Add definition of the first nanoMIPS processor in QEMU.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate_init.inc.c | 39 +++
1 file changed, 39 insertions(+)
From: Matthew Fortune
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Aleksandar Rikalo
Add nanoMIPS-related values in ELF header fields as specified in
nanoMIPS' "ELF ABI Supplement".
Reviewed-by: Aleksandar Markovic
Acked-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 18 ++
From: Aleksandar Rikalo
Modify load_elf32()/load_elf64() to treat EM_NANOMIPS as equal to
EM_MIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/hw/elf_ops.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/hw/elf_ops.h
From: Matthew Fortune
Add basic nanoMIPS boot code for Malta.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
hw/mips/mips_malta.c | 63 +---
1 file changed, 60 insertions(+), 3 deletions(-)
From: Matthew Fortune
Added a helper for ROTX based on the pseudocode from the
architecture spec. This instraction was not present in previous
MIPS instruction sets.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
From: Aleksandar Markovic
nanoMIPS is always NaN2008 compliant, and rules for checking
FCR31's NAN2008 bit are obsoleted.
Reviewed-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 3 +++
1 file changed, 3 insertions(+)
From: James Hogan
ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there
is no ISA bit, so fix set_pc() to skip the hflags update.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar
From: Dimitrije Nikolic
Add target_cpu.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_cpu.h | 21 +
1 file changed, 21 insertions(+)
create mode 100644
From: Yongbok Kim
Add emulation of various nanoMIPS load and store instructions.
Reviewed-by: Richard Henderson
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 277
From: Aleksandar Rikalo
Add sockbits.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/sockbits.h | 1 +
1 file changed, 1 insertion(+)
create mode 100644 linux-user/nanomips/sockbits.h
diff
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 4.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 363
1 file changed, 363 insertions(+)
diff --git
From: Yongbok Kim
Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called
instruction pools. Each pool contains a set of opcodes, that in turn
can be instruction opcodes or instruction pool opcodes.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by:
From: Aleksandar Markovic
Starting from nanoMIPS introduction, machine variant can be
EM_MIPS or EM_NANOMIPS.
Reviewed-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Stefan Markovic
Fix passing argument for nanoMIPS bare metal related to the
semihosting regime.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
hw/mips/mips_malta.c
From: Stefan Markovic
Update BadInstr, BadInstrP,and BadInstrX registers for nanoMIPS.
The same support for pre-nanoMIPS remains unimplemented.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 2.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
From: Aleksandar Rikalo
Value 249 is registered as valid for usage for nanoMIPS executables.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 28a5a63..312f68a 100644
From: Yongbok Kim
Add emulation of various flavors of nanoMIPS 32-bit branch
instructions.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 262
From: James Hogan
We shouldn't set the ISA bit in CP0_EPC for nanoMIPS.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Yongbok Kim
Add emulation of basic floating point arithmetic for nanoMIPS.
Reviewed-by: Richard Henderson
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 300
From: Yongbok Kim
Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 33 -
1 file changed, 32
From: Yongbok Kim
Add emulation of nanoMIPS instructions situated in pool p_lsx, and
emulation of LSA instruction as well.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 132
From: James Hogan
We shouldn't clear M16 mode when entering an interrupt on nanoMIPS,
otherwise we'll start interpreting the code as normal MIPS code.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Aleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and
linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers.
This adds 9 new syscall numbers, the last being NR_io_pgetevents.
Reviewed-by: Laurent Vivier
Reviewed-by: Richard Henderson
Signed-off-by:
From: Yongbok Kim
Add emulation of nanoMIPS 16-bit branch instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 36
1 file changed, 36
From: Yongbok Kim
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC,
ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
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