On 2018/12/12 下午2:41, Yongji Xie wrote:
On Wed, 12 Dec 2018 at 12:07, Jason Wang wrote:
On 2018/12/12 上午11:21, Yongji Xie wrote:
On Wed, 12 Dec 2018 at 11:00, Jason Wang wrote:
On 2018/12/12 上午10:48, Yongji Xie wrote:
On Mon, 10 Dec 2018 at 17:32, Jason Wang wrote:
On 2018/12/6
On 12/12/18 1:19 AM, David Gibson wrote:
> On Tue, Dec 11, 2018 at 10:06:46AM +0100, Cédric Le Goater wrote:
>> On 12/11/18 1:38 AM, David Gibson wrote:
>>> On Mon, Dec 10, 2018 at 08:53:17AM +0100, Cédric Le Goater wrote:
On 12/10/18 7:39 AM, David Gibson wrote:
> On Sun, Dec 09, 2018 at
[ ... ]
>>> So, instead I think we want a machine option which can be set to
>>> xics/xive/dual, with xics being the default for earlier machine types
>>> and dual the default for 4.0 onwards.
>>
>> I will revive an old patch doing just that.
>>
>> The question now is how to link the
On Tue, Dec 11, 2018 at 02:09:11PM +0300, Ilya Maximets wrote:
> On 11.12.2018 13:53, Daniel P. Berrangé wrote:
> >>
> >> Let's restrict memfd backend to systems with sealing support.
> >
> > I don't think we need todo that - sealing is optional in the QEMU code,
> > we simply have it set to the
Daniel P. Berrangé writes:
> On Mon, Dec 10, 2018 at 02:28:26PM +0100, Markus Armbruster wrote:
[...]
>> checkpatch.pl could flag patches adding .c files that don't include
>> "qemu/osdep.h" first. The "first" part might be a bit annoying to code.
>
> You can get this logic from GNULIBs
Marc-André Lureau writes:
> Hi
>
> On Mon, Dec 10, 2018 at 5:28 PM Markus Armbruster wrote:
>>
>> Marc-André Lureau writes:
>>
>> > Hi
>> >
>> > On Mon, Dec 10, 2018 at 1:52 PM Markus Armbruster
>> > wrote:
>> >>
>> >> Marc-André Lureau writes:
>> >>
>> >> > Now that the schema can be
On Wed, 12 Dec 2018 at 12:07, Jason Wang wrote:
>
>
> On 2018/12/12 上午11:21, Yongji Xie wrote:
> > On Wed, 12 Dec 2018 at 11:00, Jason Wang wrote:
> >>
> >> On 2018/12/12 上午10:48, Yongji Xie wrote:
> >>> On Mon, 10 Dec 2018 at 17:32, Jason Wang wrote:
> On 2018/12/6 下午9:59, Michael S.
On 2018-12-05 at 09:59:23 +, Stefan Hajnoczi wrote:
> On Mon, Nov 05, 2018 at 04:07:50PM +0800, Zhang Yi wrote:
> > Linux 4.15 introduces a new mmap flag MAP_SYNC, which can be used to
> > guarantee the write persistence to mmap'ed files supporting DAX (e.g.,
> > files on ext4/xfs file system
On 2018/12/12 上午11:21, Yongji Xie wrote:
On Wed, 12 Dec 2018 at 11:00, Jason Wang wrote:
On 2018/12/12 上午10:48, Yongji Xie wrote:
On Mon, 10 Dec 2018 at 17:32, Jason Wang wrote:
On 2018/12/6 下午9:59, Michael S. Tsirkin wrote:
On Thu, Dec 06, 2018 at 09:57:22PM +0800, Jason Wang wrote:
On Wed, 12 Dec 2018 at 11:00, Jason Wang wrote:
>
>
> On 2018/12/12 上午10:48, Yongji Xie wrote:
> > On Mon, 10 Dec 2018 at 17:32, Jason Wang wrote:
> >>
> >> On 2018/12/6 下午9:59, Michael S. Tsirkin wrote:
> >>> On Thu, Dec 06, 2018 at 09:57:22PM +0800, Jason Wang wrote:
> On 2018/12/6
On 2018/12/12 上午10:48, Yongji Xie wrote:
On Mon, 10 Dec 2018 at 17:32, Jason Wang wrote:
On 2018/12/6 下午9:59, Michael S. Tsirkin wrote:
On Thu, Dec 06, 2018 at 09:57:22PM +0800, Jason Wang wrote:
On 2018/12/6 下午2:35,elohi...@gmail.com wrote:
From: Xie Yongji
This patchset is aimed at
On 12/7/18 6:48 PM, Alistair Francis wrote:
> +static void tcg_out_addsub2(TCGContext *s,
> +TCGReg rl, TCGReg rh,
> +TCGReg al, TCGReg ah,
> +TCGReg bl, TCGReg bh,
> +bool cbl, bool
On Mon, 10 Dec 2018 at 17:32, Jason Wang wrote:
>
>
> On 2018/12/6 下午9:59, Michael S. Tsirkin wrote:
> > On Thu, Dec 06, 2018 at 09:57:22PM +0800, Jason Wang wrote:
> >> On 2018/12/6 下午2:35,elohi...@gmail.com wrote:
> >>> From: Xie Yongji
> >>>
> >>> This patchset is aimed at supporting qemu to
On 12/7/18 6:47 PM, Alistair Francis wrote:
> +if ((ct & TCG_CT_CONST_N12) && val == sextreg(-val, 0, 12)) {
-val == sextreg(-val, 0, 12)
What's here will of course always fail.
r~
>> v11 --> v12
>> realize pvpanic as a pci device and use the mmio of pci device.
>
>Do you have a pointer to the kernel patches?
>
>Thanks,
>>drew
>
I'm still sorting out the code for the kernel part, and I haven't submitted a
patch yet.
At 2018-12-11 23:22:32, "Yuval Shaia" wrote:
>On Tue, Dec 11, 2018 at 06:56:39PM +0530, P J P wrote:
>> From: Prasad J Pandit
>>
>> Define skeleton 'uar_read' routine. Avoid NULL dereference.
>>
>> Reported-by: Li Qiang
>> Signed-off-by: Prasad J Pandit
>> ---
>>
On Tue, Dec 11, 2018 at 11:19:01AM +0100, Cédric Le Goater wrote:
> On 12/11/18 3:03 AM, David Gibson wrote:
> > On Sun, Dec 09, 2018 at 08:46:07PM +0100, Cédric Le Goater wrote:
> >> The interrupt mode is chosen by the CAS negotiation process and
> >> activated after a reset to take into account
On Tue, Dec 11, 2018 at 11:28:46AM -0500, Wainer dos Santos Moschetta wrote:
> The x86_cpu_class_check_missing_features() returns a list
> of unavailable features compared to the host CPU. Currently it may
> return empty strings for unnamed features as well as duplicated
> names.
>
> For example,
Nothing, I'm packing up the 1st pull request.
On Tue, Dec 11, 2018 at 11:18:51PM -0200, Eduardo Habkost wrote:
> Friendly ping. 3.1.0 is tagged now, so there's anything else
> blocking this series?
>
>
> On Wed, Dec 05, 2018 at 05:57:02PM -0200, Eduardo Habkost wrote:
> > Existing modern-only
Friendly ping. 3.1.0 is tagged now, so there's anything else
blocking this series?
On Wed, Dec 05, 2018 at 05:57:02PM -0200, Eduardo Habkost wrote:
> Existing modern-only device types are not being touched by v3, as
> they don't need separate variants. However, I plan to implement
> separate
On Tue, Dec 11, 2018 at 10:06:46AM +0100, Cédric Le Goater wrote:
> On 12/11/18 1:38 AM, David Gibson wrote:
> > On Mon, Dec 10, 2018 at 08:53:17AM +0100, Cédric Le Goater wrote:
> >> On 12/10/18 7:39 AM, David Gibson wrote:
> >>> On Sun, Dec 09, 2018 at 08:46:00PM +0100, Cédric Le Goater wrote:
>
On Tue, Dec 11, 2018 at 02:36:09PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 10/12/2018 17:20, David Gibson wrote:
> > On Mon, Nov 12, 2018 at 03:12:26PM +1100, Alexey Kardashevskiy wrote:
> >>
> >>
> >> On 12/11/2018 05:10, Greg Kurz wrote:
> >>> Hi Alexey,
> >>>
> >>> Just a few remarks. See
On Tue, Dec 11, 2018 at 11:42:03AM +0100, Cédric Le Goater wrote:
> On 12/11/18 3:06 AM, David Gibson wrote:
> > On Mon, Dec 10, 2018 at 11:17:33PM +0100, Cédric Le Goater wrote:
> >> On 12/9/18 8:46 PM, Cédric Le Goater wrote:
> >>> This pseries machine makes use of a new sPAPR IRQ backend
On Tue, Dec 11, 2018 at 10:55:59AM +0100, Greg Kurz wrote:
> On Tue, 11 Dec 2018 14:53:32 +1100
> Alexey Kardashevskiy wrote:
>
> > On 10/12/2018 20:30, Greg Kurz wrote:
> > > On Mon, 10 Dec 2018 17:20:43 +1100
> > > David Gibson wrote:
> > >
> > >> On Mon, Nov 12, 2018 at 03:12:26PM +1100,
On Tue, Dec 11, 2018 at 11:14:41AM +0100, Cédric Le Goater wrote:
> On 12/11/18 2:47 AM, David Gibson wrote:
> > On Sun, Dec 09, 2018 at 08:46:06PM +0100, Cédric Le Goater wrote:
> >> Depending on the interrupt mode chosen, enable or disable the XIVE
> >> MMIOs.
> >>
> >> Signed-off-by: Cédric Le
I introduced indentation using tabs instead of spaces in another
commit. Peter reported the problem, and I failed to fix that
before sending my pull request.
Reported-by: Peter Maydell
Fixes: 951597607696 ("virt: Eliminate separate instance_init functions")
Signed-off-by: Eduardo Habkost
---
On Mon, Dec 10, 2018 at 9:04 AM Richard Henderson
wrote:
>
> On 12/7/18 6:46 PM, Alistair Francis wrote:
> > When cross compilling for riscv32 hosts using GCC 8.2 this error is seen:
> > error: '__NR__llseek' undeclared (first use in this function); did you
> > mean '_llseek'?
> >
> > To
Patchew URL: https://patchew.org/QEMU/20181211180129.7661-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20181211180129.7661-1-ehabk...@redhat.com
Subject: [Qemu-devel] [PULL 00/24] Machine queue post-3.1.0
On Tue, Dec 11, 2018 at 2:45 PM Richard Henderson
wrote:
>
> On 12/10/18 11:56 AM, Richard Henderson wrote:
> > On 12/7/18 6:49 PM, Alistair Francis wrote:
> >> +case INDEX_op_neg_i64:
> >> +tcg_out_opc_imm(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
> >
> > tcg_out_opc_reg.
> >
> >> +case
On 12/12/2018 03:35, Greg Kurz wrote:
> On Tue, 11 Dec 2018 16:49:25 +1100
> Alexey Kardashevskiy wrote:
>
>> SLOF receives a device tree and updates it with various properties
>> before switching to the guest kernel and QEMU is not aware of any changes
>> made by SLOF. Since there is no real
On 12/6/18 7:08 PM, no-re...@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20181206192544.3987-1-js...@redhat.com/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Subject: [Qemu-devel] [PATCH
On 12/7/18 11:25 AM, Eric Blake wrote:
> On 12/6/18 1:25 PM, John Snow wrote:
>> Especially outside of transactions, it is helpful to provide
>> all-or-nothing semantics for bitmap merges. This facilitates
>> the coalescing of multiple bitmaps into a single target for
>> the "checkpoint"
On Tue, 11 Dec 2018 14:37:07 PST (-0800), Alistair Francis wrote:
This series is now ready to be merged, all of the patches are reviewed
and tested.
Palmer can you take this with all the other RISC-V patches sent during
the freeze?
Yep, I'll be collecting everything this week.
Thanks!
V8:
Currently, the interrupt presenter of the vCPU is set at realize
time. Setting it at reset will become necessary when the new machine
supporting both interrupt modes is introduced. In this machine, the
interrupt mode is chosen at CAS time and activated after a reset.
Signed-off-by: Cédric Le
On 12/7/18 11:28 AM, Eric Blake wrote:
> On 12/6/18 1:25 PM, John Snow wrote:
>> The 'x' prefix was added because we were uncertain of the direction we'd
>> take for the libvirt API. With the general approach solidified, I feel
>> comfortable committing to this API for 4.0.
>>
>> Signed-off-by:
The interrupt modes supported by the hypervisor are advertised to the
guest with new bits definitions of the option vector 5 of property
"ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are
defined as follow :
0b00 PAPR 2.7 and earlier (Legacy systems)
0b01 XIVE
For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread. This will let the XIVE presenter
engine find a match among the NVTs dispatched on the HW threads.
This handler will become even more
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 97a5e3c9929f..705d3f4057b0 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3938,7 +3938,7 @@ static void
Hello,
Here is the version 8 of the QEMU models adding support for the XIVE
interrupt controller to the sPAPR machine, under TCG only. KVM support
will be proposed in an other patchset, along with the KVM XIVE device
patchset, so will PowerNV.
The most important changes for sPAPR are the
This option is used to select the interrupt controller mode (XICS or
XIVE) with which the machine will operate. XICS being the default
mode for now.
When running a machine with the XIVE interrupt mode backend, the guest
OS is required to have support for the XIVE exploitation mode. In the
case of
The different XIVE virtualization structures (sources and event queues)
are configured with a set of Hypervisor calls :
- H_INT_GET_SOURCE_INFO
used to obtain the address of the MMIO page of the Event State
Buffer (ESB) entry associated with the source.
- H_INT_SET_SOURCE_CONFIG
On 12/10/18 11:56 AM, Richard Henderson wrote:
> On 12/7/18 6:49 PM, Alistair Francis wrote:
>> +case INDEX_op_neg_i64:
>> +tcg_out_opc_imm(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
>
> tcg_out_opc_reg.
>
>> +case INDEX_op_mulsh_i32:
>> +case INDEX_op_mulsh_i64:
>> +
Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.
Signed-off-by: Alistair Francis
Signed-off-by: Logan Gunthorpe
Reviewed-by: Logan Gunthorpe
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
---
default-configs/riscv32-softmmu.mak | 5 +-
Depending on the interrupt mode of the machine, enable or disable the
XIVE MMIOs.
Signed-off-by: Cédric Le Goater
---
Changes since v7:
- renamed spapr_xive_enable_mmio() to spapr_xive_mmio_set_enabled()
include/hw/ppc/spapr_xive.h | 1 +
hw/intc/spapr_xive.c| 9 +
The 'dual' sPAPR IRQ backend supports both interrupt mode, XIVE
exploitation mode and the legacy compatibility mode (XICS). both modes
are not supported at the same time.
The machine starts with the legacy mode and a new interrupt mode can
then be negotiated by the CAS process. In this case, the
Enable compile support for VGA devices. This allows the user to conenct
a display by adding '-device bochs-display -display sdl' to their
command line argument.
Signed-off-by: Alistair Francis
Reviewed-by: Logan Gunthorpe
Tested-by: Andrea Bolognani
---
default-configs/riscv32-softmmu.mak | 3
Each interrupt mode has its own specific interrupt presenter object,
that we store under the CPU object, one for XICS and one for XIVE.
Extend the sPAPR IRQ backend with a new handler to support them both.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
Introduce a new sPAPR IRQ handler to handle resend after migration
when the machine is using a KVM XICS interrupt controller model.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
include/hw/ppc/spapr_irq.h | 2 ++
hw/ppc/spapr.c | 13 +
The XIVE IRQ backend uses the same layout as the new XICS backend but
covers the full range of the IRQ number space. The IRQ numbers for the
CPU IPIs are allocated at the bottom of this space, below 4K, to
preserve compatibility with XICS which does not use that range.
This should be enough given
The XIVE interface for the guest is described in the device tree under
the "interrupt-controller" node. A couple of new properties are
specific to XIVE :
- "reg"
contains the base address and size of the thread interrupt
managnement areas (TIMA), for the User level and for the Guest OS
Signed-off-by: Alistair Francis
Reviewed-by: Logan Gunthorpe
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
---
hw/riscv/virt.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2b38f89070..6b6fa39aaa 100644
---
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h
This series is now ready to be merged, all of the patches are reviewed
and tested.
Palmer can you take this with all the other RISC-V patches sent during
the freeze?
V8:
- Drop SiFive U support
- Drop legacy -nic support
- Small other review changes
V7:
- Fix the GPEX memory mapping thanks
On Tue, 11 Dec 2018 at 18:01, Eduardo Habkost wrote:
>
> The following changes since commit 32a1a94dd324d33578dca1dc96d7896a0244d768:
>
> Update version for v3.1.0 release (2018-12-11 17:18:37 +)
>
> are available in the Git repository at:
>
> git://github.com/ehabkost/qemu.git
On 12/11/18 1:35 PM, Mark Cave-Ayland wrote:
> Looking at your profiles above, the primary hotspot appears to be
> helper_lookup_tb_ptr(). However as someone quite new to the TCG parts of
> QEMU, I
> couldn't tell you whether or not this is to be expected.
>
> Perhaps a question for Richard:
On 12/11/18 1:21 PM, Mark Cave-Ayland wrote:
>> Note however, that there are other steps that you must add here before using
>> vector operations in the next patch:
>>
>> (1a) The fpr and vsr arrays must be merged, since fpr[n] == vsrh[n].
>> If this isn't done, then you simply cannot apply
On 12/11/18 11:47 AM, Collin Walling wrote:
> On 12/7/18 7:08 AM, Cornelia Huck wrote:
>> On Thu, 6 Dec 2018 17:24:17 -0500
>> Collin Walling wrote:
>>
>>> Diagnose 318 is a new z14.2 CPU feature. Since we are able to emulate
>>> it entirely via KVM, we can add guest support for earlier models.
Make sure that the new locality passed to tpm_tis_prep_abort()
is valid.
Add a comment to aborting_locty that it may be any locality, including
TPM_TIS_NO_LOCALITY.
Signed-off-by: Stefan Berger
Reviewed-by: Marc-André Lureau
---
hw/tpm/tpm_tis.c | 4 +++-
1 file changed, 3 insertions(+), 1
From: Liu Jingqi
MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
Direct store is implemented by using write combining (WC) for writing
data directly into memory without caching the data.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B
The release document
This series of patches removes an unnecessary parameter from tpm_tis_abort()
and adds a locality range check (using assert()) to tpm_tis_prep_abort() and
tpm_tis_request_completed().
Stefan
The following changes since commit 83ea23cd207a03c5736be0231acbf7f8b05dbf52:
i386: hvf: Fix overrun
From: Peter Maydell
clang complains about taking the address of a packed
member of a struct:
target/i386/kvm.c:1245:27: warning: taking address of packed member 'cpuid' of
class or structure '' may result in an unaligned pointer value
[-Waddress-of-packed-member]
c =
Remove the unused locty parameter from tpm_tis_abort() function.
Signed-off-by: Stefan Berger
Reviewed-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_tis.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c
index d9322692ee..176d424ed9
Make sure that the locality passed from the backend to
tpm_tis_request_completed() is valid.
Signed-off-by: Stefan Berger
Reviewed-by: Marc-André Lureau
---
hw/tpm/tpm_tis.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c
index 04e4ad9212..2563d7501f
From: Liu Jingqi
MOVDIRI moves doubleword or quadword from register to memory through
direct store which is implemented by using write combining (WC) for
writing data directly into memory without caching the data.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI
The release document
The STIBP flag may be supported by the host KVM module, so QEMU
can allow it to be configured manually, and it can be exposed to
guests when using "-cpu host".
No additional migration code is required because the whole
contents of spec_ctrl is already migrated in the "cpu/spec_ctrl"
section.
The following changes since commit 32a1a94dd324d33578dca1dc96d7896a0244d768:
Update version for v3.1.0 release (2018-12-11 17:18:37 +)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to
On 28/11/2018 16:34, Emilio G. Cota wrote:
> Signed-off-by: Emilio G. Cota
> ---
> docs/devel/build-system.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/devel/build-system.txt b/docs/devel/build-system.txt
> index 52501f2ad9..f9fd27fab0 100644
> ---
Hello Yuval,
+-- On Tue, 11 Dec 2018, Yuval Shaia wrote --+
| > Ditto, here send rind and recv rings stays mapped.
| > Look at how QP's ring is destroyed in destroy_qp.
| >
| > For both case suggesting to define a new static function that destroy rings
| > and call it from both error flow of
This feature is in QEMU v3.1, which was released today.
** Changed in: qemu
Status: Fix Committed => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1735049
Title:
Need MTTCG
On 12/11/18 1:47 PM, Wainer dos Santos Moschetta wrote:
Yes, it helped a lot, thanks. And I apologize for my mistake, I'm gonna
send a v3 fixing it.
You may want to wait a day or so for any other comments on v2, to
minimize the resend churn. A maintainer can fix up tags, particularly
when
On 12/11/2018 03:15 PM, Eric Blake wrote:
On 12/11/18 10:28 AM, Wainer dos Santos Moschetta wrote:
The x86_cpu_class_check_missing_features() returns a list
of unavailable features compared to the host CPU. Currently it may
return empty strings for unnamed features as well as duplicated
On 12/11/18 10:23 AM, Igor Mammedov wrote:
On Mon, 10 Dec 2018 14:14:14 -0500
Tony Krowiak wrote:
If the maximum number of devices allowed on a bus is 1 and a device
which is plugged into the bus is subsequently unplugged, attempting to replug
the device fails with error "Bus 'xxx' does not
On 11/12/2018 01:20, David Gibson wrote:
> On Mon, Dec 10, 2018 at 09:54:51PM +0100, BALATON Zoltan wrote:
>> On Mon, 10 Dec 2018, David Gibson wrote:
>>> On Mon, Dec 10, 2018 at 01:33:53AM +0100, BALATON Zoltan wrote:
On Fri, 7 Dec 2018, Mark Cave-Ayland wrote:
> This patchset is an
On Tue, 11 Dec 2018 at 19:13, Mark Cave-Ayland
wrote:
> On 10/12/2018 16:56, Peter Maydell wrote:
> > Anyway, I send it out as a skeleton for comments, because
> > it would be nice to get rid of the old unassigned_access
> > hook, which is fundamentally broken (it's still used by m68k,
> >
Some downstream distributions of QEMU set host-phys-bits=on by
default. This worked very well for most use cases, because
phys-bits really didn't have huge consequences. The only
difference was on the CPUID data seen by guests, and on the
handling of reserved bits.
This changed in KVM commit
On 10/12/2018 19:16, Richard Henderson wrote:
> On 12/7/18 2:56 AM, Mark Cave-Ayland wrote:
>> +static inline void get_vsr(TCGv_i64 dst, int n)
>> +{
>> +tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n]));
>> +}
>> +
>> +static inline void set_vsr(int n, TCGv_i64 src)
>> +{
>> +
On 10/12/2018 19:05, Richard Henderson wrote:
> On 12/7/18 2:56 AM, Mark Cave-Ayland wrote:
>> Instead of accessing the FPR, VMX and VSX registers through static arrays of
>> TCGv_i64 globals, remove them and change the helpers to load/store data
>> directly
>> within cpu_env.
>>
>>
On 10/12/2018 18:49, Richard Henderson wrote:
> On 12/7/18 2:56 AM, Mark Cave-Ayland wrote:
>> +avr = tcg_temp_new_i64();
>> \
>> EA = tcg_temp_new();
>> \
>>
On 10/12/2018 18:43, Richard Henderson wrote:
> On 12/7/18 2:56 AM, Mark Cave-Ayland wrote:
>> -gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env,
>> \
>> - cpu_fpr[rA(ctx->opcode)],
>> \
>> -
On 10/12/2018 16:56, Peter Maydell wrote:
> This patchset converts the m68k target from the deprecated
> unassigned_access hook to the new transaction_failed hook.
> It's RFC for a couple of reasons:
> * it's untested, since I don't have an m68k test image
> * the second patch just makes "bus
On 10/12/2018 13:04, Aleksandar Markovic wrote:
> On Dec 7, 2018 9:59 AM, "Mark Cave-Ayland"
> wrote:
>>
>> This patchset is an attempt at trying to improve the VMX (Altivec)
> instruction
>> performance by making use of the new TCG vector operations where possible.
>>
>
> Hello, Mark.
>
> I
On 10/12/2018 05:17, David Gibson wrote:
> On Fri, Dec 07, 2018 at 08:56:30AM +, Mark Cave-Ayland wrote:
>> These helpers allow us to move FP register values to/from the specified
>> TCGv_i64
>> argument.
>>
>> To prevent FP helpers accessing the cpu_fpr array directly, add extra TCG
>>
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of
the QEMU 3.1.0 release. This release contains 1900+ commits from 189
authors.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
The full list of changes are available at:
On 10/12/2018 03:46, David Gibson wrote:
> On Fri, Dec 07, 2018 at 04:08:05PM +, Mark Cave-Ayland wrote:
>> This is in preparation for some upcoming QEMU NDRV driver changes that pass
>> display information from the host to the guest.
>>
>> Signed-off-by: Mark Cave-Ayland
>
> This looks
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-Id: <20181125205000.10324-5-phi...@redhat.com>
Signed-off-by: Laurent Vivier
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
Reviewed-by: Mark Cave-Ayland
Message-Id: <20181125205000.10324-9-phi...@redhat.com>
Signed-off-by: Laurent Vivier
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS
On Tue, Dec 11, 2018 at 09:29:44AM +, Daniel P. Berrangé wrote:
> On Tue, Dec 11, 2018 at 08:42:41AM +0100, Hoffmann, Gerd wrote:
> > Hi,
> >
> > > Right. The main issue is that we need to make sure only
> > > in-tree devices are supported.
> >
> > Well, that is under debate right now,
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Gerd Hoffmann
Message-Id: <20181125205000.10324-18-phi...@redhat.com>
Signed-off-by: Laurent Vivier
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
From: Li Qiang
Cc: qemu-triv...@nongnu.org
Signed-off-by: Li Qiang
Reviewed-by: Laurent Vivier
Message-Id: <20181030151637.37207-1-liq...@163.com>
Signed-off-by: Laurent Vivier
---
include/hw/qdev-core.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Fam Zheng
Since I am about to change company, update the email address in
MAINTAINERS to my personal one. Depending on responsibility changes I
may eventually fade out in some of the maintained areas, but that will
be figured out afterward, or maybe I'll use the work email later. For
now,
From: "fabrice.descl...@cea.fr"
As "xchg" reads and writes both operands, the "+m" is required to avoid
undefined behavior on -O2 compilation.
Signed-off-by: Fabrice Desclaux
Reviewed-by: Richard Henderson
Message-Id: <03506cf0-a204-f619-8ee4-4990a5e69...@cea.fr>
Signed-off-by: Laurent Vivier
From: Eric Blake
POSIX states that the value of endptr is unspecified if strtol()
fails with EINVAL due to an invalid base argument. Since none of
the callers to check_strtox_error() initialized endptr, we could
end up propagating uninitialized data back to a caller on error.
However, passing
On 12/11/18 10:53 AM, Peter Maydell wrote:
> On Fri, 7 Dec 2018 at 10:37, Richard Henderson
> wrote:
>>
>> We need to reuse this from helper-a64.c. Provide a stub
>> definition for CONFIG_USER_ONLY. This matches the stub
>> definitions that we removed for arm_regime_tbi{0,1} before.
>>
>>
From: Philippe Mathieu-Daudé
This pattern now also matches:
- include/hw/timer/digic-timer.h
- include/hw/char/digic-uart.h
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-Id: <20181125205000.10324-16-phi...@redhat.com>
Signed-off-by: Laurent Vivier
---
MAINTAINERS
From: Eric Blake
Adding a new qapi module had some rather tedious repetition to
wire it into Makefile, Makefile.objs, and .gitignore (for example,
see commit bf42508f and its followup b61acdec). For make, add some
indirection by taking advantage of GNU Make string processing to
expand a list of
On 12/11/18 10:52 AM, Peter Maydell wrote:
> This has lost the bit of the old functions that converted
> the stage 1+2 MMU index into a stage 1 MMU index. The call
> to regime_el() in aa64_va_parameters() will assert if it is
> passed ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1. (In the code
> paths in
From: Thomas Huth
nios2_iic.c and the default-configs/nios2-softmmu.mak file are
currently "unmaintained" according to the get_maintainers.pl script.
Move them to the Nios2 section where they obviously belong to.
Signed-off-by: Thomas Huth
Reviewed-by: Laurent Vivier
Message-Id:
On 12/11/2018 9:11 AM, Stefano Garzarella wrote:
Hi Liam,
in order to support PVH also with SeaBIOS, I'm going to work on a new
option rom (like linuxboot/multiboot) that can be used in this case.
That is awesome. Yes, please keep us posted when you have something working.
Just FYI, before
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20181125205000.10324-15-phi...@redhat.com>
Signed-off-by: Laurent Vivier
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
On 12/11/18 9:45 AM, Peter Maydell wrote:
> On Fri, 7 Dec 2018 at 10:37, Richard Henderson
> wrote:
>>
>> Signed-off-by: Richard Henderson
>> ---
>> target/arm/cpu64.c | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
>> index
1 - 100 of 387 matches
Mail list logo
