On Jun 5, 2019 11:03 PM, "Richard Henderson"
wrote:
>
> This is a collection of related
Related to what?
> defines for notes, copied
> from glibc's . We're not going to use all of these
> right away, but it seemed foolish
I don't think this an appropriate word for a commit message.
> to
"H. Peter Anvin" writes:
> On 6/5/19 12:55 PM, H. Peter Anvin wrote:
>> Hi,
>>
>> I am writing some code I'm hoping will be able to make it into Qemu, but I
>> can't seem to find what the baseline portability requirements are. I'm
>> specifically wondering about newer POSIX features like
You neglected to cc: the file's maintainer. I'm doing that for you now.
In the future, use scripts/get_maintainer.pl to find maintainers you
might want to cc:.
Lidong Chen writes:
> The check for poll_fds in g_assert() was incorrect. The correct assertion
> should check "n_poll_fds + w->num <=
On Thursday 06 June 2019 07:04 AM, David Gibson wrote:
> On Wed, May 29, 2019 at 11:10:14AM +0530, Aravinda Prasad wrote:
>> This patch adds support in QEMU to handle "ibm,nmi-register"
>> and "ibm,nmi-interlock" RTAS calls.
>>
>> The machine check notification address is saved when the
>> OS
Eric Blake writes:
> On 6/5/19 3:13 PM, Eduardo Habkost wrote:
>
>>> IOW, I don't think RHEL-7 support as a build platform blocks us from
>>> dropping py2. We merely need to tweak our build platforms doc to clarify
>>> our intent wrt add-on yum repos.
>>
>> If we clarify the docs in QEMU 4.1,
On Tuesday 04 June 2019 08:20 PM, Greg Kurz wrote:
> On Tue, 4 Jun 2019 11:38:31 +0530
> Aravinda Prasad wrote:
>
>> On Monday 03 June 2019 04:47 PM, Greg Kurz wrote:
>>> On Mon, 3 Jun 2019 12:12:43 +0200
>>> Greg Kurz wrote:
>>>
On Wed, 29 May 2019 11:10:14 +0530
Aravinda
On 5/24/2019 8:35 PM, Igor Mammedov wrote:
On Wed, 8 May 2019 14:17:19 +0800
Tao Xu wrote:
Add build_mem_ranges callback to AcpiDeviceIfClass and use
it for generating SRAT and HMAT numa memory ranges.
Suggested-by: Igor Mammedov
Co-developed-by: Liu Jingqi
Signed-off-by: Liu Jingqi
On Thursday 06 June 2019 08:32 AM, David Gibson wrote:
> On Tue, Jun 04, 2019 at 12:15:26PM +0530, Aravinda Prasad wrote:
>>
>>
>> On Monday 03 June 2019 08:55 PM, Greg Kurz wrote:
>>> On Wed, 29 May 2019 11:10:49 +0530
>>> Aravinda Prasad wrote:
>>>
Enable the KVM capability
Laurent Vivier writes:
> Add a new RNG backend using QEMU builtin getrandom function.
>
> It can be created and used with something like:
>
> ... -object rng-builtin,id=rng0 -device virtio-rng,rng=rng0 ...
>
> Signed-off-by: Laurent Vivier
> ---
> backends/Makefile.objs | 2 +-
>
Laurent Vivier writes:
> On 05/06/2019 19:56, Markus Armbruster wrote:
>> Laurent Vivier writes:
>>
>>> On 05/06/2019 15:05, Markus Armbruster wrote:
Laurent Vivier writes:
> Add a new RNG backend using QEMU builtin getrandom function.
>
> v7: rebase on master
>
On Thursday 06 June 2019 07:13 AM, David Gibson wrote:
> On Wed, May 29, 2019 at 11:10:32AM +0530, Aravinda Prasad wrote:
>> Memory error such as bit flips that cannot be corrected
>> by hardware are passed on to the kernel for handling.
>> If the memory address in error belongs to guest then
On Thursday 06 June 2019 07:05 AM, David Gibson wrote:
> On Mon, Jun 03, 2019 at 01:17:23PM +0200, Greg Kurz wrote:
>> On Mon, 3 Jun 2019 12:12:43 +0200
>> Greg Kurz wrote:
>>
>>> On Wed, 29 May 2019 11:10:14 +0530
>>> Aravinda Prasad wrote:
>>>
This patch adds support in QEMU to handle
On Thu, Jun 06, 2019 at 02:13:20PM +1000, Alexey Kardashevskiy wrote:
> I changed my handy scripts for posting patches and the subject line
> broke, do I need to repost? It made it to the patchworks though.
No, that's fine I've seen it and will look at it when I have the chance.
>
>
>
> On
I changed my handy scripts for posting patches and the subject line
broke, do I need to repost? It made it to the patchworks though.
On 06/06/2019 14:09, Alexey Kardashevskiy wrote:
> The pseries guests do not normally allocate PCI resouces and rely on
> the system firmware doing so.
The pseries guests do not normally allocate PCI resouces and rely on
the system firmware doing so. Furthermore at least at some point in
the past the pseries guests won't even be allowed to change BARs, probably
it is still the case for phyp. So since the initial commit we have [1]
which prevents
On Tue, May 21, 2019 at 12:50:52AM +0800, Like Xu wrote:
> The die-level as the first PC-specific cpu topology is added to the
> leagcy cpu topology model which only covers sockets/cores/threads.
>
> In the new model with die-level support, the total number of logical
> processors (including
On Tue, May 21, 2019 at 12:50:52AM +0800, Like Xu wrote:
> The die-level as the first PC-specific cpu topology is added to the
> leagcy cpu topology model which only covers sockets/cores/threads.
>
> In the new model with die-level support, the total number of logical
> processors (including
On Wed, 04/17 22:53, Maxim Levitsky wrote:
> Signed-off-by: Maxim Levitsky
> ---
> block/nvme.c | 80 ++
> block/trace-events | 2 ++
> 2 files changed, 82 insertions(+)
>
> diff --git a/block/nvme.c b/block/nvme.c
> index
On Tue, May 21, 2019 at 12:50:54AM +0800, Like Xu wrote:
> For PC target, users could configure the number of dies per one package
> via command line with this patch, such as "-smp dies=2,cores=4".
>
> A new pc-specified pc_smp_parse() is introduced and to keep the interface
> consistent,
On Wed, Jun 05, 2019 at 11:54:56PM -0300, Eduardo Habkost wrote:
> On Wed, Jun 05, 2019 at 11:52:41PM -0300, Eduardo Habkost wrote:
> > On Sun, May 19, 2019 at 04:54:22AM +0800, Like Xu wrote:
> > > The global smp variables in ppc are replaced with smp machine properties.
> > >
> > > A local
On Tue, Jun 04, 2019 at 11:59:13AM +0530, Aravinda Prasad wrote:
>
>
> On Monday 03 June 2019 07:30 PM, Greg Kurz wrote:
> > On Wed, 29 May 2019 11:10:40 +0530
> > Aravinda Prasad wrote:
> >
> >> Upon a machine check exception (MCE) in a guest address space,
> >> KVM causes a guest exit to
On Tue, Jun 04, 2019 at 11:01:19AM +0200, Greg Kurz wrote:
> On Tue, 4 Jun 2019 11:59:13 +0530
> Aravinda Prasad wrote:
>
> > On Monday 03 June 2019 07:30 PM, Greg Kurz wrote:
> > > On Wed, 29 May 2019 11:10:40 +0530
> > > Aravinda Prasad wrote:
> > >
> > >> Upon a machine check exception
On Wed, May 29, 2019 at 11:10:57AM +0530, Aravinda Prasad wrote:
> This patch includes migration support for machine check
> handling. Especially this patch blocks VM migration
> requests until the machine check error handling is
> complete as (i) these errors are specific to the source
> hardware
On Tue, Jun 04, 2019 at 12:15:26PM +0530, Aravinda Prasad wrote:
>
>
> On Monday 03 June 2019 08:55 PM, Greg Kurz wrote:
> > On Wed, 29 May 2019 11:10:49 +0530
> > Aravinda Prasad wrote:
> >
> >> Enable the KVM capability KVM_CAP_PPC_FWNMI so that
> >> the KVM causes guest exit with NMI as
On Wed, May 29, 2019 at 11:10:49AM +0530, Aravinda Prasad wrote:
> Enable the KVM capability KVM_CAP_PPC_FWNMI so that
> the KVM causes guest exit with NMI as exit reason
> when it encounters a machine check exception on the
> address belonging to a guest. Without this capability
> enabled, KVM
On Sun, May 19, 2019 at 04:54:28AM +0800, Like Xu wrote:
> The global smp variables in vl.c are completely replaced with machine
> properties.
>
> Form this commit, the smp_cpus/smp_cores/smp_threads/max_cpus are deprecated
> and only machine properties within MachineState are fully applied and
On 6/5/2019 8:12 PM, Igor Mammedov wrote:
On Wed, 5 Jun 2019 14:04:10 +0800
Tao Xu wrote:
On 6/4/2019 11:04 PM, Igor Mammedov wrote:
On Wed, 8 May 2019 14:17:22 +0800
Tao Xu wrote:
...
+
+/* SMBIOS Handles */
+/* TBD: set smbios handles */
+
On Sun, May 19, 2019 at 04:54:18AM +0800, Like Xu wrote:
> This patch series make existing cores/threads/sockets into machine
> properties and get rid of global smp_* variables they use currently.
>
> The purpose of getting rid of globals is disentangle layer violations and
> let's do it one step
On Sun, May 19, 2019 at 04:54:26AM +0800, Like Xu wrote:
> The global smp variables in arm are replaced with smp machine properties.
> The init_cpus() and *_create_rpu() are refactored to pass MachineState.
>
> A local variable of the same name would be introduced in the declaration
> phase if
On Sun, May 19, 2019 at 04:54:27AM +0800, Like Xu wrote:
> The global smp variables in alpha/hppa/mips/openrisc/sparc*/xtensa codes
> are replaced with smp properties from MachineState.
>
> A local variable of the same name would be introduced in the declaration
> phase if it's used widely in the
On Sun, May 19, 2019 at 04:54:25AM +0800, Like Xu wrote:
> The global smp variables in i386 are replaced with smp machine properties.
> To avoid calling qdev_get_machine() as much as possible, some related funtions
> for acpi data generations are refactored. No semantic changes.
>
> A local
On Sun, May 19, 2019 at 04:54:24AM +0800, Like Xu wrote:
> The global smp variables in s390x are replaced with smp machine properties.
>
> A local variable of the same name would be introduced in the declaration
> phase if it's used widely in the context OR replace it on the spot if it's
> only
On Wed, 04/17 22:53, Maxim Levitsky wrote:
> Signed-off-by: Maxim Levitsky
> ---
> block/nvme.c | 69 +++-
> block/trace-events | 1 +
> include/block/nvme.h | 19 +++-
> 3 files changed, 87 insertions(+), 2 deletions(-)
>
> diff --git
On Wed, Jun 05, 2019 at 11:52:41PM -0300, Eduardo Habkost wrote:
> On Sun, May 19, 2019 at 04:54:22AM +0800, Like Xu wrote:
> > The global smp variables in ppc are replaced with smp machine properties.
> >
> > A local variable of the same name would be introduced in the declaration
> > phase if
On Sun, May 19, 2019 at 04:54:22AM +0800, Like Xu wrote:
> The global smp variables in ppc are replaced with smp machine properties.
>
> A local variable of the same name would be introduced in the declaration
> phase if it's used widely in the context OR replace it on the spot if it's
> only
On Mon, Jun 03, 2019 at 01:17:23PM +0200, Greg Kurz wrote:
> On Mon, 3 Jun 2019 12:12:43 +0200
> Greg Kurz wrote:
>
> > On Wed, 29 May 2019 11:10:14 +0530
> > Aravinda Prasad wrote:
> >
> > > This patch adds support in QEMU to handle "ibm,nmi-register"
> > > and "ibm,nmi-interlock" RTAS calls.
On Wed, May 29, 2019 at 11:10:32AM +0530, Aravinda Prasad wrote:
> Memory error such as bit flips that cannot be corrected
> by hardware are passed on to the kernel for handling.
> If the memory address in error belongs to guest then
> the guest kernel is responsible for taking suitable action.
>
On Wed, May 29, 2019 at 11:10:14AM +0530, Aravinda Prasad wrote:
> This patch adds support in QEMU to handle "ibm,nmi-register"
> and "ibm,nmi-interlock" RTAS calls.
>
> The machine check notification address is saved when the
> OS issues "ibm,nmi-register" RTAS call.
>
> This patch also handles
When we are not in the last_stage, we need to update the cache if page
is not the same.
Currently this procedure is scattered in two places and mixed with
encoding status check.
This patch extract this general step out to make the code a little bit
easy to read.
Signed-off-by: Wei Yang
---
For cache miss condition not in last_stage, we need to insert data into
cache. When this step succeed, current_data should be updated. While no
matter these checks pass or not, -1 is returned.
Based on this, the logic in cache miss handling could be simplified a
little.
Signed-off-by: Wei Yang
Two trivial patches to make save_xbzrle_page() a little bit easy to
understand.
Wei Yang (2):
migration/xbzrle: update cache and current_data in one place
migration/xbzrle: cleanup the handling cache miss condition
migration/ram.c | 36 +---
1 file changed,
On 6/4/2019 10:34 PM, Cornelia Huck wrote:
On Fri, 24 May 2019 16:18:38 +0800
Tao Xu wrote:
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
Availability of the user wait instructions is indicated by the presence
of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
The
Hi,
Looking at QEMU source code, I am puzzled regarding how migration backwards
compatibility is preserved regarding X86CPU.
As I understand it, fields that are based on KVM capabilities and guest runtime
usage are defined in VMState subsections in order to not send them if not
necessary.
On Wed, 05 Jun 2019 13:59:53 PDT (-0700), ma...@decred.org wrote:
Joel is on vacation so here it is again.
Begin forwarded message:
From: Alistair Francis
Subject: Re: [j...@sing.id.au: atomic failures on qemu-system-riscv64]
Date: June 5, 2019 at 7:19:53 PM GMT+1
To: "j...@sing.id.au" ,
Patchew URL:
https://patchew.org/QEMU/20190605205706.569-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v6 0/6] linux-user/aarch64: Support PROT_BTI
Type: series
Message-id:
On Wed, 5 Jun 2019 at 23:07, Alistair Francis wrote:
>
> On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
> wrote:
> >
> > The PMP should be checked when doing a page table walk, and report access
> > fault exception if the to-be-read PTE failed the PMP check.
> >
> > Suggested-by: Jonathan
Patchew URL: https://patchew.org/QEMU/20190605213654.9785-1-ptosc...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190605213654.9785-1-ptosc...@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH v6] ssh: switch
On 6/5/19 3:49 PM, Eduardo Habkost wrote:
> On Wed, Jun 05, 2019 at 03:42:39PM -0500, Eric Blake wrote:
>> On 6/5/19 3:13 PM, Eduardo Habkost wrote:
>>
IOW, I don't think RHEL-7 support as a build platform blocks us from
dropping py2. We merely need to tweak our build platforms doc to
Rewrite the implementation of the ssh block driver to use libssh instead
of libssh2. The libssh library has various advantages over libssh2:
- easier API for authentication (for example for using ssh-agent)
- easier API for known_hosts handling
- supports newer types of keys in known_hosts
Use
On Tue, May 21, 2019 at 01:19:09AM +0200, Philippe Mathieu-Daudé wrote:
> This tests boots a Linux kernel on a Malta machine up to a
> busybox shell on the serial console. Few commands are executed
> before halting the machine (via reboot).
>
> We use the initrd cpio image from the kerneltests
Joel is on vacation so here it is again.
> Begin forwarded message:
>
> From: Alistair Francis
> Subject: Re: [j...@sing.id.au: atomic failures on qemu-system-riscv64]
> Date: June 5, 2019 at 7:19:53 PM GMT+1
> To: "j...@sing.id.au" , "pal...@sifive.com"
>
> Cc: "ma...@decred.org" ,
On Jun 5, 2019 11:03 PM, "Richard Henderson"
wrote:
>
> This is a collection of related defines for notes, copied
> from glibc's . We're not going to use all of these
> right away, but it seemed foolish to cherry-pick only the
> ones we need now.
>
But you are doing exactly that:
On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
wrote:
>
> The PMP should be checked when doing a page table walk, and report access
> fault exception if the to-be-read PTE failed the PMP check.
>
> Suggested-by: Jonathan Behrens
> Signed-off-by: Hesham Almatary
> ---
> target/riscv/cpu.h
On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
wrote:
>
> The current PMP check function checks for env->priv which is not the effective
> memory privilege mode.
>
> For example, mstatus.MPRV could be set while executing in M-Mode, and in that
> case the privilege mode for the PMP check should
The kernel will return -EINVAL for bits set in the prot argument
that are unknown or invalid. Previously we were simply cropping
out the bits that we care about.
Introduce validate_prot_to_pageflags to perform this check in a
single place between the two syscalls. Differentiate between
the
On May 21, 2019 12:07 AM, "Philippe Mathieu-Daudé" wrote:
>
> Avoid to log empty lines in console debug logs.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
Acked-by: Aleksandar Markovic
> tests/acceptance/boot_linux_console.py | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
On Tue, May 28, 2019 at 11:13 AM Markus Armbruster wrote:
>
> We have a bunch of headers without multiple inclusion guards. Some are
> clearly intentional, some look accidental. Too many for me to find out
> by examining each of them, so I'm asking their maintainers.
>
> Why do I ask? I'd like
Transform the prot bit to a qemu internal page bit, and save
it in the page tables.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 2 ++
linux-user/syscall_defs.h | 4
linux-user/mmap.c | 16
target/arm/translate-a64.c | 6 +++---
4 files
This will build with older toolchains, without the upstream support
for -mbranch-protection. Such a toolchain will produce a warning
in such cases,
ld: warning: /tmp/ccyZt0kq.o: unsupported GNU_PROPERTY_TYPE (5) \
type: 0xc000
but the still places the note at the correct location in the
The value of btype for syscalls is CONSTRAINED UNPREDICTABLE,
so we need to make sure that the value is 0 before clone,
fork, or syscall return.
The kernel sets btype for the signal handler as if for a call.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/cpu_loop.c | 7 +++
For aarch64, this includes the GNU_PROPERTY_AARCH64_FEATURE_1_BTI bit,
which indicates that the image should be mapped with guarded pages.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 83 +++-
1 file changed, 75 insertions(+), 8
Take care of reading/indicating the 32-bit elements.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 ++
target/s390x/vec_fpu_helper.c |
This is a collection of related defines for notes, copied
from glibc's . We're not going to use all of these
right away, but it seemed foolish to cherry-pick only the
ones we need now.
Signed-off-by: Richard Henderson
---
include/elf.h | 48
1
We can reuse some of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
On Wed, Jun 05, 2019 at 12:06:59PM -0400, Cleber Rosa wrote:
> On Tue, May 21, 2019 at 12:06:35AM +0200, Philippe Mathieu-Daudé wrote:
> > Similar to the x86_64/pc test, it boots a Linux kernel on an
> > Emcraft board and verify the serial is working.
> >
> > If ARM is a target being built, "make
Dave Martin has recently posted a kernel patch set for
supporting ARMv8.5 Branch Target Identification in userland.
http://lists.infradead.org/pipermail/linux-arm-kernel/2019-May/654654.html
While that support is not yet in the upstream kernel, it looks
to be close to its final form. Note
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed, 30 insertions(+)
diff
On Wed, Jun 05, 2019 at 03:42:39PM -0500, Eric Blake wrote:
> On 6/5/19 3:13 PM, Eduardo Habkost wrote:
>
> >> IOW, I don't think RHEL-7 support as a build platform blocks us from
> >> dropping py2. We merely need to tweak our build platforms doc to clarify
> >> our intent wrt add-on yum repos.
>
On 6/5/19 3:13 PM, Eduardo Habkost wrote:
>> IOW, I don't think RHEL-7 support as a build platform blocks us from
>> dropping py2. We merely need to tweak our build platforms doc to clarify
>> our intent wrt add-on yum repos.
>
> If we clarify the docs in QEMU 4.1, is there anything that
>
The only FP instruction we can implement without an helper.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 52 +
2 files changed, 54 insertions(+)
diff --git
On 6/5/19 12:55 PM, H. Peter Anvin wrote:
> Hi,
>
> I am writing some code I'm hoping will be able to make it into Qemu, but I
> can't seem to find what the baseline portability requirements are. I'm
> specifically wondering about newer POSIX features like openat(), which seems
> to be used in
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed, 30 insertions(+)
diff
1. We'll reuse op_vfa() for similar instructions later, prepare for
that.
2. We'll reuse vop64_3() for other instructions later.
3. Take care of modifying the vector register only if no trap happened.
- on traps, flags are not updated and no elements are modified
- traps don't modify the fpc
We can reuse most of the infrastructure added for VECTOR FP ADD.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 4 +++
target/s390x/translate_vx.inc.c | 23
target/s390x/vec_fpu_helper.c | 48 +
4 files changed,
Similar to VECTOR FP ADD.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +
4 files changed, 24
We can reuse float64_dcmask().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 21 +++
target/s390x/vec_fpu_helper.c | 37
Provide for all three instructions all four combinations of cc bit and
s bit.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 12
target/s390x/insn-data.def | 6 ++
target/s390x/translate_vx.inc.c | 51
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store")
revealed that the vregs are not aligned to 16 bytes. Align them to
16 bytes, to avoid segfault'ing on x86.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/cpu.h | 2 +-
1 file changed, 1
Vector floating-point instructions will require these functions, so
allow to use them from other files.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 4 ++--
target/s390x/internal.h | 4
2 files changed, 6 insertions(+), 2 deletions(-)
Very similar to VECTOR FP DIVIDE.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +
4 files
From: Richard Henderson
This replaces the target-specific implementations for VSEL.
Signed-off-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/translate_vx.inc.c | 38 ++---
1 file changed, 6 insertions(+), 32 deletions(-)
diff --git
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:
z14 PoP, 6-20, "Vector-Exception Code"
When a vector-processing exception causes a pro-
gram interruption, a vector-exception code (VXC) is
stored at location 147, and zeros are
Let's add all HWCAPs that we can support under TCG right now, when the
respective CPU facilities are enabled.
Cc: Riku Voipio
Cc: Laurent Vivier
Cc: Cornelia Huck
Cc: Laurent Vivier
Cc: Richard Henderson
Acked-by: Laurent Vivier
Reviewed-by: Richard Henderson
Signed-off-by: David
Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H.
Add s390_vec_read_element() that can deal with element sizes.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6 +++
target/s390x/insn-data.def | 2 +
We don't care about the other two missing base features:
- S390_FEAT_DFP_PACKED_CONVERSION
- S390_FEAT_GROUP_GEN13_PTFF
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
hw/s390x/s390-virtio-ccw.c | 2 ++
target/s390x/cpu_models.c | 4 ++--
target/s390x/gen-features.c |
We can reuse most of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
Let's add it to the max model, so we can enable it.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/gen-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index c346b76bdf..a818c80332 100644
As far as I can see, there is only a tiny difference.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 21 +
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing
helper function.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 +++
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed, 30 insertions(+)
diff
1. We'll reuse op_vcdg() for similar instructions later, prepare for
that.
2. We'll reuse vop64_2() later for other instructions.
We have to mangle the erm (effective rounding mode) and the m4 into
the simd_data(), and properly unmangle them again.
Make sure to restore the erm before
Unfortunately, there is no easy way to avoid looping over all elements
in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and
all element types. Especially for different values of rt, the compiler
might be able to optimize the code a lot.
Add s390_vec_write_element().
used_stfl_bytes is 0, before initialized via prepare_stfl() on the
first invocation. We have to move the calculation of max_bytes after
prepare_stfl().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/misc_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1
Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
able to make use of it.
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: David Hildenbrand
---
target/s390x/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/s390x/cpu.c
The PoP (z14, 7-382) says:
Doublewords to the right of the doubleword in which the
highest-numbered facility bit is assigned for a model
may or may not be stored.
However, stack protection in certain binaries can't deal with that.
"gzip" example code:
f1b4: a7 08 00 03
Core logic courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 31 +
target/s390x/vec_string_helper.c | 57
CPU_DoubleU is primarily used to reinterpret between integer and floats.
We don't really need this functionality. So let's just keep it simple
and use an uint64_t.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
linux-user/s390x/signal.c | 4 +-
target/s390x/arch_dump.c
Complicated stuff. Provide two different helpers for CC an !CC handling.
We might want to add more helpers later.
zero_search() and match_index() are courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/Makefile.objs | 2 +-
Logic mostly courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6 +
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 34
target/s390x/vec_string_helper.c | 45
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