[Qemu-devel] [PULL 4/4] Deprecate Python 2 support

Python 2 will reach end of life in January 1 2020. Declare it as deprecated. Signed-off-by: Eduardo Habkost Message-Id: <20190503193721.18459-1-ehabk...@redhat.com> Reviewed-by: Thomas Huth Reviewed-by: Markus Armbruster Reviewed-by: Daniel P. Berrangé [ehabkost: print "warning:" in

[Qemu-devel] [PULL 25/46] aspeed: Link SCU to the watchdog

From: Joel Stanley The ast2500 uses the watchdog to reset the SDRAM controller. This operation is usually performed by u-boot's memory training procedure, and it is enabled by setting a bit in the SCU and then causing the watchdog to expire. Therefore, we need the watchdog to be able to access

Re: [Qemu-devel] [PATCH v3 00/27] Support disabling TCG on ARM

Patchew URL: https://patchew.org/QEMU/20190701132516.26392-1-phi...@redhat.com/ Hi, This series failed build test on s390x host. Please find the details below. === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under the git checkout with # HEAD pointing to a commit that

Re: [Qemu-devel] [PULL 0/3] M68k next patches

On Wed, 26 Jun 2019 at 17:42, Laurent Vivier wrote: > > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50 +0100) > > are available in the Git

[Qemu-devel] [PULL 41/46] target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()

From: Philippe Mathieu-Daudé The vfp_set_fpscr() helper contains code specific to the host floating point implementation (here the SoftFloat library). Extract this code to vfp_set_fpscr_to_host(). Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-16-phi...@redhat.com

[Qemu-devel] [PULL 35/46] target/arm: Fix coding style issues

From: Philippe Mathieu-Daudé Since we'll move this code around, fix its style first. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-9-phi...@redhat.com Signed-off-by: Peter Maydell --- target/arm/translate.c | 11 ++-

[Qemu-devel] [PULL 0/4] Python queue, 2019-07-01

The following changes since commit 7d0e02405fc02a181319b1ab8681d2f72246b7c6: Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2019-07-01 17:40:32 +0100) are available in the Git repository at: git://github.com/ehabkost/qemu.git

[Qemu-devel] [PULL 05/46] i.mx7d: Add no-op/unimplemented PCIE PHY IP block

From: Andrey Smirnov Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to use PCIE. Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-...@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell ---

[Qemu-devel] [PULL 33/46] target/arm/helper: Remove unused include

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-7-phi...@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/helper.c

[Qemu-devel] [PULL 40/46] target/arm/vfp_helper: Move code around

From: Philippe Mathieu-Daudé To ease the review of the next commit, move the vfp_exceptbits_to_host() function directly after vfp_exceptbits_from_host(). Amusingly the diff shows we are moving vfp_get_fpscr(). Signed-off-by: Philippe Mathieu-Daudé Message-id:

[Qemu-devel] Python 2 in tests/vm (was Re: [PULL 0/8] Python queue, 2019-06-07)

On Mon, Jun 10, 2019 at 01:58:50PM +0100, Peter Maydell wrote: > On Fri, 7 Jun 2019 at 22:16, Eduardo Habkost wrote: > > > > The following changes since commit 185b7ccc11354cbd69b6d53bf8d831dd964f6c88: > > > > Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190607-2' into > > staging

[Qemu-devel] [PULL 29/46] target/arm: Makefile cleanup (ARM)

From: Philippe Mathieu-Daudé Group ARM objects together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-3-phi...@redhat.com Signed-off-by: Peter Maydell ---

[Qemu-devel] [PATCH] migration: move port_attr inside CONFIG_LINUX

Otherwise the FreeBSD compiler complains about an unused variable. Signed-off-by: Alex Bennée --- migration/rdma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/migration/rdma.c b/migration/rdma.c index 74cb2aa9f9..3036221ee8 100644 --- a/migration/rdma.c +++

[Qemu-devel] [PULL 12/46] hw/arm/aspeed: Add RTC to SoC

From: Joel Stanley All systems have an RTC. The IRQ is hooked up but the model does not use it at this stage. There is no guest code that uses it, so this limitation is acceptable. Signed-off-by: Joel Stanley Reviewed-by: Peter Maydell Message-id: 20190618165311.27066-5-...@kaod.org

[Qemu-devel] [PULL 04/46] i.mx7d: Add no-op/unimplemented APBH DMA module

From: Andrey Smirnov Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel. Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-...@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell ---

Re: [Qemu-devel] [PATCH] BootLinuxSshTest: Only use 'test' for unittest.TestCase method names

On Jul 1, 2019 5:23 PM, "Cleber Rosa" wrote: > > On Mon, Jul 01, 2019 at 05:03:33PM +0200, Aleksandar Markovic wrote: > > On Jul 1, 2019 4:22 PM, "Philippe Mathieu-Daudé" wrote: > > > > > > ping? > > > > > > On 6/7/19 7:49 PM, Philippe Mathieu-Daudé wrote: > > > > In commit f6e501a28ef9, Eduardo

[Qemu-devel] [PULL 43/46] target/arm/vfp_helper: Restrict the SoftFloat use to TCG

From: Philippe Mathieu-Daudé This code is specific to the SoftFloat floating-point implementation, which is only used by TCG. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-18-phi...@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell ---

[Qemu-devel] [PATCH v4 2/8] target/arm: Restrict semi-hosting to TCG

Per Peter Maydell: Semihosting hooks either SVC or HLT instructions, and inside KVM both of those go to EL1, ie to the guest, and can't be trapped to KVM. Let check_for_semihosting() return False when not running on TCG. Signed-off-by: Philippe Mathieu-Daudé --- v3: inline call to

[Qemu-devel] [PULL 13/46] aspeed: introduce a configurable number of CPU per machine

From: Cédric Le Goater The current models of the Aspeed SoCs only have one CPU but future ones will support SMP. Introduce a new num_cpus field at the SoC class level to define the number of available CPUs per SoC and also introduce a 'num-cpus' property to activate the CPUs configured for the

Re: [Qemu-devel] [PATCH 0/6] hw/arm: Use ARM_CPU_TYPE_NAME() and object_initialize_child()

Patchew URL: https://patchew.org/QEMU/20190701123108.12493-1-phi...@redhat.com/ Hi, This series failed build test on s390x host. Please find the details below. === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under the git checkout with # HEAD pointing to a commit that

[Qemu-devel] [PULL 38/46] target/arm: Declare get_phys_addr() function publicly

From: Philippe Mathieu-Daudé In the next commit we will split the TLB related routines of this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-12-phi...@redhat.com

[Qemu-devel] [PULL 23/46] hw/misc/aspeed_xdma: New device

From: Eddie James The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so enable it for all of those. Add trace events on the important

[Qemu-devel] [PULL 36/46] target/arm: Move the DC ZVA helper into op_helper

From: Samuel Ortiz Those helpers are a software implementation of the ARM v8 memory zeroing op code. They should be moved to the op helper file, which is going to eventually be built only when TCG is enabled. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Robert Bradford Signed-off-by:

[Qemu-devel] [PULL 02/46] hw/arm/msf2-som: Exit when the cpu is not the expected one

From: Philippe Mathieu-Daudé This machine correctly defines its default_cpu_type to cortex-m3 and report an error if the user requested another cpu_type, however it does not exit, and this can confuse users trying to use another core: $ qemu-system-arm -M emcraft-sf2 -cpu cortex-m4 -kernel

Re: [Qemu-devel] [PATCH] hw/misc/macio: Add the nvram as child of the MacIO south bridge

Patchew URL: https://patchew.org/QEMU/20190701123441.13412-1-phi...@redhat.com/ Hi, This series failed build test on s390x host. Please find the details below. === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under the git checkout with # HEAD pointing to a commit that

[Qemu-devel] [PATCH] tests: Update DSDT ACPI table for arm/virt board with PCDIMM related changes

PCDIMM hotplug addition updated the DSDT. Update the reference table. Signed-off-by: Eric Auger --- tests/data/acpi/virt/DSDT | Bin 18476 -> 18493 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index

[Qemu-devel] [PATCH v2 1/2] qdev: Add a no default uuid property

From: Corey Minyard This is for IPMI, which will behave differently if the UUID is not set. Signed-off-by: Corey Minyard Cc: Fam Zheng Cc: Michael S. Tsirkin Cc: Marc-André Lureau --- include/hw/qdev-properties.h | 7 +++ 1 file changed, 7 insertions(+) diff --git

Re: [Qemu-devel] [PATCH v9 0/2] Add Arm SBSA Reference Machine

Hi Peter, On Mon, Jul 01, 2019 at 03:54:24PM +0100, Peter Maydell wrote: > I've pointed out a number of issues with these patches, but they > all turn out to be very minor (mostly fixable by moving code between > patch 1 and 2). The other thing we need is a MAINTAINERS section for > the new

[Qemu-devel] [PULL 07/46] pci: designware: Update MSI mapping when MSI address changes

From: Andrey Smirnov MSI mapping needs to be update when MSI address changes, so add the code to do so. Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-...@nongnu.org Acked-by: Michael S. Tsirkin Reviewed-by: Peter Maydell

[Qemu-devel] [PULL 15/46] aspeed/timer: Fix behaviour running Linux

From: Joel Stanley The Linux kernel driver was updated in commit 4451d3f59f2a ("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an issue observed on hardware: > RELOAD register is loaded into COUNT register when the aspeed timer > is enabled, which means the next event may be

[Qemu-devel] [PATCH v4 6/8] RFC target/arm: Restrict R and M profiles to TCG

KVM is only able to run A profile cpus. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 290ef16e52..a0934a47ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c

[Qemu-devel] [PATCH v4 5/8] RFC target/arm: Do not build pre-ARMv7 cpus when using KVM

A KVM-only build won't be able to run pre-ARMv7 cpus, disable them. If KVM is not enabled, they are enabled by default. Signed-off-by: Philippe Mathieu-Daudé --- Sadly this does not work with --enable-tcg --enable-kvm dual config. --- default-configs/arm-softmmu.mak | 33

[Qemu-devel] [PULL 03/46] hw/arm/virt: Add support for Cortex-A7

From: Jan Kiszka Allow cortex-a7 to be used with the virt board; it supports the v7VE features and there is no reason to deny this type. Signed-off-by: Jan Kiszka Reviewed-by: Philippe Mathieu-Daudé Message-id: fc5404f7-4d1d-c28f-6e48-d8799c82a...@web.de Reviewed-by: Peter Maydell

Re: [Qemu-devel] [PATCH v3 18/27] target/arm: Restrict semi-hosting to TCG

On 7/1/19 5:38 PM, Philippe Mathieu-Daudé wrote: > On 7/1/19 5:25 PM, Peter Maydell wrote: >> On Mon, 1 Jul 2019 at 14:26, Philippe Mathieu-Daudé >> wrote: >>> >>> Per Peter Maydell: >>> >>> Semihosting hooks either SVC or HLT instructions, and inside KVM >>> both of those go to EL1, ie to

Re: [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model

On Mon, Jul 01, 2019 at 03:23:31PM +0800, Xiaoyao Li wrote: > On 6/28/2019 8:28 AM, Eduardo Habkost wrote: > > Add new version of Cascadelake-Server CPU model, setting > > stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR > > with some flags. > > > > The new feature will introduce a new host

[Qemu-devel] [PULL 11/46] hw: timer: Add ASPEED RTC device

From: Joel Stanley The RTC is modeled to provide time and date functionality. It is initialised at zero to match the hardware. There is no modelling of the alarm functionality, which includes the IRQ line. As there is no guest code to exercise this function that is acceptable for now.

Re: [Qemu-devel] [PULL 0/4] Trivial patches patches

On Wed, 26 Jun 2019 at 21:09, Laurent Vivier wrote: > > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50 +0100) > > are available in the Git

Re: [Qemu-devel] [PATCH v3 00/27] Support disabling TCG on ARM

On 7/1/19 8:41 PM, no-re...@patchew.org wrote: > Patchew URL: > https://patchew.org/QEMU/20190701132516.26392-1-phi...@redhat.com/ > > This series failed build test on s390x host. Please find the details below. > [...] > In file included from >

[Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally

From: Andrey Smirnov Expression to calculate update_msi_mapping in code handling writes to DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should be: !!root->msi.intr[0].enable ^ !!val; so that MSI mapping is updated when enabled transitions from either "none" -> "any" or

Re: [Qemu-devel] [PATCH v2 1/2] tests/acceptance: Add test of NeXTcube framebuffer using OCR

On 7/1/19 10:09 PM, Cleber Rosa wrote: > On Mon, Jul 01, 2019 at 05:34:35PM +0200, Philippe Mathieu-Daudé wrote: >> Add a test of the NeXTcube framebuffer using the Tesseract OCR >> engine on a screenshot of the framebuffer device. >> >> The test is very quick: >> >> $ avocado --show=app,ocr run

[Qemu-devel] [PULL 21/46] aspeed/smc: add a 'sdram_base' property

From: Cédric Le Goater The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model with this value. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Philippe Mathieu-Daudé Message-id:

[Qemu-devel] [PATCH v2 2/2] ipmi: Add a UUID device property

From: Corey Minyard Using the UUID that qemu generates probably isn't the best thing to do, allow it to be passed in via properties, and use QemuUUID for the type. If the UUID is not set, return an unsupported command error. This way we are not providing an all-zero (or randomly generated)

[Qemu-devel] [PULL 37/46] target/arm: Move CPU state dumping routines to cpu.c

From: Philippe Mathieu-Daudé Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-11-phi...@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 - target/arm/translate.h | 5 -

Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

On Mon, Jul 1, 2019 at 8:56 AM wrote: > > From: Jonathan Behrens > > QEMU currently always triggers an illegal instruction exception when > code attempts to read the time CSR. This is valid behavor, but only if > the TM bit in mcounteren is hardwired to zero. This change also > corrects

[Qemu-devel] [PULL 46/46] target/arm: Declare some M-profile functions publicly

From: Philippe Mathieu-Daudé In the next commit we will split the M-profile functions from this file. Some function will be called out of helper.c. Declare them in the "internals.h" header. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id:

[Qemu-devel] [PATCH v2 0/2] Add a UUID device property to IPMI

I sent this out a while ago and didn't really receive any comments then kind of forgot about it. These changes are not critical, but are really necessary for certain situations and testing to make things behave like they really should: * It allows a BMC to be created with no UUID, returning an

Re: [Qemu-devel] [PATCH 00/10] hw/pci-host: Clean the GT64120 north bridge

On Jun 25, 2019 12:31 AM, "Philippe Mathieu-Daudé" wrote: > > Hi, > > This series clean the gt64120 device. > It is no more target-dependent, and tracing is improved. > If nobody objects, I am going to select majority of the patches for mips queue scheduled tomorrow. Those that remain will be

Re: [Qemu-devel] [PATCH 00/10] hw/pci-host: Clean the GT64120 north bridge

On Jul 1, 2019 7:46 PM, "Philippe Mathieu-Daudé" wrote: > > Hi Aleksandar, > > On 7/1/19 7:16 PM, Aleksandar Markovic wrote: > > > > On Jun 25, 2019 12:31 AM, "Philippe Mathieu-Daudé" > > wrote: > >> > >> Hi, > >> > >> This series clean the gt64120 device. > >> It is no

Re: [Qemu-devel] [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3

On Mon, Jul 1, 2019 at 6:23 AM Anup Patel wrote: > > On Mon, Jul 1, 2019 at 6:12 PM Jonathan Cameron > wrote: > > > > On Fri, 28 Jun 2019 09:12:45 -0700 > > Alistair Francis wrote: > > > > > On Fri, Jun 28, 2019 at 2:47 AM Jonathan Cameron > > > wrote: > > > > > > > > On Thu, 27 Jun 2019

Re: [Qemu-devel] [RFC PATCH v2 0/3] python: refactor qemu/__init__.py

On Thu, Jun 27, 2019 at 05:32:17PM -0400, John Snow wrote: > I didn't actually mean to retain the RFC tag, but oh well. I'm queueing patch 1-2 for QEMU 4.1. Patch 3 will require more careful review. If you can demonstrate it fixes a problem in some use cases, we can call it a bug fix and

Re: [Qemu-devel] [PULL 0/2] Add a UUID device property to IPMI

On Mon, Jul 01, 2019 at 07:10:50PM +0100, Peter Maydell wrote: > On Thu, 27 Jun 2019 at 13:48, wrote: > > > > I believe we are not in softfreeze yet, and this is the only real > > fix I have for IPMI at the moment. > > > > This was posted Nov 2018 with little commentary. > > > > The following

[Qemu-devel] [PULL 24/46] aspeed: vic: Add support for legacy register interface

From: Andrew Jeffery The legacy interface only supported up to 32 IRQs, which became restrictive around the AST2400 generation. QEMU support for the SoCs started with the AST2400 along with an effort to reimplement and upstream drivers for Linux, so up until this point the consumers of the QEMU

Re: [Qemu-devel] [PATCH 0/6] hw/arm: Use ARM_CPU_TYPE_NAME() and object_initialize_child()

On Mon, 1 Jul 2019 at 19:13, Philippe Mathieu-Daudé wrote: > > On 7/1/19 7:56 PM, no-re...@patchew.org wrote: > > Patchew URL: > > https://patchew.org/QEMU/20190701123108.12493-1-phi...@redhat.com/ > > > > Hi, > > > > This series failed build test on s390x host. Please find the details below. >

[Qemu-devel] [Bug 1834613] Re: Crypto related operations failing on Alpine Linux on QEMU 4.0

Fix for that is already included in git master: 2a1224359008 target/ppc: Fix lxvw4x, lxvh8x and lxvb16x More fix for 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") are availabe: 77bd8937c03d target/ppc: Fix xvabs[sd]p, xvnabs[sd]p,

[Qemu-devel] [PATCH v2 2/3] qapi: implement block-dirty-bitmap-remove transaction action

It is used to do transactional movement of the bitmap (which is possible in conjunction with merge command). Transactional bitmap movement is needed in scenarios with external snapshot, when we don't want to leave copy of the bitmap in the base image. Signed-off-by: Vladimir Sementsov-Ogievskiy

[Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG

From: Philippe Mathieu-Daudé Under KVM, the kernel gets the HVC call and handle the PSCI requests. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-20-phi...@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 6 +- 1

Re: [Qemu-devel] [PATCH v9 0/2] Add Arm SBSA Reference Machine

Hi Leif and Peter, We talked with Hongbo about the takeover, so please add me as maintainer. On Mon, 1 Jul 2019 at 18:08, Leif Lindholm wrote: > Hi Peter, > > On Mon, Jul 01, 2019 at 03:54:24PM +0100, Peter Maydell wrote: > > I've pointed out a number of issues with these patches, but they >

[Qemu-devel] [PATCH v4 7/8] RFC target/arm: Do not build A/M-profile cpus when using KVM

A KVM-only build won't be able to run A or M-profile cpus, disable them. If KVM is not enabled, they are enabled by default. Signed-off-by: Philippe Mathieu-Daudé --- Sadly this does not work with --enable-tcg --enable-kvm dual config. --- default-configs/arm-softmmu.mak | 14 ++

[Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container

From: Cédric Le Goater The RAM memory region is defined after the SoC is realized when the SDMC controller has checked that the defined RAM size for the machine is correct. This is problematic for controller models requiring a link on the RAM region, for DMA support in the SMC controller for

[Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part

From: Hongbo Zhang Following the previous patch, this patch adds peripheral devices to the newly introduced SBSA-ref machine. Signed-off-by: Hongbo Zhang Message-id: 1561890034-15921-3-git-send-email-hongbo.zh...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell ---

Re: [Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes

On Mon, Jul 1, 2019 at 12:30 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 6/30/19 7:58 PM, Mark Cave-Ayland wrote: > > I don't have space for a full set of images on the G4, however I've > tried boot tests > > on installer CDs for MacOS 9, OS X 10.2, Linux and HelenOS and it

[Qemu-devel] [PATCH v4 4/8] RFC target/arm: Restrict pre-ARMv7 cpus to TCG

KVM requires at least a ARMv7 cpu. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 12 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ca718fb38f..290ef16e52 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1643,6

Re: [Qemu-devel] [PATCH 0/6] hw/arm: Use ARM_CPU_TYPE_NAME() and object_initialize_child()

On 7/1/19 7:56 PM, no-re...@patchew.org wrote: > Patchew URL: > https://patchew.org/QEMU/20190701123108.12493-1-phi...@redhat.com/ > > Hi, > > This series failed build test on s390x host. Please find the details below. > > CC hw/dma/i8257.o > CC hw/dma/xilinx_axidma.o >

Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

On Mon, 1 Jul 2019 at 19:09, Alistair Francis wrote: > > On Mon, 2019-07-01 at 19:01 +0100, Peter Maydell wrote: > > On Mon, 1 Jul 2019 at 18:50, Alistair Francis < > > alistair.fran...@wdc.com> wrote: > > > PS: It seems like there are still some issues with this patch so > > > maybe > > > it's

[Qemu-devel] [PATCH v4 0/8] Support disabling TCG on ARM

Paolo motived me to salvage this (other!) previous series fromi Samuel Ortiz (NEMU project). v1 cover from Samuel [1]: This patchset allows for building and running ARM targets with TCG disabled. It splits the target/arm/helper.c file into logical TCG and non TCG dependent files so that

Re: [Qemu-devel] [PATCH 1/5] tests/acceptance: Add test that runs NetBSD installer on PRep/40p

Le 27/06/2019 à 14:00, Philippe Mathieu-Daudé a écrit : typo "PRep" -> "PReP" in patch subject On 6/27/19 1:01 PM, Philippe Mathieu-Daudé wrote: User case from: http://mail-index.netbsd.org/port-prep/2017/04/11/msg000112.html Signed-off-by: Philippe Mathieu-Daudé ---

[Qemu-devel] [PATCH v2 0/3] qapi: block-dirty-bitmap-remove transaction action

Hi, this is a proposal based off of Vladimir's patchset: [Qemu-devel] [PATCH 0/4] qapi: block-dirty-bitmap-remove transaction action It replaces patches two and three with a modified patch (now patch 2) that foregoes the need for a hide()/unhide() bitmap API. I think it's suitable as a smaller

[Qemu-devel] [PULL 00/46] target-arm queue

-target-arm-20190701 for you to fetch changes up to 787a7e76c2e93a48c47b324fea592c9910a70483: target/arm: Declare some M-profile functions publicly (2019-07-01 17:29:01 +0100) target-arm queue: * hw/arm/boot: fix direct kernel boot

[Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate

From: Philippe Mathieu-Daudé Reviewed-by: Robert Bradford Reviewed-by: Samuel Ortiz Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-6-phi...@redhat.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 7 +++ 1 file changed, 7

Re: [Qemu-devel] [PATCH v3 08/15] hw/i386/pc: Let fw_cfg_init() use the generic MachineState

On 7/1/19 6:01 PM, Christophe de Dinechin wrote: > Philippe Mathieu-Daudé writes: > >> We removed the PCMachineState access, we can now let the fw_cfg_init() >> function to take a generic MachineState object. > > to take -> take > >> >> Suggested-by: Samuel Ortiz >> Signed-off-by: Philippe

[Qemu-devel] [PATCH v2 1/3] blockdev: reduce aio_context locked sections in bitmap add/remove

From: Vladimir Sementsov-Ogievskiy Commit 0a6c86d024c52 returned these locks back to add/remove functionality, to protect from intersection of persistent bitmap related IO with other IO. But other bitmap-related functions called here are unrelated to the problem, and there are no needs to keep

[Qemu-devel] [PULL 28/46] target/arm: Makefile cleanup (Aarch64)

From: Philippe Mathieu-Daudé Group Aarch64 rules together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-2-phi...@redhat.com Signed-off-by: Peter Maydell ---

[Qemu-devel] [PULL 22/46] aspeed: Add support for the swift-bmc board

From: Adriana Kobylak The Swift board is an OpenPOWER system hosting POWER processors. Add support for their BMC including the I2C devices as found on HW. Signed-off-by: Adriana Kobylak Reviewed-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-20-...@kaod.org

[Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space

From: Cédric Le Goater This will simplify the definition of new SoCs, like the AST2600 which should use a different CPU and a different IRQ number layout. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley Message-id:

Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

On Mon, 2019-07-01 at 19:01 +0100, Peter Maydell wrote: > On Mon, 1 Jul 2019 at 18:50, Alistair Francis < > alistair.fran...@wdc.com> wrote: > > On Mon, 2019-07-01 at 17:54 +0100, Peter Maydell wrote: > > > On Thu, 27 Jun 2019 at 16:24, Palmer Dabbelt > > > wrote: > > > > From: Alistair Francis

[Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link

From: Cédric Le Goater It has never been used as far as I can tell from the git history. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-13-...@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 2 -- 1 file changed, 2 deletions(-) diff

[Qemu-devel] [PULL 45/46] target/arm: Declare arm_log_exception() function publicly

From: Philippe Mathieu-Daudé In few commits we will split the M-profile functions from this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Since it is in the middle of a block of M profile functions, move it previous to this block to ease the

[Qemu-devel] [PULL 34/46] target/arm: Fix multiline comment syntax

From: Philippe Mathieu-Daudé Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-8-phi...@redhat.com

[Qemu-devel] [PULL 17/46] aspeed/timer: Fix match calculations

From: Andrew Jeffery If the match value exceeds reload then we don't want to include it in calculations for the next event. Signed-off-by: Andrew Jeffery Signed-off-by: Cédric Le Goater Message-id: 20190618165311.27066-10-...@kaod.org Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c

[Qemu-devel] [PATCH v4 8/8] target/arm: Do not build TCG objects when TCG is off

We can now safely turn all TCG dependent build off when CONFIG_TCG is off. This allows building ARM binaries with --disable-tcg. Signed-off-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- v3: complete rewrite of patch content, removed R-b tags --- target/arm/Makefile.objs | 4

Re: [Qemu-devel] [PULL 0/2] Add a UUID device property to IPMI

On Mon, 1 Jul 2019 at 19:25, Corey Minyard wrote: > > On Mon, Jul 01, 2019 at 07:10:50PM +0100, Peter Maydell wrote: > > I have to say I'm not entirely happy with applying a pullreq > > with patches that are unreviewed and were last posted on list > > over six months ago. Can you post a v2 to try

Re: [Qemu-devel] [RFC PATCH 10/10] hw/pci-host/gt64120: Clean the decoded address space

Cc'ing the kernel folks. On 6/25/19 12:28 AM, Philippe Mathieu-Daudé wrote: > The SysAd bus is split in various address spaces. > Declare the different regions separately, this helps a lot > while tracing different access while debugging. > > We also add the PCI1 ranges. > > See 'GT-64120A

[Qemu-devel] Question about bdrv_co_invalidate_cache

Hi, I just want to clarify the purpose of bdrv_co_invalidate_cache callback. IIUC on of the purposes of this callback is to "activate" BDRV (opposite of the bdrv_inactivate callback) on migration end, right? E.g, if we have a custom BDRV which is backed by some network block storage with

Re: [Qemu-devel] [PATCH] tests/machine-none: Test recent MIPS cpus

On Jul 1, 2019 4:53 PM, "Aleksandar Markovic" wrote: > > > On Jul 1, 2019 4:45 PM, "Philippe Mathieu-Daudé" wrote: > > > > The MIPS I7200 got added in commit d45942d908e, and the I6500 > > in commit ca1ffd14ed8. > > Extend the coverage on the little-endian machines. > > The 4Kc and 20Kc are

[Qemu-devel] [PATCH v2 3/3] iotests: test bitmap moving inside 254

From: Vladimir Sementsov-Ogievskiy Test persistent bitmap copying with and without removal of original bitmap. Signed-off-by: Vladimir Sementsov-Ogievskiy Signed-off-by: John Snow --- tests/qemu-iotests/254 | 30 +- tests/qemu-iotests/254.out | 82

Re: [Qemu-devel] [PATCH v9 0/2] Add Arm SBSA Reference Machine

On Mon, 1 Jul 2019 at 17:23, Radoslaw Biernacki wrote: > > Hi Leif and Peter, > > We talked with Hongbo about the takeover, so please add me as maintainer. Thanks for volunteering; I've updated the MAINTAINERS entry in my target-arm queue as Leif suggests. thanks -- PMM

Re: [Qemu-devel] [PATCH 00/10] hw/pci-host: Clean the GT64120 north bridge

Hi Aleksandar, On 7/1/19 7:16 PM, Aleksandar Markovic wrote: > > On Jun 25, 2019 12:31 AM, "Philippe Mathieu-Daudé" > wrote: >> >> Hi, >> >> This series clean the gt64120 device. >> It is no more target-dependent, and tracing is improved. >> > > If nobody objects, I am

[Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW

From: Andrey Smirnov Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches that of i.MX6: * INTD/MSI122 * INTC123 * INTB124 * INTA125 Fix all of the relevant code to reflect that fact. Needed by latest Linux kernels. (Reference: Linux

Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2

On Fri, 28 Jun 2019 at 18:32, Palmer Dabbelt wrote: > > merged tag 'mips-queue-jun-21-2019' > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50

[Qemu-devel] [PULL 30/46] target/arm: Makefile cleanup (KVM)

From: Philippe Mathieu-Daudé Group KVM rules together. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-4-phi...@redhat.com Signed-off-by: Peter Maydell --- target/arm/Makefile.objs | 9 + 1 file changed, 5 insertions(+), 4 deletions(-)

[Qemu-devel] [PULL 39/46] target/arm: Move TLB related routines to tlb_helper.c

From: Philippe Mathieu-Daudé These routines are TCG specific. The arm_deliver_fault() function is only used within the new helper. Make it static. Suggested-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190701132516.26392-13-phi...@redhat.com Reviewed-by: Peter Maydell

Re: [Qemu-devel] [PATCH v4 0/4] Kconfig dependencies for some MIPS machines

On Jul 1, 2019 1:26 PM, "Philippe Mathieu-Daudé" wrote: > > Express the MIPS machine dependencies with Kconfig. > > Various issues prevent to use Kconfig with the Boston and Malta > boards. They will be switched later. > I am going to select the whole series for mips queue scheduled tomorrow.

Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

On Mon, 1 Jul 2019 at 18:50, Alistair Francis wrote: > > On Mon, 2019-07-01 at 17:54 +0100, Peter Maydell wrote: > > On Thu, 27 Jun 2019 at 16:24, Palmer Dabbelt > > wrote: > > > From: Alistair Francis > > > > > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary. > > > > > >

Re: [Qemu-devel] [PATCH 5/5] iotests: Add new case to 030

On 28/06/2019 01:32, Max Reitz wrote: > We recently removed the dependency of the stream job on its base node. > That makes it OK to use a commit filter node there. Test that. > > Signed-off-by: Max Reitz > --- > tests/qemu-iotests/030 | 25 + >

[Qemu-devel] [PULL 01/46] hw/arm/boot: fix direct kernel boot with initrd

From: Andrew Jones Fix the condition used to check whether the initrd fits into RAM; in some cases if an initrd was also passed on the command line we would get an error stating that it was too big to fit into RAM after the kernel. Despite the error the loader continued anyway, though, so also

Re: [Qemu-devel] [PATCH v3 00/27] Support disabling TCG on ARM

On Mon, 1 Jul 2019 at 16:45, Philippe Mathieu-Daudé wrote: > > On 7/1/19 5:41 PM, Peter Maydell wrote: > > I have applied to target-arm.next: > > 1-12 > > 14-17 > > 19-21 > > > > I had comments about 13 and 18. 22 has a conflict when I try to apply it: > > I think this is just accidental

Re: [Qemu-devel] [PATCH 3/5] iotests: Compare error messages in 030

On 28/06/2019 01:32, Max Reitz wrote: > Currently, 030 just compares the error class, which does not say > anything. > > Before HEAD^ added throttling to test_overlapping_4, that test actually > usually failed because node2 was already gone, not because it was the > commit and stream job were

Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

On Thu, 27 Jun 2019 at 16:24, Palmer Dabbelt wrote: > > From: Alistair Francis > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary. > > Signed-off-by: Alistair Francis > Reviewed-by: Bin Meng > Tested-by: Bin Meng > Signed-off-by: Palmer Dabbelt > --- > .gitmodules

[Qemu-devel] [PULL 14/46] aspeed: add support for multiple NICs

From: Cédric Le Goater The Aspeed SoCs have two MACs. Extend the Aspeed model to support a second NIC. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-7-...@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 3 ++-

Re: [Qemu-devel] [PATCH 2/5] iotests: Fix throttling in 030

On 28/06/2019 01:32, Max Reitz wrote: > Currently, TestParallelOps in 030 creates images that are too small for > job throttling to be effective. This is reflected by the fact that it > never undoes the throttling. > > Increase the image size and undo the throttling when the job should be >

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