Until recently, target install used to recurse into target directories
in its recipe: it ran make install in a for-loop. Since target
install depends on target all, this trivially ensured we run the
sub-make install only after completing target all.
Commit 1338a4b "Makefile: Reuse all's
Did this get stuck?
Fei Li writes:
> Hi,
>
> This idea comes from BiteSizedTasks, and this patch series implement
> the error checking of qemu_thread_create: make qemu_thread_create
> return a flag to indicate if it succeeded rather than failing with
> an error; make all callers check it.
>
>
On 7/12/19 12:32 AM, Jan Bobek wrote:
> insnv allows emitting variable-length instructions in little-endian or
> big-endian byte order; it subsumes functionality of former insn16()
> and insn32() functions.
>
> randint can reliably generate signed or unsigned integers of arbitrary
> width.
>
>
From: Sarah Harris
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
arch_init.c | 2 ++
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
include/disas/dis-asm.h | 6 ++
include/sysemu/arch_init.h | 1 +
This includes:
- TCG translations for each instruction
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 2888
1 file changed, 2888 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c
From: Sarah Harris
A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs
include a lot of on-board peripherals.
Signed-off-by: Michael Rolnik
---
hw/Kconfig | 1 +
From: Sarah Harris
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Signed-off-by: Michael Rolnik
---
gdb-xml/avr-cpu.xml| 49
target/avr/cpu-param.h | 37 +++
target/avr/cpu.c | 579
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
---
target/avr/insn.decode | 175 +
1 file changed, 175 insertions(+)
create mode 100644 target/avr/insn.decode
diff --git
From: Sarah Harris
Stubs for unimplemented instructions and helpers for instructions that need to
interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex
peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to
generate
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support
Since the start addr is already checked, to make sure the range is
aligned, checking the length is enough.
Signed-off-by: Wei Yang
---
exec.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/exec.c b/exec.c
index 50ea9c5aaa..8fa980baae 100644
--- a/exec.c
+++ b/exec.c
This implements the H_TPM_COMM hypercall, which is used by an
Ultravisor to pass TPM commands directly to the host's TPM device, or
a TPM Resource Manager associated with the device.
This also introduces a new pseries machine option which is used to
configure what TPM device to pass commands to,
On Tue, Jul 09, 2019 at 05:49:17PM +0800, Kirti Wankhede wrote:
> Flow during _RESUMING device state:
> - If Vendor driver defines mappable region, mmap migration region.
> - Load config state.
> - For data packet, till VFIO_MIG_FLAG_END_OF_STATE is not reached
> - read data_size from packet,
On Tue, Jul 09, 2019 at 05:49:16PM +0800, Kirti Wankhede wrote:
> Added .save_live_pending, .save_live_iterate and .save_live_complete_precopy
> functions. These functions handles pre-copy and stop-and-copy phase.
>
> In _SAVING|_RUNNING device state or pre-copy phase:
> - read pending_bytes
> -
On Thu, Jul 11, 2019 at 10:34:27AM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> Commit 6b6712efccd3 ('ram: Split dirty bitmap by RAMBlock') changes the
>> parameter of postcopy_send_discard_bm_ram(), while left the document
>> part untouched.
>>
>>
These patches are also available at:
https://github.com/mdroth/qemu/commits/spapr-tpm-hcall-v0
This patchset implements the H_TPM_COMM hypercall, which provides a way
for an Ultravisor to pass raw TPM commands on to a host's TPM device,
either directly or through a TPM Resource Manager (needed
For now this only covers hcalls relating to TPM communication since
it's the only one particularly important from a QEMU perspective atm,
but others can be added here where it makes sense.
The full specification for all hcalls/ucalls will eventually be made
available in the public/OpenPower
On Wed, Jul 03, 2019 at 07:54:57AM +0200, Cédric Le Goater wrote:
> On 03/07/2019 04:07, David Gibson wrote:
> > On Sun, Jun 30, 2019 at 10:45:59PM +0200, Cédric Le Goater wrote:
> >> This is to perform lookups in the NVT table when a vCPU is dispatched
> >> and possibly resend interrupts.
> >
>
On Thu, Jun 13, 2019 at 11:37:45AM +1000, Alexey Kardashevskiy wrote:
>
>
> On 12/06/2019 16:11, David Gibson wrote:
> > On Thu, Jun 06, 2019 at 02:09:19PM +1000, Alexey Kardashevskiy wrote:
> >> The pseries guests do not normally allocate PCI resouces and rely on
> >> the system firmware doing
On 2019/7/11 21:05, Alex Bennée wrote:
Commit a5e0b3311 removed these in favour of querying machine
properties. Remove the extern declarations as well.
Signed-off-by: Alex Bennée
Cc: Like Xu
Reviewed-by: Like Xu
---
include/sysemu/sysemu.h | 2 --
1 file changed, 2 deletions(-)
diff
On Tue, Jul 09, 2019 at 05:49:18PM +0800, Kirti Wankhede wrote:
> Dirty page tracking (.log_sync) is part of RAM copying state, where
> vendor driver provides the bitmap of pages which are dirtied by vendor
> driver through migration region and as part of RAM copy, those pages
> gets copied to
On Fri, Jul 12, 2019 at 03:08:31AM +0800, Kirti Wankhede wrote:
>
>
> On 7/11/2019 9:53 PM, Dr. David Alan Gilbert wrote:
> > * Yan Zhao (yan.y.z...@intel.com) wrote:
> >> On Thu, Jul 11, 2019 at 06:50:12PM +0800, Dr. David Alan Gilbert wrote:
> >>> * Yan Zhao (yan.y.z...@intel.com) wrote:
>
Patchew URL:
https://patchew.org/QEMU/20190711172845.31035-1-eric.au...@redhat.com/
Hi,
This series failed build test on s390x host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit
On Fri, Jul 12, 2019 at 12:23:15AM +0800, Dr. David Alan Gilbert wrote:
> * Yan Zhao (yan.y.z...@intel.com) wrote:
> > On Thu, Jul 11, 2019 at 06:50:12PM +0800, Dr. David Alan Gilbert wrote:
> > > * Yan Zhao (yan.y.z...@intel.com) wrote:
> > > > Hi Kirti,
> > > > There are still unaddressed
Add AVX instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 1362 ++
1 file changed, 1362 insertions(+)
diff --git a/x86.risu b/x86.risu
index 177979a..03ffc89 100644
--- a/x86.risu
+++ b/x86.risu
@@ -29,6
Add AVX2 instructions to the configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 1239 ++
1 file changed, 1239 insertions(+)
diff --git a/x86.risu b/x86.risu
index 03ffc89..1705a8e 100644
--- a/x86.risu
+++ b/x86.risu
@@ -91,6 +91,12
Add SSE2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 734 +++
1 file changed, 734 insertions(+)
diff --git a/x86.risu b/x86.risu
index 2d963fc..b9d424e 100644
--- a/x86.risu
+++ b/x86.risu
@@ -23,48
Add SSE4.1 and SSE4.2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 270 +++
1 file changed, 270 insertions(+)
diff --git a/x86.risu b/x86.risu
index 6f89a80..bc6636e 100644
--- a/x86.risu
+++ b/x86.risu
The module risugen_x86_constraints.pm provides environment for
evaluating x86 "!constraints" blocks. This is facilitated by the
single exported function eval_constraints_block.
Signed-off-by: Jan Bobek
---
risugen_x86_constraints.pm | 154 +
1 file changed,
extract_fields can extract named variable fields from an opcode; it
returns a hash which can be then passed as environment parameter to
eval_block. More importantly, this allows the caller to augment the
block environment with more variables, if they wish to do so.
Signed-off-by: Jan Bobek
---
The module risugen_x86_asm.pm exports named register constants and
asm_insn_* family of functions, which greatly simplify emission of x86
instructions.
Signed-off-by: Jan Bobek
---
risugen_x86_asm.pm | 918 +
1 file changed, 918 insertions(+)
create
Accept all instructions whose bit length is divisible by 8. Note that
the maximum instruction length (as specified in the config file) is 32
bits, hence this change permits instructions which are 8 bits or 24
bits long (16-bit instructions have already been considered valid).
Note that while
insnv allows emitting variable-length instructions in little-endian or
big-endian byte order; it subsumes functionality of former insn16()
and insn32() functions.
randint can reliably generate signed or unsigned integers of arbitrary
width.
Signed-off-by: Jan Bobek
---
risugen_common.pm | 55
Add SSSE3 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 160 +++
1 file changed, 160 insertions(+)
diff --git a/x86.risu b/x86.risu
index d40b9df..6f89a80 100644
--- a/x86.risu
+++ b/x86.risu
@@ -286,6
This is v3 of the patch series posted in [1] and [2]. Note that this
is the first fully-featured patch series implementing all desired
functionality, including (V)LDMXCSR and VSIB-based instructions like
VGATHER*.
While implementing the last bits required in order to support VGATHERx
The module risugen_x86_memory.pm provides environment for evaluating
x86 "!memory" blocks. This is facilitated by the single exported
function eval_memory_block.
Signed-off-by: Jan Bobek
---
risugen_x86_memory.pm | 87 +++
1 file changed, 87 insertions(+)
risugen_x86.pm is the main backend module for Intel i386 and x86_64
architectures; it orchestrates generation of the test code with
support from the rest of risugen_x86_* modules.
Signed-off-by: Jan Bobek
---
risugen_x86.pm | 518 +
1 file
Add SSE instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 318 +++
1 file changed, 318 insertions(+)
diff --git a/x86.risu b/x86.risu
index 208ac16..2d963fc 100644
--- a/x86.risu
+++ b/x86.risu
@@ -35,6
Add AES-NI and PCLMULQDQ instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 45 +
1 file changed, 45 insertions(+)
diff --git a/x86.risu b/x86.risu
index bc6636e..177979a 100644
--- a/x86.risu
+++ b/x86.risu
@@ -886,6
Add SSE3 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 50 ++
1 file changed, 50 insertions(+)
diff --git a/x86.risu b/x86.risu
index b9d424e..d40b9df 100644
--- a/x86.risu
+++ b/x86.risu
@@ -161,6 +161,26 @@
This flag instructs the x86 backend to emit 64-bit (rather than
32-bit) code.
Signed-off-by: Jan Bobek
---
risugen | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 0c859aa..50920eb 100755
--- a/risugen
+++ b/risugen
@@ -10,6 +10,7 @@
# Peter
Add an x86 configuration file with all MMX instructions.
Signed-off-by: Jan Bobek
---
x86.risu | 321 +++
1 file changed, 321 insertions(+)
create mode 100644 x86.risu
diff --git a/x86.risu b/x86.risu
new file mode 100644
index
The --xfeatures option is modelled after identically-named option to
RISU itself; it allows the user to specify which vector registers
should be initialized, so that the test image doesn't try to access
registers which may not be present at runtime. Note that it is still
the user's responsibility
Patchew URL:
https://patchew.org/QEMU/20190711173933.31203-1-eric.au...@redhat.com/
Hi,
This series failed build test on s390x host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit
On 7/11/19 9:57 AM, Richard Henderson wrote:
> On 7/11/19 3:29 PM, Jan Bobek wrote:
>> However, I downloaded a fresh copy of Intel SDM off the Intel website
>> this morning (just to make sure) and in Volume 2B, Section "4.3
>> Instructions (M-U)," page 4-208 titled "PADDB/PADDW/PADDD/PADDQ—Add
>>
On Thu, Jul 11, 2019 at 7:32 PM Laurent Vivier wrote:
>
> Notes:
> v4: [lv] timeval64 and timespec64 are { long long , long }
>
> +STRUCT(timeval64, TYPE_LONGLONG, TYPE_LONG)
> +
> +STRUCT(timespec64, TYPE_LONGLONG, TYPE_LONG)
> +
This still doesn't look right, see my earlier comment about
The function declarations for pci_cap_slot_get and
pci_cap_slot_write_config call the argument "slot_ctl", but the function
definitions and all the call sites drop the 'o' and call it "slt_ctl".
Let's be consistent.
Reported-by: Peter Maydell
Signed-off-by: Michael S. Tsirkin
---
Fix
Signed-off-by: Max Reitz
---
tests/qemu-iotests/259 | 71 ++
tests/qemu-iotests/259.out | 20 +++
tests/qemu-iotests/group | 1 +
3 files changed, 92 insertions(+)
create mode 100755 tests/qemu-iotests/259
create mode 100644
If a protocol driver does not support image creation, we can see whether
maybe the file exists already. If so, just truncating it will be
sufficient.
Signed-off-by: Max Reitz
---
block.c | 77 -
1 file changed, 65 insertions(+), 12
file-posix does not need to basically duplicate our fallback truncate
implementation; and sheepdog can fall back to it for "shrinking" files.
Signed-off-by: Max Reitz
---
block/file-posix.c | 21 +
block/sheepdog.c | 2 +-
2 files changed, 2 insertions(+), 21 deletions(-)
When nbd_close() is called from a coroutine, the connection_co never
gets to run, and thus nbd_teardown_connection() hangs.
This is because aio_co_enter() only puts the connection_co into the main
coroutine's wake-up queue, so this main coroutine needs to yield and
reschedule itself to let the
Hi,
Some protocol drivers do not really support file truncation but still
implement .bdrv_co_truncate(): They just don’t do anything when asked to
shrink a file. This is reflected by qemu-img, which warns if you resize
a file and it has the exact same length afterwards as it had before.
We can
If a protocol driver does not support truncation, we call fall back to
effectively not doing anything if the new size is less than the actual
file size. This is what we have been doing for some host device drivers
already.
The only caveat is that we have to zero out everything in the first
Re-read the timebase before migrate was ported from x86 commit:
6053a86fe7bd: kvmclock: reduce kvmclock difference on migration
The clock move makes the guest knows about the paused time between
the stop and migrate commands. This is an issue in an already-paused
VM because some side effects,
On 7/11/19 12:47 PM, Dr. David Alan Gilbert wrote:
> * Singh, Brijesh (brijesh.si...@amd.com) wrote:
>> When memory encryption is enabled in VM, the guest pages will be
>> encrypted with the guest-specific key, to protect the confidentiality
>> of data in transit. To support the live migration
On 7/11/19 4:59 AM, Dr. David Alan Gilbert wrote:
> * Singh, Brijesh (brijesh.si...@amd.com) wrote:
>> AMD SEV encrypts the memory of VMs and because this encryption is done using
>> an address tweak, the hypervisor will not be able to simply copy ciphertext
>> between machines to migrate a VM.
On 7/11/19 12:34 PM, Dr. David Alan Gilbert wrote:
> * Singh, Brijesh (brijesh.si...@amd.com) wrote:
>> When memory encryption is enabled, the guest memory will be encrypted with
>> the guest specific key. The patch introduces RAM_SAVE_FLAG_ENCRYPTED_PAGE
>> flag to distinguish the encrypted
slt ctl/status are passed in incorrect order.
Fix this up.
Signed-off-by: Michael S. Tsirkin
Reported-by: Peter Maydell
---
hw/pci-bridge/xio3130_downstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/xio3130_downstream.c
The function declarations for pci_cap_slot_get and
pci_cap_slot_write_config call the argument "slot_ctl", but the function
definitions and all the call sites drop the 'o' and call it "slt_ctl".
Let's be consistent.
Reported-by: Peter Maydell
Signed-off-by: Michael S. Tsirkin
---
On 2019-07-10 21:57, Marc-André Lureau wrote:
> On Tue, Jul 9, 2019 at 10:57 PM Kővágó, Zoltán wrote:
>>
>> They just called audio_pcm_sw_read/write anyway, so it makes no sense
>> to have them too. (The noaudio's read is the only exception, but it
>> should work with the generic code too.)
>
>
On 7/11/2019 5:43 PM, Dr. David Alan Gilbert wrote:
> * Kirti Wankhede (kwankh...@nvidia.com) wrote:
>> VM state change handler gets called on change in VM's state. This is used to
>> set
>> VFIO device state to _RUNNING.
>> VM state change handler, migration state change handler and log_sync
On 2019-07-10 21:30, Marc-André Lureau wrote:
> On Tue, Jul 9, 2019 at 11:00 PM Kővágó, Zoltán wrote:
>>
>> This means you should probably stop using -soundhw (as it doesn't allow
>> you to specify any options) and add the device manually with -device.
>> The exception is pcspk, it's currently
On 7/11/2019 9:53 PM, Dr. David Alan Gilbert wrote:
> * Yan Zhao (yan.y.z...@intel.com) wrote:
>> On Thu, Jul 11, 2019 at 06:50:12PM +0800, Dr. David Alan Gilbert wrote:
>>> * Yan Zhao (yan.y.z...@intel.com) wrote:
Hi Kirti,
There are still unaddressed comments to your patches v4.
On 2019-07-11 16:37, Markus Armbruster wrote:
> "Zoltán Kővágó" writes:
>
>> On 2019-07-10 06:06, Markus Armbruster wrote:
>>> "Kővágó, Zoltán" writes:
>>>
Audio functions no longer access glob_audio_state, instead they get an
AudioState as a parameter. This is required in order to
* Singh, Brijesh (brijesh.si...@amd.com) wrote:
> The SEV VMs have concept of private and shared memory. The private memory
> is encrypted with guest-specific key, while shared memory may be encrypted
> with hyperivosr key. The KVM_GET_PAGE_ENC_BITMAP can be used to get a
> bitmap indicating
lgtm, thanks Paolo
Reviewed-by: Julio Montes
Tested-by: Julio Montes
On Thu, 2019-07-11 at 19:22 +0200, Paolo Bonzini wrote:
> CONFIG_TPM is defined to a rather weird $(CONFIG_SOFTMMU) so that it
> expands to the right thing in hw/Makefile.objs. This however is not
> needed anymore and it
Let's introduce two helpers that allow to DMA map/unmap a RAM
section. Those helpers will be called for nested stage setup in
another call site. Also the vfio_listener_region_add/del()
structure may be clearer.
Signed-off-by: Eric Auger
---
hw/vfio/common.c | 177
* Singh, Brijesh (brijesh.si...@amd.com) wrote:
> Signed-off-by: Brijesh Singh
> ---
> docs/amd-memory-encryption.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/amd-memory-encryption.txt b/docs/amd-memory-encryption.txt
> index 43bf3ee6a5..abb9a976f5 100644
>
On 7/11/19 8:37 AM, Max Reitz wrote:
> On 11.07.19 05:21, John Snow wrote:
>>
>> On 7/10/19 4:46 PM, Max Reitz wrote:
>>> On 10.07.19 21:00, John Snow wrote:
On 7/10/19 1:14 PM, Max Reitz wrote:
> On 10.07.19 03:05, John Snow wrote:
>
> Hm. How useful is bitmap support for
On 7/11/19 7:22 PM, Paolo Bonzini wrote:
> CONFIG_TPM is defined to a rather weird $(CONFIG_SOFTMMU) so that it
> expands to the right thing in hw/Makefile.objs. This however is not
> needed anymore and it has a corresponding hack in create_config
> to turn it into "#define CONFIG_TPM 1". Clean
We convert iommu_fault structs received from the kernel
into the data struct used by the emulation code and record
the evnts into the virtual event queue.
Signed-off-by: Eric Auger
---
v3 -> v4:
- fix compil issue on mingw
Exhaustive mapping remains to be done
---
hw/arm/smmuv3.c | 71
* Singh, Brijesh (brijesh.si...@amd.com) wrote:
> When memory encryption is enabled in VM, the guest pages will be
> encrypted with the guest-specific key, to protect the confidentiality
> of data in transit. To support the live migration we need to use
> platform specific hooks to access the
Cc: Marcelo Tosatti
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f2d868f..bc8853d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -902,7 +902,7 @@ static
Set up the fault region which is composed of the actual fault
queue (mmappable) and a header used to handle it. The fault
queue is mmapped.
Signed-off-by: Eric Auger
---
v4 -> v5:
- use a single DMA FAULT region. No version selection anymore
---
hw/vfio/pci.c | 64
Let's introduce two helpers that allow to DMA map/unmap a RAM
section. Those helpers will be called for nested stage setup in
another call site. Also the vfio_listener_region_add/del()
structure may be clearer.
Signed-off-by: Eric Auger
---
hw/vfio/common.c | 177
We register the stage1 MSI bindings when enabling the vectors
and we unregister them on container disconnection.
Signed-off-by: Eric Auger
---
v4 -> v5:
- use VFIO_IOMMU_SET_MSI_BINDING
v2 -> v3:
- only register the notifier if the IOMMU translates MSIs
- record the msi bindings in a
Let's introduce a hostwin_from_range() helper that returns the
hostwin encapsulating an IOVA range or NULL if non is found.
This improves the readibility of callers and removes the usage
of hostwin_found.
Signed-off-by: Eric Auger
---
hw/vfio/common.c | 36 +---
In case PASID PciOps are set for the device we call
the set_pasid_table() callback on each STE update.
This allows to pass the guest stage 1 configuration
to the host and apply it at physical level.
Signed-off-by: Eric Auger
---
v4 -> v5:
- Use PciOps instead of config notifiers
v3 -> v4:
-
Let's propagate the leaf attribute throughout the invalidation path.
This hint is used to reduce the scope of the invalidations to the
last level of translation. Not enforcing it induces large performance
penalties in nested mode.
Signed-off-by: Eric Auger
---
hw/arm/smmuv3.c | 16
Now all the bricks are there, let allow VFIO/SMMUv3 use case.
Signed-off-by: Eric Auger
---
hw/vfio/common.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 8a2d201058..c849b084bf 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@
In case we detect the address space is translated by
a virtual IOMMU which requires HW nested paging to
integrate with VFIO, let's set up the container with
the VFIO_TYPE1_NESTING_IOMMU iommu_type.
Signed-off-by: Eric Auger
---
v4 -> v5:
- fail immediatly if nested is wanted but not supported
When the guest invalidates one S1 entry, it passes the asid.
When propagating this invalidation downto the host, the asid
information also must be passed. So let's fill the arch_id field
introduced for that purpose.
Signed-off-by: Eric Auger
---
hw/arm/smmuv3.c | 1 +
1 file changed, 1
The SMMUv3 has the peculiarity to translate MSI
transactionss. let's advertise the corresponding
attribute.
Signed-off-by: Eric Auger
---
---
hw/arm/smmuv3.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 517755aed5..9372b15b34 100644
---
Whenever the eventfd is triggered, we retrieve the DMA fault(s)
from the mmapped fault region and inject them in the iommu
memory region.
Signed-off-by: Eric Auger
---
hw/vfio/pci.c | 50 ++
hw/vfio/pci.h | 1 +
2 files changed, 51 insertions(+)
TLB entries are usually tagged with some ids such as the asid
or pasid. When propagating an invalidation command from the
guest to the host, we need to pass this id.
Also we add a leaf field which indicates, in case of invalidation
notification whether only cache entries for the last level of
For VFIO integration we will need to pass the Context Descriptor (CD)
table GPA to the host. The CD table is also referred to as the PASID
table. Its GPA corresponds to the s1ctrptr field of the Stream Table
Entry. So let's decode and store it in the configuration structure.
Signed-off-by: Eric
Patchew URL: https://patchew.org/QEMU/20190711173131.6347-1-laur...@vivier.eu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v4] linux-user: fix to handle variably sized
SIOCGSTAMP with new kernels
We use the new extended IRQ VFIO_IRQ_TYPE_NESTED type and
VFIO_IRQ_SUBTYPE_DMA_FAULT subtype to set/unset
a notifier for physical DMA faults. The associated eventfd is
triggered, in nested mode, whenever a fault is detected at IOMMU
physical level.
The actual handler will be implemented in
In nested mode, legacy vfio_iommu_map_notify cannot be used as
there is no "caching" mode and we do not trap on map.
On Intel, vfio_iommu_map_notify was used to DMA map the RAM
through the host single stage.
With nested mode, we need to setup the stage 2 and the stage 1
separately. This patch
An IOVA/ASID invalidation is notified to all IOMMU Memory Regions
through smmuv3_inv_notifiers_iova/smmuv3_notify_iova.
When the notification occurs it is possible that some of the
PCIe devices associated to the notified regions do not have a
valid stream table entry. In that case we output a
As done for vfio regions, add helpers to retrieve irq info
including their optional capabilities.
Signed-off-by: Eric Auger
---
hw/vfio/common.c | 97 +++
hw/vfio/trace-events | 1 +
include/hw/vfio/vfio-common.h | 7 +++
3 files changed,
From: Andrew Jones
Signed-off-by: Andrew Jones
---
scripts/update-linux-headers.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index dfdfdfddcf..c97d485b08 100755
--- a/scripts/update-linux-headers.sh
+++
This new API allows to inject @count iommu_faults into
the IOMMU memory region.
Signed-off-by: Eric Auger
---
include/exec/memory.h | 25 +
memory.c | 10 ++
2 files changed, 35 insertions(+)
diff --git a/include/exec/memory.h
This header is meant to exposes data types used by
several IOMMU devices such as struct for SVA and
nested stage configuration.
Signed-off-by: Eric Auger
---
include/hw/iommu/iommu.h | 25 +
1 file changed, 25 insertions(+)
create mode 100644 include/hw/iommu/iommu.h
We introduce a new IOMMU Memory Region attribute, IOMMU_ATTR_MSI_TRANSLATE
which tells whether the virtual IOMMU translates MSIs. ARM SMMU
will expose this attribute since, as opposed to Intel DMAR, MSIs
are translated as any other DMA requests.
Signed-off-by: Eric Auger
---
From: Liu Yi L
This patch introduces PCIPASIDOps for IOMMU related operations.
https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg00078.html
https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg00940.html
So far, to setup virt-SVA for assigned SVA capable device, needs to
configure
Update the script to import the new iommu.h uapi header.
Signed-off-by: Eric Auger
---
scripts/update-linux-headers.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index f76d77363b..dfdfdfddcf 100755
---
This is an update against
https://github.com/eauger/linux/tree/v5.3.0-rc0-2stage-v9.
Signed-off-by: Eric Auger
---
include/standard-headers/asm-x86/bootparam.h | 2 +
include/standard-headers/linux/virtio_ids.h | 1 -
include/standard-headers/linux/virtio_pmem.h | 34 --
On 10/07/19 10:02, Wanpeng Li wrote:
> From: Wanpeng Li
>
> Adds PV_SCHED_YIELD CPUID feature bit.
>
> Cc: Eduardo Habkost
> Cc: Paolo Bonzini
> Cc: Radim Krčmář
> Signed-off-by: Wanpeng Li
> ---
> Note: kvm part is merged
> v1 -> v2:
> * use bit 13 instead of bit 12 since bit 12 has user
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