The size of the qcow2 L2 cache defaults to 32 MB, which can be easily
larger than the maximum amount of L2 metadata that the image can have.
For example: with 64 KB clusters the user would need a qcow2 image
with a virtual size of 256 GB in order to have 32 MB of L2 metadata.
Because of that, sinc
Erik Skultety writes:
> On Fri, Aug 16, 2019 at 08:10:20AM +0200, Markus Armbruster wrote:
>> Eduardo Habkost writes:
>>
>> > We have this issue reported when using libvirt to hotplug CPUs:
>> > https://bugzilla.redhat.com/show_bug.cgi?id=1741451
>> >
>> > Basically, libvirt is not copying die-i
Kevin Wolf writes:
> Am 15.08.2019 um 21:24 hat Markus Armbruster geschrieben:
[...]
>> Let's assume all libvirt ever does with deprecation notices is logging
>> them. Would that solve the problem of reliably alerting libvirt
>> developers to deprecation issues? Nope. But it could help
>> occa
On 8/16/19 1:23 PM, Philippe Mathieu-Daudé wrote:
> On 8/16/19 12:59 PM, Peter Maydell wrote:
>> On Tue, 13 Aug 2019 at 16:54, Markus Armbruster wrote:
>>>
>>> The following changes since commit 864ab314f1d924129d06ac7b571f105a2b76a4b2:
>>>
>>> Update version for v4.1.0-rc4 release (2019-08-06 1
Cc qemu-stable
This bug means that under certain conditions it's impossible to
create a cache large enough for the image, resulting in reduced I/O
performance.
On Fri, Aug 16, 2019 at 03:17:42PM +0300, Alberto Garcia wrote:
> The size of the qcow2 L2 cache defaults to 32 MB, which can be easily
>
Hi Alexander,
On Fri, Aug 09, 2019 at 10:33:59AM +0100, Stefan Hajnoczi wrote:
On Mon, Aug 05, 2019 at 07:11:10AM +, Oleinik, Alexander wrote:
Temporary solution until there is a better build solution for fuzzers in
tests/Makefile.include
Signed-off-by: Alexander Oleinik
---
target/i386/
The translation table walk for an ATS instruction can result in
various faults. In general these are just reported back via the
PAR_EL1 fault status fields, but in some cases the architecture
requires that the fault is turned into an exception:
* synchronous stage 2 faults of any kind during AT S
16.08.2019 15:33, Markus Armbruster wrote:
> Kevin Wolf writes:
>
>> Am 15.08.2019 um 21:24 hat Markus Armbruster geschrieben:
> [...]
>>> Let's assume all libvirt ever does with deprecation notices is logging
>>> them. Would that solve the problem of reliably alerting libvirt
>>> developers to
The translation table walk for an ATS instruction can result in
various faults. In general these are just reported back via the
PAR_EL1 fault status fields, but in some cases the architecture
requires that the fault is turned into an exception:
* synchronous stage 2 faults of any kind during AT S
On Tue, 25 Jun 2019 at 12:28, Jonathan Cameron
wrote:
>
> CCIX topologies are 'layered' on top of PCIe tree topologies.
> This is done primarily by allowing a single CCIX device to appear as
> multiple disjoint nodes in the PCIe tree.
> This patch is being distributed by the CCIX Consortium, Inc.
Currently the only part of an ARMCPRegInfo which is allowed to cause
a CPU exception is the access function, which returns a value indicating
that some flavour of UNDEF should be generated.
For the ATS system instructions, we would like to conditionally
generate exceptions as part of the writefn,
On Thu, 15 Aug 2019 at 17:36, Dr. David Alan Gilbert (git)
wrote:
>
> From: "Dr. David Alan Gilbert"
>
> The following changes since commit f28ed74fd116491e31329044d140fde4aa23b2a0:
>
> Update version for v4.1.0-rc5 release (2019-08-13 15:38:38 +0100)
>
> are available in the Git repository at:
sysemu/sysemu.h is a rather unfocused dumping ground for stuff related
to the system-emulator. Evidence:
* It's included widely: in my "build everything" tree, changing
sysemu/sysemu.h still triggers a recompile of some 1100 out of 6600
objects (not counting tests and objects that don't depen
The following changes since commit f8f2eac4e5de8ce8ef17591ee1b84904437be25b:
Open 4.2 development tree (2019-08-15 17:20:55 +0100)
are available in the Git repository at:
git://repo.or.cz/qemu/armbru.git tags/pull-include-2019-08-13-v2
for you to fetch changes up to 54d31236b906c8f03eb01171
Am 16.08.2019 um 14:17 hat Alberto Garcia geschrieben:
> The size of the qcow2 L2 cache defaults to 32 MB, which can be easily
> larger than the maximum amount of L2 metadata that the image can have.
> For example: with 64 KB clusters the user would need a qcow2 image
> with a virtual size of 256 G
Currently when QEMU is given a bios image with only a file name and
its file path passed in "-L", it still reports file not found.
This series fixes the issue. This is especially helpful for creating
distro QEMU packages.
Bin Meng (2):
riscv: Add a helper routine for finding firmware
riscv:
This adds a helper routine for finding firmware. It is currently
used only for "-bios default" case.
Signed-off-by: Bin Meng
---
hw/riscv/boot.c | 22 +++---
include/hw/riscv/boot.h | 1 +
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/boot.c b
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng
---
hw/riscv/boot.c | 6 +++---
1 file changed, 3 insertions(+), 3 de
From: Richard Henderson
This function is used in two different contexts, and it will be
clearer if the function is given the address to which it applies.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190807045335.1361-2-richard.h
From: Aaron Hill
This commit properly sets the ENET_BD_BDU flag once the emulated FEC controller
has finished processing the last descriptor. This is done for both transmit
and receive descriptors.
This allows the QNX 7.0.0 BSP for the Sabrelite board (which can be
found at http://blackberry.qnx
From: Alex Bennée
While most features are now detected by probing the ID_* registers
kernels can (and do) use MIDR_EL1 for working out of they have to
apply errata. This can trip up warnings in the kernel as it tries to
work out if it should apply workarounds to features that don't
actually exist
:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20190816
for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b:
target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word (2019-08-16
14:0
Factor out code to 'generate a singlestep exception', which is
currently repeated in four places.
To do this we need to also pull the identical copies of the
gen-exception() function out of translate-a64.c and translate.c
into translate.h.
(There is a bug in the code: we're taking the exception t
From: Richard Henderson
Replace x = double_saturate(y) with x = add_saturate(y, y).
There is no need for a separate more specialized helper.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190807045335.1361-12-richard.hender...@lin
From: Richard Henderson
We currently have 3 different ways of computing the architectural
value of "PC" as seen in the ARM ARM.
The value of s->pc has been incremented past the current insn,
but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
for t16, PC = s->pc + 2. These diff
When generating an architectural single-step exception we were
routing it to the "default exception level", which is to say
the same exception level we execute at except that EL0 exceptions
go to EL1. This is incorrect because the debug exception level
can be configured by the guest for situations
From: Richard Henderson
The offset is variable depending on the instruction set, whereas
we have stored values for the current pc and the next pc. Passing
in the actual value is clearer in intent.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
From: Damien Hedde
Replace the zynq_slcr registers enum and macros using the
hw/registerfields.h macros.
Signed-off-by: Damien Hedde
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 20190729145654.14644-30-damien.he...@greensocs.com
Signed-off-by: Peter Maydell
-
From: Andrew Jones
The current implementation of ZCR_ELx matches the architecture, only
implementing the lower four bits, with the rest RAZ/WI. This puts
a strict limit on ARM_MAX_VQ of 16. Make sure we don't let ARM_MAX_VQ
grow without a corresponding update here.
Suggested-by: Dave Martin
Sig
From: Richard Henderson
Add a new field to retain the address of the instruction currently
being translated. The 32-bit uses are all within subroutines used
by a32 and t32. This will become less obvious when t16 support is
merged with a32+t32, and having a clear definition will help.
Convert a
From: Andrew Jones
If -cpu ,aarch64=off is used then KVM must also be used, and it
and the host must support running the vcpu in 32-bit mode. Also, if
-cpu ,aarch64=on is used, then it doesn't matter if kvm is
enabled or not.
Signed-off-by: Andrew Jones
Reviewed-by: Eric Auger
Signed-off-by: P
From: Andrew Jones
We first convert the pmu property from a static property to one with
its own accessors. Then we use the set accessor to check if the PMU is
supported when using KVM. Indeed a 32-bit KVM host does not support
the PMU, so this check will catch an attempt to use it at property-set
From: Richard Henderson
Unlike the other more generic gen_exception{,_internal}_insn
interfaces, breakpoints always refer to the current instruction.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190807045335.1361-10-richard.hend
From: Richard Henderson
The thumb bit has already been removed from s->pc, and is always even.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190807045335.1361-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
targ
From: Andrew Jones
Unless we're guaranteed to always increase ARM_MAX_VQ by a multiple of
four, then we should use DIV_ROUND_UP to ensure we get an appropriate
array size.
Signed-off-by: Andrew Jones
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 2 +-
1 f
From: Richard Henderson
Use deposit as the composit operation to merge the
bits from the two inputs.
Signed-off-by: Richard Henderson
Message-id: 20190808202616.13782-3-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 26 ++
From: Richard Henderson
Promote this function from aarch64 to fully general use.
Use it to unify the code sequences for generating illegal
opcode exceptions.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190807045335.1361-11-rich
From: Richard Henderson
Provide a common routine for the places that require ALIGN(PC, 4)
as the base address as opposed to plain PC. The two are always
the same for A32, but the difference is meaningful for thumb mode.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by:
From: Andrew Jones
A couple return -EINVAL's forgot their '-'s.
Signed-off-by: Andrew Jones
Reviewed-by: Eric Auger
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target/arm/kvm64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b
From: Richard Henderson
Extract is a compact combination of shift + and.
Signed-off-by: Richard Henderson
Message-id: 20190808202616.13782-2-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 9 +
1 file changed, 1 insert
From: Richard Henderson
Rotate is the more compact and obvious way to swap 16-bit
elements of a 32-bit word.
Signed-off-by: Richard Henderson
Message-id: 20190808202616.13782-6-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 6
From: Richard Henderson
The offset is variable depending on the instruction set.
Passing in the actual value is clearer in intent.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190807045335.1361-9-richard.hender...@linaro.org
Sig
From: Richard Henderson
The immediate shift generator functions already test for,
and eliminate, the case of a shift by zero.
Signed-off-by: Richard Henderson
Message-id: 20190808202616.13782-4-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/ar
Philippe Mathieu-Daudé writes:
> On 8/16/19 1:23 PM, Philippe Mathieu-Daudé wrote:
>> On 8/16/19 12:59 PM, Peter Maydell wrote:
>>> On Tue, 13 Aug 2019 at 16:54, Markus Armbruster wrote:
The following changes since commit
864ab314f1d924129d06ac7b571f105a2b76a4b2:
Upda
From: Richard Henderson
The helper function is more documentary, and also already
handles the case of rotate by zero.
Signed-off-by: Richard Henderson
Message-id: 20190808202616.13782-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/transl
From: Richard Henderson
We must update s->base.pc_next when we return from the translate_insn
hook to the main translator loop. By incrementing s->base.pc_next
immediately after reading the insn word, "pc_next" contains the address
of the next instruction throughout translation.
All remaining u
On 16.08.19 13:01, Vladimir Sementsov-Ogievskiy wrote:
> 15.08.2019 20:01, Max Reitz wrote:
>> On 15.08.19 17:21, Vladimir Sementsov-Ogievskiy wrote:
>>> 09.08.2019 19:14, Max Reitz wrote:
Currently, check_to_replace_node() only allows mirror to replace a node
in the chain of the source n
From: Richard Henderson
All of the inputs to these instructions are 32-bits. Rather than
extend each input to 64-bits and then extract the high 32-bits of
the output, use tcg_gen_muls2_i32 and other 32-bit generator functions.
Signed-off-by: Richard Henderson
Message-id: 20190808202616.13782-7
From: Andrew Jones
Move the getting/putting of the fpsimd registers out of
kvm_arch_get/put_registers() into their own helper functions
to prepare for alternatively getting/putting SVE registers.
No functional change.
Signed-off-by: Andrew Jones
Reviewed-by: Eric Auger
Reviewed-by: Richard He
From: Richard Henderson
Separate shift + extract low will result in one extra insn
for hosts like RISC-V, MIPS, and Sparc.
Signed-off-by: Richard Henderson
Message-id: 20190808202616.13782-8-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/t
To be sure, you can also run my original C test code from
2010. If that produces a bit-identtical result, then this
has indeed been fixed. If there are deviations in the last
digits, then the fingerprinting issues is still there, but
at least Python has stopped complaining.
Regards,
Arno
On Fri,
On Thu, 15 Aug 2019 15:38:03 -0300
Eduardo Habkost wrote:
> We have this issue reported when using libvirt to hotplug CPUs:
> https://bugzilla.redhat.com/show_bug.cgi?id=1741451
>
> Basically, libvirt is not copying die-id from
> query-hotpluggable-cpus, but die-id is now mandatory.
this should
On Fri 16 Aug 2019 02:59:21 PM CEST, Kevin Wolf wrote:
> The requirement so that this bug doesn't affect the user seems to be
> that the image size is a multiple of 64k * 8k = 512 MB. Which means
> that users are probably often lucky enough in practice.
Or rather: cluster_size^2 / 8, which, if my
On Fri, Aug 16, 2019 at 09:04:16AM +0800, Like Xu wrote:
> Hi,
>
> On 2019/8/16 2:38, Eduardo Habkost wrote:
> > The error message for die-id range validation is incorrect. Example:
> >
> >$ qemu-system-x86_64 -smp 1,sockets=6,maxcpus=6 \
> > -device qemu64-x86_64-cpu,socket-id=1,die-id
On Thu, 15 Aug 2019 at 18:59, Thomas Huth wrote:
>
> Hi Peter,
>
> the following changes since commit 9e06029aea3b2eca1d5261352e695edc1e7d7b8b:
>
> Update version for v4.1.0 release (2019-08-15 13:03:37 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/huth/qemu.git ta
On Fri, Aug 16, 2019 at 5:44 AM Alistair Francis
wrote:
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Jonathan Behrens
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Chih-Min Chao
> ---
> hw/riscv/sifive_plic.c | 12
> include/hw/riscv/sifive_plic.h | 3 ---
>
On Fri, Aug 16, 2019 at 5:41 AM Alistair Francis
wrote:
>
> Setting write permission on dirty PTEs results in userspace inside a
> Hypervisor guest (VU) becoming corrupted. This appears to be because it
> ends up with write permission in the second stage translation in cases
> where we aren't doin
On Fri, Aug 16, 2019 at 5:44 AM Alistair Francis
wrote:
>
> The mip register is an MXLEN-bit long register. Convert it to a
> target_ulong type instead of uint32_t.
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-
On Fri, Aug 16, 2019 at 5:42 AM Alistair Francis
wrote:
>
> Let's create a function that tests if floating point support is
> enabled. We can then protect all floating point operations based on if
> they are enabled.
>
> This patch so far doesn't change anything, it's just preparing for the
> Hype
On Thu, 15 Aug 2019 15:38:01 -0300
Eduardo Habkost wrote:
> The error message for die-id range validation is incorrect. Example:
>
> $ qemu-system-x86_64 -smp 1,sockets=6,maxcpus=6 \
> -device qemu64-x86_64-cpu,socket-id=1,die-id=1,core-id=0,thread-id=0
> qemu-system-x86_64: -device
>
On Thu, 15 Aug 2019 15:38:02 -0300
Eduardo Habkost wrote:
> The error message when die-id is omitted doesn't make sense:
>
> $ qemu-system-x86_64 -smp 1,sockets=6,maxcpus=6 \
> -device qemu64-x86_64-cpu,socket-id=1,core-id=0,thread-id=0
> qemu-system-x86_64: -device
> qemu64-x86_64-cpu,
On Fri, Aug 16, 2019 at 5:41 AM Alistair Francis
wrote:
>
> Update the Hypervisor CSR addresses to match the v0.4 spec.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Chih-Min Chao
> ---
> target/riscv/cpu_bits.h | 35 ++-
> 1 file changed, 18 insertions(+),
Am 16.08.2019 um 15:30 hat Alberto Garcia geschrieben:
> On Fri 16 Aug 2019 02:59:21 PM CEST, Kevin Wolf wrote:
> > The requirement so that this bug doesn't affect the user seems to be
> > that the image size is a multiple of 64k * 8k = 512 MB. Which means
> > that users are probably often lucky en
On Fri, Aug 16, 2019 at 5:48 AM Alistair Francis
wrote:
>
> From: Atish Patra
>
> Use both the generic register name and ABI name for the general purpose
> registers and floating point registers.
>
> Signed-off-by: Atish Patra
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.c | 19 +
On Fri, Aug 16, 2019 at 5:38 AM Alistair Francis
wrote:
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
Looking at our code we're still implementing the x87 insns FSIN, FCOS,
FSINCOS, FPTAN, FPATAN, F2XM1, FYL2X, FYL2XP1 by "convert the floatx80
to a host double and use the host C library functions", so I think this
bug is still unfixed. If the C program in comment 1 and/or the Python
code has stoppe
16.08.2019 16:30, Max Reitz wrote:
> On 16.08.19 13:01, Vladimir Sementsov-Ogievskiy wrote:
>> 15.08.2019 20:01, Max Reitz wrote:
>>> On 15.08.19 17:21, Vladimir Sementsov-Ogievskiy wrote:
09.08.2019 19:14, Max Reitz wrote:
> Currently, check_to_replace_node() only allows mirror to replace
On Fri 16 Aug 2019 04:08:19 PM CEST, Kevin Wolf wrote:
>> And yes, the odd value on the 512KB row on that we discussed last month
>> is due to this same bug:
>>
>> https://lists.gnu.org/archive/html/qemu-block/2019-07/msg00496.html
>
> Hm... And suddently it makes sense. :-)
>
> So I assume all of
From: "Dr. David Alan Gilbert"
The virtio-fs virtio device provides shared file system access using
the FUSE protocol carried ovew virtio.
The actual file server is implemented in an external vhost-user-fs device
backend process.
Signed-off-by: Stefan Hajnoczi
Signed-off-by: Sebastien Boeuf
Si
From: "Dr. David Alan Gilbert"
Hi,
This pair of patches adds the core of the virtio-fs support to qemu;
it's marked experimental since the kernel patch and spec changes aren't
in yet; but they're bubbling along.
While the spec change is still in progress; the ID number is already
reserved.
From: "Dr. David Alan Gilbert"
Add the PCI version of vhost-user-fs.
Launch QEMU like this:
qemu -chardev socket,path=/tmp/vhost-fs.sock,id=chr0
-device x-vhost-user-fs-pci,tag=myfs,chardev=chr0
Signed-off-by: Stefan Hajnoczi
Signed-off-by: Sebastien Boeuf
Signed-off-by: Dr. David A
On Wed, 14 Aug 2019 10:24:03 +0800
Tao Xu wrote:
> On 8/13/2019 11:00 PM, Igor Mammedov wrote:
> > On Fri, 9 Aug 2019 14:57:25 +0800
> > Tao wrote:
> >
> >> From: Tao Xu
> >>
> >> In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
> >> The initiator represents processor
On Fri, 16 Aug 2019 at 14:08, Markus Armbruster wrote:
>
> The following changes since commit f8f2eac4e5de8ce8ef17591ee1b84904437be25b:
>
> Open 4.2 development tree (2019-08-15 17:20:55 +0100)
>
> are available in the Git repository at:
>
> git://repo.or.cz/qemu/armbru.git tags/pull-include-2
On Wed, 14 Aug 2019 19:31:27 -0700
Dan Williams wrote:
> On Wed, Aug 14, 2019 at 6:57 PM Tao Xu wrote:
> >
> > On 8/15/2019 5:29 AM, Dan Williams wrote:
> > > On Tue, Aug 13, 2019 at 10:14 PM Tao Xu wrote:
> > >>
> > >> On 8/14/2019 10:39 AM, Dan Williams wrote:
> > >>> On Tue, Aug 13, 20
Further patch will run partial requests of iterations of
qcow2_co_preadv in parallel for performance reasons. To prepare for
this, separate part which may be parallelized into separate function
(qcow2_co_preadv_task).
While being here, also separate encrypted clusters reading to own
function, like
Common interface for aio task loops. To be used for improving
performance of synchronous io loops in qcow2, block-stream,
copy-on-read, and may be other places.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
---
include/block/aio_task.h | 54 +
block/aio_tas
Similarly to previous commit, prepare for parallelizing write-loop
iterations.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
---
block/qcow2.c | 153 +-
1 file changed, 89 insertions(+), 64 deletions(-)
diff --git a/block/qco
It improves performance for fragmented qcow2 images. It also affect 026
iotest, increasing leaked clusters number, which is not surprising when
we run several sub-requests of qcow2 request in parallel.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.h | 3 +
bl
Hi all!
Here is an asynchronous scheme for handling fragmented qcow2
reads and writes. Both qcow2 read and write functions loops through
sequential portions of data. The series aim it to parallelize these
loops iterations.
It improves performance for fragmented qcow2 images, I've tested it
as desc
qemu-io now prefixes its error and warnings with "qemu-io:".
36b9986b08787019e fixed a lot of iotests output but forget about
026.out.nocache. Fix it too.
Fixes: 99e98d7c9fc1a1639fad ("qemu-io: Use error_[gs]et_progname()")
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/026.o
On Thu, 15 Aug 2019 at 19:34, Eric Blake wrote:
>
> The following changes since commit 9e06029aea3b2eca1d5261352e695edc1e7d7b8b:
>
> Update version for v4.1.0 release (2019-08-15 13:03:37 +0100)
>
> are available in the Git repository at:
>
> https://repo.or.cz/qemu/ericb.git tags/pull-nbd-201
On 16/08/2019 09:32, Rashmica Gupta wrote:
> The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
> addtional two sets of 1.8V gpios.
>
> Signed-off-by: Rashmica Gupta
One minor comment below, but this is minor.
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> hw/gpio/aspeed_
On 16/08/2019 09:32, Rashmica Gupta wrote:
> GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC.
> (Note that the ast2400 controller only goes up to group AB).
> A set has four groups (except set AC which only has one) and is
> referred to by the groups it is composed of (eg ABC
On 16/08/2019 09:32, Rashmica Gupta wrote:
> Signed-off-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 3 +++
> hw/arm/aspeed_soc.c | 17 +
> 2 files changed, 20 insertions(+)
>
> diff --git a/include/hw/arm/aspee
On 16/08/2019 09:40, Rashmica Gupta wrote:
> Cédric, this is how I thought changes to the SOC for your aspeed-4.1
> branch would look
Some comments,
> From 13a07834476fa266c352d9a075b341c483b2edf9 Mon Sep 17 00:00:00 2001
> From: Rashmica Gupta
> Date: Fri, 16 Aug 2019 15:18:22 +1000
> Subjec
09.08.2019 19:14, Max Reitz wrote:
> Parts of the block layer treat BDS.backing_file as if it were whatever
> the image header says (i.e., if it is a relative path, it is relative to
> the overlay), other parts treat it like a cache for
> bs->backing->bs->filename (relative paths are relative to th
On 16/08/2019 09:32, Rashmica Gupta wrote:
> v5:
> - integrated AspeedGPIOController fields into AspeedGPIOClass
> - separated ast2600_3_6v and ast2600_1_8v into two classes
Rashmica,
This looks much nicer !
Please take a look at branch aspeed-4.2 in which I have merged your
v5 and modified sl
On Fri, 16 Aug 2019 at 10:36, Kevin Wolf wrote:
>
> The following changes since commit 9e06029aea3b2eca1d5261352e695edc1e7d7b8b:
>
> Update version for v4.1.0 release (2019-08-15 13:03:37 +0100)
>
> are available in the Git repository at:
>
> git://repo.or.cz/qemu/kevin.git tags/for-upstream
>
15.08.2019 18:39, Vladimir Sementsov-Ogievskiy wrote:
> 15.08.2019 17:09, Max Reitz wrote:
>> On 15.08.19 14:10, Vladimir Sementsov-Ogievskiy wrote:
>>> Hi all!
>>>
>>> Here is an asynchronous scheme for handling fragmented qcow2
>>> reads and writes. Both qcow2 read and write functions loops throu
On Fri, Aug 16, 2019 at 08:10:20AM +0200, Markus Armbruster wrote:
> Eduardo Habkost writes:
>
> > We have this issue reported when using libvirt to hotplug CPUs:
> > https://bugzilla.redhat.com/show_bug.cgi?id=1741451
> >
> > Basically, libvirt is not copying die-id from
> > query-hotpluggable-c
On Fri, Aug 16, 2019 at 03:20:11PM +0200, Igor Mammedov wrote:
> On Thu, 15 Aug 2019 15:38:03 -0300
> Eduardo Habkost wrote:
>
> > We have this issue reported when using libvirt to hotplug CPUs:
> > https://bugzilla.redhat.com/show_bug.cgi?id=1741451
> >
> > Basically, libvirt is not copying die
Fine by me. I suggest to keep tracking this though, if necessary
in another bug item.
Regards,
Arno
On Fri, Aug 16, 2019 at 16:06:29 CEST, Peter Maydell wrote:
> Looking at our code we're still implementing the x87 insns FSIN, FCOS,
> FSINCOS, FPTAN, FPATAN, F2XM1, FYL2X, FYL2XP1 by "convert the
20190814a' into staging (2019-08-16
> 12:00:18 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20190816
>
> for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b:
>
In job_finish_sync job_enter should be enough for a job to make some
progress and draining is a wrong tool for it. So use job_enter directly
here and drop job_drain with all related staff not used more.
Suggested-by: Kevin Wolf
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
It's a continuation
We have this issue reported when using libvirt to hotplug CPUs:
https://bugzilla.redhat.com/show_bug.cgi?id=1741451
Basically, libvirt is not copying die-id from
query-hotpluggable-cpus, but die-id is now mandatory.
We could blame libvirt and say it is not following the documented
interface, beca
16.08.2019 20:04, Vladimir Sementsov-Ogievskiy wrote:
> In job_finish_sync job_enter should be enough for a job to make some
> progress and draining is a wrong tool for it. So use job_enter directly
> here and drop job_drain with all related staff not used more.
>
> Suggested-by: Kevin Wolf
> Sig
16.08.2019 20:10, Vladimir Sementsov-Ogievskiy wrote:
> 16.08.2019 20:04, Vladimir Sementsov-Ogievskiy wrote:
>> In job_finish_sync job_enter should be enough for a job to make some
>> progress and draining is a wrong tool for it. So use job_enter directly
>> here and drop job_drain with all relate
When 'system_reset' is called, the main loop clear the memory
region cache before the BH has a chance to execute. Later when
the deferred function is called, some assumptions that were
made when scheduling them are no longer true when they actually
execute.
This is what happens using a virtio-blk
On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei wrote:
>
> Hi, Palmer
>
> When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the
> mail list, "the CLIC interrupt controller is under testing,
> and will be included in QEMU 3.1 or 3.2". It is pity that the CLIC is not in
> included ev
On Fri, Aug 16, 2019 at 02:22:58PM +0200, Markus Armbruster wrote:
> Erik Skultety writes:
>
> > On Fri, Aug 16, 2019 at 08:10:20AM +0200, Markus Armbruster wrote:
> >> Eduardo Habkost writes:
> >>
> >> > We have this issue reported when using libvirt to hotplug CPUs:
> >> > https://bugzilla.red
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