Traditional PCI INTx for vfio devices can only perform well if using
an in-kernel irqchip. Therefore, vfio_intx_update() issues a warning
if an in kernel irqchip is not available.
We usually do have an in-kernel irqchip available for pseries machines
on POWER hosts. However, because the
pseries machine type can have one of two different interrupt controllers in
use depending on feature negotiation with the guest. Usually this is
invisible to devices, because they route to a common set of qemu_irqs which
in turn dispatch to the correct back end.
VFIO passthrough devices,
Awareness of an in kernel irqchip is usually local to the machine and its
top-level interrupt controller. However, in a few cases other things need
to know about it. In particular vfio devices need this in order to
accelerate interrupt delivery.
If interrupt routing is changed, such devices may
This splits the vfio_intx_update() function into one part doing the actual
reconnection with the KVM irqchip (vfio_intx_update(), now taking an
argument with the new routing) and vfio_intx_routing_notifier() which
handles calls to the pci device intx routing notifier and calling
vfio_intx_update()
VFIO PCI devices already respond to the pci intx routing notifier, in order
to update kernel irqchip mappings when routing is updated. However this
won't handle the case where the irqchip itself is replaced by a different
model while retaining the same routing. This case can happen on
the
The pseries machine type has the odd property that it's root irq chip
can be completely changed at runtime. This comes about because PAPR
feature negotiation lets the guest choose between the old XICS style
or new XIVE style PIC. It's possible, because both PICs are
paravirtualized via
Patchew URL:
https://patchew.org/QEMU/20191017044232.27601-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/4] target/arm vector improvements
Type: series
Message-id:
On 10/16/19 5:46 PM, Wei Yang wrote:
> Signed-off-by: Wei Yang
> CC: Richard Henderson
> CC: Stefan Hajnoczi
>
> ---
> v2: add "\b" for better match, suggested by Richard Henderson
>
> ---
> scripts/checkpatch.pl | 6 ++
> 1 file changed, 6 insertions(+)
Reviewed-by: Richard Henderson
We still need two different helpers, since NEON and SVE2 get the
inputs from different locations within the source vector. However,
we can convert both to the same internal form for computation.
The sve2 helper is not used yet, but adding it with this patch
helps illustrate why the neon changes
These instructions shift left or right depending on the sign
of the input, and 7 bits are significant to the shift. This
requires several masks and selects in addition to the actual
shifts to form the complete answer.
That said, the operation is still a small improvement even for
two 64-bit
The gvec form will be needed for implementing SVE2.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 4 +---
target/arm/neon_helper.c | 30 --
target/arm/translate-a64.c | 28 +++-
target/arm/translate.c | 16
The gvec form will be needed for implementing SVE2.
Extend the implementation to operate on uint64_t instead of uint32_t.
Use a counted inner loop instead of terminating when op1 goes to zero,
looking toward the required implementation for ARMv8.4-DIT.
Signed-off-by: Richard Henderson
---
The first patch has been seen before.
https://patchwork.ozlabs.org/patch/1115039/
It had a bug and I didn't fix it right away and then forgot.
Fixed now; I had mixed up the operand ordering for aarch32.
The next 3 are something that I noticed while doing other stuff.
In particular, pmull is
Patchew URL:
https://patchew.org/QEMU/20191017004633.13229-1-richardw.y...@linux.intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Patch v2] checkpatch: sugguest to use qemu_real_host_page_size
instead of getpagesize() or
On Wed, Oct 16, 2019 at 06:04:04PM +0200, Greg Kurz wrote:
> On Wed, 9 Oct 2019 17:07:59 +1100
> David Gibson wrote:
>
> > This is a substantial rework to clean up the handling of IRQs in
> > spapr. It includes some cleanups to both the XICS and XIVE interrupt
> > controller backends, as well
Signed-off-by: Wei Yang
CC: Richard Henderson
CC: Stefan Hajnoczi
---
v2: add "\b" for better match, suggested by Richard Henderson
---
scripts/checkpatch.pl | 6 ++
1 file changed, 6 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index aa9a354a0e..ab68a16fd2
On Wed, Oct 16, 2019 at 07:48:50PM +0100, Stefan Hajnoczi wrote:
>On Wed, Oct 16, 2019 at 09:24:32AM +0800, Wei Yang wrote:
>> Signed-off-by: Wei Yang
>> CC: David Gibson
>> ---
>> scripts/checkpatch.pl | 6 ++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/scripts/checkpatch.pl
On Wed, Oct 16, 2019 at 08:43:32AM -0700, Richard Henderson wrote:
>On 10/15/19 6:24 PM, Wei Yang wrote:
>> if ($line =~ /\bbzero\(/) {
>> ERROR("use memset() instead of bzero()\n" . $herecurr);
>> }
>> +if ($line =~ /getpagesize\(\)/) {
On Wed, 16 Oct 2019 22:18:47 +0200
Jens Freimann wrote:
> On Tue, Oct 15, 2019 at 07:52:12PM -0600, Alex Williamson wrote:
> >On Fri, 11 Oct 2019 13:20:15 +0200
> >Jens Freimann wrote:
> >
> >> As usual block all vfio-pci devices from being migrated, but make an
> >> exception for failover
On Sun, Oct 13, 2019 at 11:51 PM Sai Pavan Boddu
wrote:
>
> ZynqMP/Versal specific qspi registers should be handled inside
> zynqmp_qspi_read/write calls. When few of these transactions are handled by
> spi hooks we see state change in spi bus unexpectedly.
>
> Signed-off-by: Sai Pavan Boddu
>
On 10/16/19 6:42 PM, Eduardo Habkost wrote:
> Python 3.5 is the oldest Python version available on our
> supported build platforms, and Python 2 end of life will be 3
> weeks after the planned release date of QEMU 4.2.0. Drop Python
> 2 support from configure completely, and require Python 3.5
Python 3.5 is the oldest Python version available on our
supported build platforms, and Python 2 end of life will be 3
weeks after the planned release date of QEMU 4.2.0. Drop Python
2 support from configure completely, and require Python 3.5 or
newer.
Signed-off-by: Eduardo Habkost
---
On Wed, Oct 16, 2019 at 08:11:57AM +0200, Thomas Huth wrote:
> On 16/10/2019 05.00, Eduardo Habkost wrote:
> > On Tue, Sep 17, 2019 at 08:31:40PM -0300, Eduardo Habkost wrote:
> >> On Mon, Jul 01, 2019 at 07:25:27PM -0300, Eduardo Habkost wrote:
> >>> On Mon, Jun 10, 2019 at 01:58:50PM +0100,
On 10/9/19 3:41 AM, Vladimir Sementsov-Ogievskiy wrote:
Implement reconnect. To achieve this:
1. add new modes:
connecting-wait: means, that reconnecting is in progress, and there
were small number of reconnect attempts, so all requests are
waiting for the connection.
Signed-off-by: Andrew Kelley
---
linux-user/aarch64/syscall_nr.h | 13 ++
linux-user/arm/syscall_nr.h | 38
linux-user/i386/syscall_nr.h| 43
linux-user/mips/cpu_loop.c | 6 +
linux-user/ppc/syscall_nr.h
On Mon, Oct 14, 2019 at 7:50 PM Peter Xu wrote:
>
> On Mon, Oct 14, 2019 at 01:28:49PM -0700, Jintack Lim wrote:
> > Hi,
>
> Hello, Jintack,
>
Hi Peter,
> >
> > I'm trying to pass through a physical network device to a nested VM
> > using virtual IOMMU. While I was able to do it successfully
On Wed, Oct 16, 2019 at 12:02 PM Palmer Dabbelt wrote:
>
> On Mon, 07 Oct 2019 11:05:33 PDT (-0700), alistai...@gmail.com wrote:
> > On Thu, Oct 3, 2019 at 8:53 AM Palmer Dabbelt wrote:
> >>
> >> On Fri, 23 Aug 2019 16:38:47 PDT (-0700), Alistair Francis wrote:
> >> > Signed-off-by: Alistair
On Tue, Oct 8, 2019 at 11:36 AM Palmer Dabbelt wrote:
>
> On Fri, 23 Aug 2019 16:39:00 PDT (-0700), Alistair Francis wrote:
> > Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
> > MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
> >
> > Signed-off-by: Alistair Francis
On Wed, Oct 2, 2019 at 4:52 PM Palmer Dabbelt wrote:
>
> On Fri, 23 Aug 2019 16:38:44 PDT (-0700), Alistair Francis wrote:
> > Respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when performing
> > floating point operations when V=0.
>
> I'm confused as to what this has to do with floating
On Tue, Sep 10, 2019 at 7:48 AM Palmer Dabbelt wrote:
>
> On Fri, 23 Aug 2019 16:38:00 PDT (-0700), Alistair Francis wrote:
> > Update the CSR permission checking to work correctly when we are in
> > HS-mode.
> >
> > Signed-off-by: Alistair Francis
> > ---
> > target/riscv/csr.c | 10 --
Philippe Mathieu-Daudé writes:
> Hi Sergio,
>
> On 10/15/19 1:23 PM, Sergio Lopez wrote:
>> Follow checkpatch.pl recommendation and replace the use of strtol with
>> qemu_strtol in x86_load_linux().
>
> "with qemu_strtoui"
>
>>
>> Signed-off-by: Sergio Lopez
>> ---
>> hw/i386/pc.c | 9
On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
Tested-by: Jae Hyun Yoo
Thanks for the implementation!
-Jae
On Tue, Oct 15, 2019 at 07:52:12PM -0600, Alex Williamson wrote:
On Fri, 11 Oct 2019 13:20:15 +0200
Jens Freimann wrote:
As usual block all vfio-pci devices from being migrated, but make an
exception for failover primary devices. This is achieved by setting
unmigratable to 0 but also add a
On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.
A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length
On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.
Signed-off-by: Cédric Le Goater
Tested-by: Jae Hyun Yoo
On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
The Aspeed I2C controller can operate in different transfer modes :
- Byte Buffer mode, using a dedicated register to transfer a
byte. This is what the model supports today.
- Pool Buffer mode, using an internal SRAM to transfer
On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
Currently, we link the DRAM memory region to the FMC model (for DMAs)
through a property alias at the SoC level. The I2C model will need a
similar region for DMA support, add a DRAM region property at the SoC
level for both model to use.
Patchew URL: https://patchew.org/QEMU/20191016164145.115898-1-sam...@google.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v8 0/8] Add Qemu to SeaBIOS LCHS interface
Type: series
Message-id:
Hi
On Wed, Oct 16, 2019 at 12:24 PM Sergio Lopez wrote:
>
> microvm is a machine type inspired by Firecracker and constructed
> after its machine model.
>
> It's a minimalist machine type without PCI nor ACPI support, designed
> for short-lived guests. microvm also establishes a baseline for
>
Callers of create_image() will pass strings as arguments, but the
Image class will expect bytes objects to be provided. Encode
them inside create_image().
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/layout.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Field values are supposed to be bytes objects, not unicode
strings. Change two constants that were declared as strings.
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/layout.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
No caller of fuzzer functions is interested in unicode string values,
so replace them with bytes sequences.
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/fuzz.py | 42
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git
This makes the formatting code simpler, and safer if we change
the type of self.value from str to bytes.
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/layout.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/image-fuzzer/qcow2/layout.py
StringIO.StringIO is not available on Python 3, but io.StringIO
is available on both Python 2 and 3. io.StringIO is slightly
different from the Python 2 StringIO module, though, so we need
bytes coming from subprocess.Popen() to be explicitly decoded.
Signed-off-by: Eduardo Habkost
---
image-fuzzer is now supposed to be ready to run using Python 3.
Remove the __future__ imports and change the interpreter line to
"#!/usr/bin/env python3".
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/__init__.py | 1 -
tests/image-fuzzer/qcow2/layout.py | 1 -
Instead of manually encoding stderr and stdout output, use
`errors` parameter of subprocess.Popen(). This will make
process.communicate() return unicode strings instead of bytes
objects.
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/runner.py | 11 ---
1 file changed, 4
Most of the division expressions in image-fuzzer assume integer
division. Use the // operator to keep the same behavior when we
move to Python 3.
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/fuzz.py | 12 -
tests/image-fuzzer/qcow2/layout.py | 40
This probably never caused problems because on Linux there's no
actual newline conversion happening, but on Python 3 the
binary/text distinction is stronger and we must explicitly open
the image file in binary mode.
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/layout.py | 2 +-
1
This is necessary for Python 3 compatibility.
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/qcow2/layout.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/image-fuzzer/qcow2/layout.py
b/tests/image-fuzzer/qcow2/layout.py
index c57418fa15..fe273d4143 100644
This series ports image-fuzzer to Python 3.
Eduardo Habkost (10):
image-fuzzer: Open image files in binary mode
image-fuzzer: Write bytes instead of string to image file
image-fuzzer: Explicitly use integer division operator
image-fuzzer: Use io.StringIO
image-fuzzer: Use %r for all
Patchew URL:
https://patchew.org/QEMU/157124-882302-1-git-send-email-andrey.shinkev...@virtuozzo.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Patchew URL:
https://patchew.org/QEMU/157124-882302-1-git-send-email-andrey.shinkev...@virtuozzo.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
On Mon, 07 Oct 2019 11:05:33 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Oct 3, 2019 at 8:53 AM Palmer Dabbelt wrote:
On Fri, 23 Aug 2019 16:38:47 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu_helper.c | 39
On 10/16/19 9:37 AM, Andrew Jones wrote:
> When dumping a guest with dump-guest-memory also dump the SVE
> registers if they are in use.
>
> Signed-off-by: Andrew Jones
> ---
> v3:
> - Pulled sve_bswap64 out of kvm64.c and reused it here
> - Changed fpsr_offset and sve_size to only align to
On Wed, Oct 16, 2019 at 09:24:32AM +0800, Wei Yang wrote:
> Signed-off-by: Wei Yang
> CC: David Gibson
> ---
> scripts/checkpatch.pl | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
> index aa9a354a0e..4b360ed310 100755
> ---
On Mon, Oct 14, 2019 at 06:54:40PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Use RCU_READ_LOCK_GUARD and WITH_RCU_READ_LOCK_GUARD
> to replace the manual rcu_read_(un)lock calls.
>
> I think the only change is virtio_load which was missing unlocks
> in
Thomas Huth writes:
> Update / add some libraries that we use in the Travis builds, and
> enable compiling on the aarch64 host, too.
Queued 1-3 to testing/next and I'll have a play with 4/5 but probably
won't include them in the final PR unless they seem solid.
>
> Thomas Huth (5):
>
Solved: I added kvm.ignore_msrs=1 to kernel parameter!
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1848244
Title:
QEMU KVM IGD SandyBridge Passthrough crash
Status in QEMU:
New
Bug
I can confirm exactly the same issue on Arch linux running qemu-4.1.0.
After downgrading from 4.1.0 => 4.0.0 everything is running normal
again, no corruption detected and all qcow2 images stays healthy.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is
I can confirm exactly the same issue on Arch linux with ext4 filesystem
(qemu-4.1.0).
After downgrading from 4.1.0 => 4.0.0 everything is running normal
again, no corruption detected and all qcow2 images stays healthy.
--
You received this bug notification because you are a member of qemu-
Registering a SaveStateEntry object via savevm_state_insert_handler()
is an O(n) operation because the list is a priority queue maintained by
walking the list from head to tail to find a suitable insertion point.
This adds considerable overhead for VMs with many such objects. For
instance, ppc64
No reason to limit buffered copy to one cluster. Let's allow up to 1
MiB.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block-copy.h | 2 +-
block/block-copy.c | 48 +-
2 files changed, 33 insertions(+), 17 deletions(-)
diff --git
Move bounce_buffer allocation block_copy_with_bounce_buffer. This
commit simplifies further work on implementing copying by larger chunks
(of different size) and further asynchronous handling of block_copy
iterations (with help of block/aio_task API).
Allocation works fast, a lot faster than disk
I'm going to bring block-status driven, async copying process to
block-copy, to make it fast. The first step is to limit memory usage of
backup, here is it.
v2: [mostly by Max's comments]
Now based on master (Thank you Max!)
01: add Max's r-b
02: add Max's r-b
03: - refactor block_copy_do_copy
Merge copying code into one function block_copy_do_copy, which only
calls bdrv_ io functions and don't do any synchronization (like dirty
bitmap set/reset).
Refactor block_copy() function so that it takes full decision about
size of chunk to be copied and does all the synchronization (checking
Large copy range may imply memory allocation and large io effort, so
using 2G copy range request may be bad idea. Let's limit it to 16 MiB.
It also helps the following patch to refactor copy-with-offload
fallback to copy-with-bounce-buffer.
Note, that total memory usage of backup is still not
Introduce an API for some shared splittable resource, like memory.
It's going to be used by backup. Backup uses both read/write io and
copy_range. copy_range may consume memory implictly, so the new API is
abstract: it doesn't allocate any real memory by but only hands out
tickets.
The idea is
Currently total allocation for parallel requests to block-copy instance
is unlimited. Let's limit it to 128 MiB.
For now block-copy is used only in backup, so actually we limit total
allocation for backup job.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block-copy.h | 3 +++
On 10/14/19 3:59 PM, Alex Bennée wrote:
Again this is guess work based on public websites. Please confirm.
Signed-off-by: Alex Bennée
Cc: Emanuele Giuseppe Esposito
Cc: Bastian Koppelmann
Cc: "Kővágó, Zoltán"
Cc: Li Qiang
Cc: Li Qiang
---
contrib/gitdm/group-map-academics | 3 +++
Patchew URL: https://patchew.org/QEMU/20191016073240.12473-1-mky...@tachyum.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH] Added hardfloat conversion from float32 to float64
Type: series
Message-id:
On 16.10.19 16:54, Andrew Jones wrote:
Beata Michalska noticed this missing visit_free() while reviewing
arm's implementation of qmp_query_cpu_model_expansion(), which is
modeled off this s390x implementation.
Nice to see ARM support getting added.
Signed-off-by: Andrew Jones
---
From: Sam Eiderman
Add QTest tests to check the logical geometry override option.
The tests in hd-geo-test are out of date - they only test IDE and do not
test interesting MBRs.
Creating qcow2 disks with specific size and MBR layout is currently
unused - we only use a default empty MBR.
From: Sam Eiderman
Using fw_cfg, supply logical CHS values directly from QEMU to the BIOS.
Non-standard logical geometries break under QEMU.
A virtual disk which contains an operating system which depends on
logical geometries (consistent values being reported from BIOS INT13
AH=08) will most
From: Sam Eiderman
Relevant devices are:
* ide-hd (and ide-cd, ide-drive)
* scsi-hd (and scsi-cd, scsi-disk, scsi-block)
* virtio-blk-pci
We do not call del_boot_device_lchs() for ide-* since we don't need to -
IDE block devices do not support unplugging.
Reviewed-by: Karl Heubaum
On 10/16/19 5:19 PM, Sam Eiderman wrote:
Sure!
Philippe withdrew his R-b on 7/8, as I explained 7/8 is fine (only
need to remove a bad comment) the problem was in the tests 8/8 -
should I include the original R/b?
I withdrew it because John was preparing his pull request, and I needed
more
From: Sam Eiderman
Move device name construction to a separate function.
We will reuse this function in the following commit to pass logical CHS
parameters through fw_cfg much like we currently pass bootindex.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Reviewed-by: Philippe
From: Sam Eiderman
We will need to add LCHS removal logic to scsi-hd's unrealize() in the
next commit.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Sam Eiderman
Signed-off-by: Sam Eiderman
---
hw/scsi/scsi-bus.c | 16
From: Sam Eiderman
Fixing tabbing in block related macros.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Sam Eiderman
Signed-off-by: Sam Eiderman
---
hw/ide/qdev.c| 2 +-
include/hw/block/block.h | 16
2
From: Sam Eiderman
Add an interface to provide direct logical CHS values for boot devices.
We will use this interface in the next commits.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Signed-off-by: Sam Eiderman
Signed-off-by: Sam Eiderman
---
bootdevice.c| 55
From: Sam Eiderman
Add QTest tests to check the logical geometry override option.
The tests in hd-geo-test are out of date - they only test IDE and do not
test interesting MBRs.
Creating qcow2 disks with specific size and MBR layout is currently
unused - we only use a default empty MBR.
From: Sam Eiderman
Add logical geometry variables to BlockConf.
A user can now supply "lcyls", "lheads" & "lsecs" for any HD device
that supports CHS ("cyls", "heads", "secs").
These devices include:
* ide-hd
* scsi-hd
* virtio-blk-pci
In future commits we will use the provided
v1:
Non-standard logical geometries break under QEMU.
A virtual disk which contains an operating system which depends on
logical geometries (consistent values being reported from BIOS INT13
AH=08) will most likely break under QEMU/SeaBIOS if it has non-standard
logical geometries - for example
When dumping a guest with dump-guest-memory also dump the SVE
registers if they are in use.
Signed-off-by: Andrew Jones
---
v3:
- Pulled sve_bswap64 out of kvm64.c and reused it here
- Changed fpsr_offset and sve_size to only align to a
16 byte boundary from the note payload offset, not
Hi
On Wed, Oct 16, 2019 at 12:19 PM Sergio Lopez wrote:
>
> Document the new microvm machine type.
>
> Signed-off-by: Sergio Lopez
> Reviewed-by: Michael S. Tsirkin
> ---
> docs/microvm.rst | 98
> 1 file changed, 98 insertions(+)
> create
Add a case to the iotest #030 that tests the 'compress' option for a
block-stream job.
Signed-off-by: Andrey Shinkevich
---
tests/qemu-iotests/030 | 51 +-
tests/qemu-iotests/030.out | 4 ++--
2 files changed, 52 insertions(+), 3 deletions(-)
To inform the block layer about writing all the data compressed, we
introduce the 'compress' command line option. Based on that option, the
written data will be aligned by the cluster size at the generic layer.
Suggested-by: Roman Kagan
Suggested-by: Vladimir Sementsov-Ogievskiy
Signed-off-by:
QEMU currently supports writing compressed data of the size equal to
one cluster. This patch allows writing QCOW2 compressed data that
exceed one cluster. Now, we split buffered data into separate clusters
and write them compressed using the existing functionality.
Suggested-by: Pavel Butsykin
New enhancements for writing compressed data to QCOW2 image.
v4:
The 'compression' support at the block generic layer has been
accumulated in the separate patch 1/4. A little code refactoring
was made.
v3:
Instead of introducing multiple key options for many drivers, the
Add the test case to the iotest #214 that checks possibility of writing
compressed data of more than one cluster size.
Signed-off-by: Andrey Shinkevich
---
tests/qemu-iotests/214 | 35 +++
tests/qemu-iotests/214.out | 15 +++
2 files changed, 50
On Wed, Oct 16, 2019 at 04:16:57PM +0100, Beata Michalska wrote:
> On Wed, 16 Oct 2019 at 14:50, Andrew Jones wrote:
> >
> > On Wed, Oct 16, 2019 at 02:24:50PM +0100, Beata Michalska wrote:
> > > On Tue, 15 Oct 2019 at 12:56, Beata Michalska
> > > wrote:
> > > >
> > > > On Tue, 15 Oct 2019 at
On Wed, 9 Oct 2019 17:07:59 +1100
David Gibson wrote:
> This is a substantial rework to clean up the handling of IRQs in
> spapr. It includes some cleanups to both the XICS and XIVE interrupt
> controller backends, as well as more to the common spapr irq handling
> infrastructure.
>
Patches
These patches are based on gitlab.com/virtio-fs/qemu.git virtio-fs-dev.
virtiofsd is sandboxed so that it does not have access to the system in the
event that the process is compromised. At the moment we use seccomp and mount
namespaces to restrict the list of allowed syscalls and only give
virtiofsd needs access to /proc/self/fd. Let's move to a new pid
namespace so that a compromised process cannot see another other
processes running on the system.
One wrinkle in this approach: unshare(CLONE_NEWPID) affects *child*
processes and not the current process. Therefore we need to fork
If the process is compromised there should be no network access. Use an
empty network namespace to sandbox networking.
Signed-off-by: Stefan Hajnoczi
---
contrib/virtiofsd/passthrough_ll.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/contrib/virtiofsd/passthrough_ll.c
On Wed, Oct 16, 2019 at 11:35 PM wrote:
>
> Patchew URL:
> https://patchew.org/QEMU/20191016112209.9024-1-chen.zh...@intel.com/
>
>
>
> Hi,
>
> This series failed the docker-quick@centos7 build test. Please find the
> testing commands and
> their output below. If you have Docker installed, you
On 10/15/19 6:24 PM, Wei Yang wrote:
> if ($line =~ /\bbzero\(/) {
> ERROR("use memset() instead of bzero()\n" . $herecurr);
> }
> + if ($line =~ /getpagesize\(\)/) {
> + ERROR("use qemu_real_host_page_size instead
On Wed, Oct 16, 2019 at 11:35 PM wrote:
> Patchew URL:
> https://patchew.org/QEMU/20191016112209.9024-1-chen.zh...@intel.com/
>
>
>
> Hi,
>
> This series failed the docker-quick@centos7 build test. Please find the
> testing commands and
> their output below. If you have Docker installed, you can
On 10/16/19 2:13 AM, Andrew Jones wrote:
> On Thu, Oct 10, 2019 at 01:33:02PM -0400, Richard Henderson wrote:
>> Ah, I wonder if you changed things around with the ifdefs due to the pregs.
>> There's no trivial solution for those. It'd be nice to share the bswapping
>> subroutine that you add in
On 10/16/19 12:32 AM, Matus Kysel wrote:
> +float64 float32_to_float64(float32 a, float_status *status)
> +{
> +if (unlikely(!float32_is_normal(a))) {
> +return soft_float32_to_float64(a, status);
> +} else if (float32_is_zero(a)) {
> +return float64_set_sign(float64_zero,
Patchew URL:
https://patchew.org/QEMU/20191016112209.9024-1-chen.zh...@intel.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
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