On Sat, Nov 16, 2019 at 7:09 AM Bin Meng wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 's
On Tue, Nov 19, 2019 at 12:03 AM Zhuang, Siwei (Data61, Kensington
NSW) wrote:
>
> This patch adds an optional function pointer, "sym_cb", to
> riscv_load_kernel() which provides the possibility to access the symbol
> table during kernel loading.
>
> The pointer is ignored, if supplied with Image
Include AVR maintaners in MAINTAINERS file
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5e5e3e52d6..ad2d9dd04a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -163,6 +163,15 @@ S: Maintained
F: hw/arm/sm
A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs
include a lot of on-board peripherals.
NOTE: this is not a real board
NOTE: it's used for CPU testing
Signed-off-by: Michael Rol
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/tr
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 174 +
1 file changed, 174 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index f2ec2e2d2f..30ba13bdd7 100644
Print out 'T' through serial port
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Acked-by: Thomas Huth
---
tests/boot-serial-test.c | 10 ++
tests/Makefile.include | 2 ++
2 files changed, 12 insertions(+)
diff --git a/tests/boo
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 549 -
1 file changed, 546 insert
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Phil
Make AVR support buildable
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
---
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
target/avr/Makefile.objs| 34 +
3 fi
From: Sarah Harris
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-o
Stubs for unimplemented instructions and helpers for instructions that need to
interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex
peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to
generate wake interrupts.
Memory a
Provide function disassembles executed instruction when `-d in_asm` is
provided
Signed-off-by: Michael Rolnik
---
target/avr/cpu.h | 1 +
target/avr/cpu.c | 2 +-
target/avr/disas.c | 214 +
target/avr/translate.c | 11 +++
4 files cha
Add AVR related definitions into QEMU
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
---
qapi/machine.json | 3 ++-
include/disas/dis-asm.h| 6 ++
include/sysemu/arch_init.h | 1 +
arch_init.c| 2 ++
tests/machi
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/insn.decode | 175 +
1 file changed, 175 insertions(+)
create mode 100644 target/avr
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 822 +
1 file changed, 822 insertions(+)
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 1123
1 file changed, 1123 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/transla
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 132 +
1 file changed, 132 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c b/target/avr/translate.c
new file mode 100644
index 00..53c9892a60
--
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
Acked-by: Igor Mammedov
---
targe
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet
On Tuesday, October 29, 2019, Michael Rolnik wrote:
> Signed-off-by: Michael Rolnik
> ---
> MAINTAINERS | 9 +
> arch_init.c | 2 ++
> configure | 7 +++
> default-configs/avr-softmmu.mak | 5 +
> include/disas/di
On Tuesday, October 29, 2019, Michael Rolnik wrote:
> 1. Avocado test
> The test is based on
> https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
> demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX'
> out.
> it also demostrates that timer and IR
On Fri, Nov 22, 2019 at 7:12 PM Aleksandar Markovic
wrote:
>
> > +
> > +static void avr_avr1_initfn(Object *obj)
> > +{
> > +AVRCPU *cpu = AVR_CPU(obj);
> > +CPUAVRState *env = &cpu->env;
> > +
> > +avr_set_feature(env, AVR_FEATURE_LPM);
> > +avr_set_feature(env, AVR_FEATURE_2_BYTE
On Donnerstag, 21. November 2019 00:37:36 CET Christian Schoenebeck wrote:
> If so, I haven't understood how precisely v9fs_co_run_in_worker() works. I
> mean I understand now how QEMU coroutines are working, and the idea of
> v9fs_co_run_in_worker() is dispatching the passed code block to the work
From: Dan Schatzberg
Some filesystems may return 0s in statfs (trivially, a FUSE filesystem
can do so). QEMU should handle this gracefully and just behave the
same as if statfs failed.
Signed-off-by: Dan Schatzberg
Acked-by: Christian Schoenebeck
Signed-off-by: Greg Kurz
---
hw/9pfs/9p.c | 6
The following changes since commit 2061735ff09f9d5e67c501a96227b470e7de69b1:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2019-11-21 17:18:40 +)
are available in the Git repository at:
https://github.com/gkurz/qemu.git tags/9p-fix-2019-11-23
for you to
I believe I got this number from this spec
https://ww1.microchip.com/downloads/en/devicedoc/atmel-2549-8-bit-avr-microcontroller-atmega640-1280-1281-2560-2561_datasheet.pdf
on page 101
On Fri, Nov 22, 2019 at 7:28 PM Aleksandar Markovic
wrote:
>
> > +#ifndef CONFIG_USER_ONLY
> > +/* Set the n
Sarah,
could you please answer this question?
Thanks,
Michael
On Fri, Nov 22, 2019 at 6:49 PM Aleksandar Markovic
wrote:
>
> On Tue, Oct 29, 2019 at 10:25 PM Michael Rolnik wrote:
> >
> > From: Sarah Harris
> >
> > These were designed to facilitate testing but should provide enough
> > functi
On Fri, 22 Nov 2019 22:53:09 +0100
Christian Schoenebeck wrote:
> On Freitag, 22. November 2019 21:00:34 CET Dan Schatzberg wrote:
> > Some filesystems may return 0s in statfs (trivially, a FUSE filesystem
> > can do so). QEMU should handle this gracefully and just behave the
> > same as if statf
On Saturday, November 23, 2019, Philippe Mathieu-Daudé
wrote:
> On 11/22/19 9:37 PM, Aleksandar Markovic wrote:
>
>> On Fri, Nov 22, 2019 at 9:28 PM Philippe Mathieu-Daudé
>> wrote:
>>
>>>
>>> On 11/13/19 2:47 PM, Aleksandar Markovic wrote:
>>>
From: Aleksandar Markovic
Add two f
On Sun, Nov 03, 2019 at 09:56:01PM +0100, Sven Schnelle wrote:
> Hi,
>
> these series adds quite a lot to the HPPA emulation in QEMU:
> i82596 emulation from Helge, PS/2 and Artist graphics emulation.
> [..]
Ping? :-)
Regards
Sven
On 11/22/19 9:37 PM, Aleksandar Markovic wrote:
On Fri, Nov 22, 2019 at 9:28 PM Philippe Mathieu-Daudé
wrote:
On 11/13/19 2:47 PM, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Add two files that were recently introduced in a refactoring,
that Malta emulation relies on. They are adde
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
registers traps to EL2, and QEMU has so far ignored this requirement.
This breaks (among other things) KVM guests that have PtrAuth enabled,
while the hypervisor doesn't want to expose the feature to its guest.
To achieve this, KVM tr
On Thursday, November 21, 2019, Helge Deller wrote:
> The strace functionality in qemu-user lacks the possibility to trace
> which real values get returned to pointers in userspace by syscalls.
>
> For example, the read() and getcwd() syscalls currently only show the
> destination address where t
On 22/11/19 18:34, Alex Williamson wrote:
> +config INTEL_IGD_PASSTHROUGH
> +default y
If it's "default y", it need not be "implied". It probably shouldn't be
"default y", since it's I440FX-specific.
Paolo
> +bool
> +
> config PREP_PCI
> bool
> select PCI
> @@ -32,6 +36,7 @@
On Fri, Nov 22, 2019 at 07:17:05PM +0100, Cédric Le Goater wrote:
> On 15/11/2019 17:24, Cédric Le Goater wrote:
> > Hello,
> >
> > The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
> > acts as an hypervisor (L0). Supporting emulation of KVM to run guests
> > (L1) requires a few m
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