Re: [PATCH v17 03/14] util/cutils: refactor do_strtosz() to support suffixes list

Tao Xu writes: > Add do_strtomul() to convert string according to different suffixes. > > Reviewed-by: Eduardo Habkost > Signed-off-by: Tao Xu What's the actual change here? "Refactor" suggests the interfaces stay the same, only their implementation changes. "Support suffixes list" suggests

[PATCH v6 17/20] ppc/xive: Synthesize interrupt from the saved IPB in the NVT

When a vCPU is dispatched on a HW thread, its context is pushed in the thread registers and it is activated by setting the VO bit in the CAM line word2. The HW grabs the associated NVT, pulls the IPB bits and merges them with the IPB of the new context. If interrupts were missed while the vCPU was

[PATCH v6 19/20] ppc/pnv: Extend XiveRouter with a get_block_id() handler

When doing CAM line compares, fetch the block id from the interrupt controller which can have set the PC_TCTXT_CHIPID field. Signed-off-by: Cédric Le Goater --- include/hw/ppc/xive.h | 2 +- hw/intc/pnv_xive.c| 6 ++ hw/intc/spapr_xive.c | 6 ++ hw/intc/xive.c| 21

[PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system

The TIMA region gives access to the thread interrupt context registers of a CPU. It is mapped at the same address on all chips and can be accessed by any CPU of the system. To identify the chip from which the access is being done, the PowerBUS uses a 'chip' field in the load/store messages. QEMU

[PATCH v6 10/20] ppc/spapr: Implement the XiveFabric interface

The CAM line matching sequence in the pseries machine does not change much apart from the use of the new QOM interfaces. There is an extra indirection because of the sPAPR IRQ backend of the machine. Only the XIVE backend implements the new 'match_nvt' handler. Reviewed-by: Greg Kurz

[PATCH v6 14/20] ppc/xive: Move the TIMA operations to the controller model

On the P9 Processor, the thread interrupt context registers of a CPU can be accessed "directly" when by load/store from the CPU or "indirectly" by the IC through an indirect TIMA page. This requires to configure first the PC_TCTXT_INDIRx registers. Today, we rely on the get_tctx() handler to

[PATCH v6 15/20] ppc/xive: Remove the get_tctx() XiveRouter handler

It is now unused. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater --- include/hw/ppc/xive.h | 2 -- hw/intc/pnv_xive.c| 13 - hw/intc/spapr_xive.c | 8 hw/intc/xive.c| 7 --- 4 files changed, 30 deletions(-) diff --git a/include/hw/ppc/xive.h

[PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper

and use this helper to exclude CPUs which are not enabled in the XIVE controller. Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 5 + hw/intc/pnv_xive.c | 19 +++ 2 files changed, 24 insertions(+) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index

[PATCH v6 09/20] ppc/pnv: Implement the XiveFabric interface

The CAM line matching on the PowerNV machine now scans all chips of the system and all CPUs of a chip to find a dispatched NVT in the thread contexts. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 35 +++ 1 file changed, 35

[PATCH v6 20/20] ppc/pnv: Dump the XIVE NVT table

This is useful to dump the saved contexts of the vCPUs : configuration of the base END index of the vCPU and the Interrupt Pending Buffer register, which is updated when an interrupt can not be presented. When dumping the NVT table, we skip empty indirect pages which are not necessarily

[PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter

The TIMA operations are performed on behalf of the XIVE IVPE sub-engine (Presenter) on the thread interrupt context registers. The current operations supported by the model are simple and do not require access to the controller but more complex operations will need access to the controller NVT

[PATCH v6 18/20] ppc/pnv: Introduce a pnv_xive_block_id() helper

When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field overrides the hardwired chip ID in the Powerbus operations and for CAM compares. This is typically used in the one block-per-chip configuration to associate a unique block id number to each IC of the system. Simplify the model

[PATCH v6 08/20] ppc/xive: Introduce a XiveFabric interface

The XiveFabric QOM interface acts as the PowerBUS interface between the interrupt controller and the system and should be implemented by the QEMU machine. On HW, the XIVE sub-engine is responsible for the communication with the other chip is the Common Queue (CQ) bridge unit. This interface

[PATCH v6 05/20] ppc: Introduce a ppc_cpu_pir() helper

Signed-off-by: Cédric Le Goater --- include/hw/ppc/ppc.h | 1 + hw/ppc/ppc.c | 9 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 4bdcb8bacd4e..585be6ab98c5 100644 --- a/include/hw/ppc/ppc.h +++

[PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces

Now that the machines have handlers implementing the XiveFabric and XivePresenter interfaces, remove xive_presenter_match() and make use of the 'match_nvt' handler of the machine. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater --- hw/intc/xive.c | 48

[PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT

CPU_FOREACH() loops on all the CPUs of the machine which is incorrect. Each XIVE Presenter should scan only the HW threads of the chip it belongs to. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater --- hw/intc/pnv_xive.c | 61

[PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper

We will use it to resend missed interrupts when a vCPU context is pushed on a HW thread. Signed-off-by: Cédric Le Goater --- include/hw/ppc/xive.h | 1 + hw/intc/xive.c| 21 +++-- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/hw/ppc/xive.h

[PATCH v6 01/20] ppc/xive: Introduce a XivePresenter interface

When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification Virtual Target (NVT) to notify, it broadcasts a message on the PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT dispatched on one of its HW threads, and then forwards the notification if any response was received.

[PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access

When the TIMA of a CPU needs to be accessed from the indirect page, the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0 register. This thread id is relative to the chip and not to the system. Introduce a helper routine to look for a CPU of a given PIR and fix

[PATCH v6 02/20] ppc/xive: Implement the XivePresenter interface

Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt' handler of the XivePresenter QOM interface. This is simply moving code and taking into account the new API. To be noted that the xive_router_get_tctx() helper is not used anymore when doing CAM matching and will be removed

[PATCH v6 03/20] ppc/pnv: Instantiate cores separately

From: Greg Kurz Allocating a big void * array to store multiple objects isn't a recommended practice for various reasons: - no compile time type checking - potential dangling pointers if a reference on an individual is taken and the array is freed later on - duplicate boiler plate

[PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests

Hello, The QEMU PowerNV machine emulates a baremetal OpenPOWER system and acts as an hypervisor (L0). Supporting emulation of KVM to run guests (L1) requires a few more extensions, among which guest support for the XIVE interrupt controller on POWER9 processor. The following changes extend the

Re: [PATCH v17 02/14] util/cutils: Use qemu_strtold_finite to parse size

Tao Xu writes: > Support full 64bit precision, modify related test cases. That's not true in general: long double need not be any wider than double. It might be true on the host machines we support, but I don't know. If we decide to rely on it, we better make the build fail when the host

Re: [PATCH v17 01/14] util/cutils: Add Add qemu_strtold and qemu_strtold_finite

Tao Xu writes: > Work like qemu_strtod() and qemu_strtold_finite, except store long > double. > > Signed-off-by: Tao Xu > --- > > No changes in v17. > --- > include/qemu/cutils.h | 3 +++ > util/cutils.c | 48 ++- > 2 files changed, 50

Re: [PATCH v2 15/20] nvme: add support for scatter gather lists

On Tue, Nov 12, 2019 at 03:25:18PM +, Beata Michalska wrote: > Hi Klaus, > > On Tue, 15 Oct 2019 at 11:57, Klaus Jensen wrote: > > +static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg, > > +NvmeSglDescriptor sgl, uint32_t len, NvmeRequest *req) > > +{ > > +const int MAX_NSGLD =

[PULL 1/1] util/cutils: Fix incorrect integer->float conversion caught by clang

From: Fangrui Song Clang does not like do_strtosz()'s code to guard against overflow: qemu/util/cutils.c:245:23: error: implicit conversion from 'unsigned long' to 'double' changes value from 18446744073709550592 to 18446744073709551616 [-Werror,-Wimplicit-int-float-conversion] The

[PULL 0/1] Miscellaneous patches for 2019-11-25

The following changes since commit 2061735ff09f9d5e67c501a96227b470e7de69b1: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-11-21 17:18:40 +) are available in the Git repository at: git://repo.or.cz/qemu/armbru.git tags/pull-misc-2019-11-25 for you

[PATCH v7] Implement backend program convention command for vhost-user-blk

From: Micky Yun Chan This patch is to add standard commands defined in docs/interop/vhost-user.rst For vhost-user-* program Signed-off-by: Micky Yun Chan (michiboo) --- contrib/vhost-user-blk/vhost-user-blk.c | 108 ++-- docs/interop/vhost-user.json| 31

[Bug 1824704] Re: -k tr not working after v20171217! turkish keyboard dont working

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1824704 Title: -k tr not

Re: [PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking

On Mon, Nov 25, 2019 at 08:33:19AM +0800, yadong...@intel.com wrote: > From: "Qi, Yadong" > > The following patches are to refine/fix issues of reserved fields checking > logic > of Second-Level Paging Entries of VT-d: > - split the resevred fields arrays into two ones, > - large page only

[PATCH v3 1/2] intel_iommu: refine SL-PEs reserved fields checking

From: "Qi, Yadong" 1. split the resevred fields arrays into two ones, 2. large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page. Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 37

[PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking

From: "Qi, Yadong" The following patches are to refine/fix issues of reserved fields checking logic of Second-Level Paging Entries of VT-d: - split the resevred fields arrays into two ones, - large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page, - when

[PATCH v3 2/2] intel_iommu: TM field should not be in reserved bits

From: "Qi, Yadong" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 9 ++--- hw/i386/intel_iommu_internal.h | 13 ++--- 2 files changed, 16 insertions(+), 6

[PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking

From: "Qi, Yadong" The following patches are to refine/fix issues of reserved fields checking logic of Second-Level Paging Entries of VT-d: - split the resevred fields arrays into two ones, - large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page, - when

Re: [PATCH v36 01/17] target/avr: Add outward facing interfaces and core CPU logic

On Sunday, November 24, 2019, Michael Rolnik wrote: > This includes: > - CPU data structures > - object model classes and functions > - migration functions > - GDB hooks > > Co-developed-by: Michael Rolnik > Co-developed-by: Sarah Harris > Signed-off-by: Michael Rolnik > Signed-off-by: Sarah

Re: [PATCH v17 12/14] hmat acpi: Build Memory Side Cache Information Structure(s)

On 11/22/2019 8:32 PM, Igor Mammedov wrote: On Fri, 22 Nov 2019 15:48:24 +0800 Tao Xu wrote: From: Liu Jingqi This structure describes memory side cache information for memory proximity domains if the memory side cache is present and the physical device forms the memory side cache. The

Re: [PATCH v17 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT)

On 11/22/2019 8:38 PM, Igor Mammedov wrote: On Fri, 22 Nov 2019 01:17:12 -0800 (PST) no-re...@patchew.org wrote: Patchew URL: https://patchew.org/QEMU/20191122074826.1373-1-tao3...@intel.com/ do not ignore warnings "line over 80 characters", just fix them OK I will fin them in the next

Re: [PATCH v17 01/14] util/cutils: Add Add qemu_strtold and qemu_strtold_finite

Hi Markus, Do you have any comments on this patch and 02/14 05/14 06/14. Thank you! On 11/22/2019 3:48 PM, Xu, Tao3 wrote: Work like qemu_strtod() and qemu_strtold_finite, except store long double. Signed-off-by: Tao Xu --- No changes in v17. --- include/qemu/cutils.h | 3 +++

[Bug 1853781] Re: Baremetal kernel built from assembly runs multiple times

I just noticed that on lines 53 and 55 of the attached file, I forgot to replace the register "r0" with its alias "address". Fixing these lines doesn't change the behavior of the program. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[Bug 1853781] [NEW] Baremetal kernel built from assembly runs multiple times

Public bug reported: QEMU version: 4.1.0. Full command used to launch: qemu-system-arm -machine raspi2 -kernel main (Technically, the first term of the command is actually "~/Applications/QEMU/qemu-4.1.0/build/arm-softmmu/qemu-system-arm", but I shortened it for readability.) Host information:

Re: [PATCH v36 01/17] target/avr: Add outward facing interfaces and core CPU logic

On Sunday, November 24, 2019, Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Sunday, November 24, 2019, Michael Rolnik wrote: > >> This includes: >> - CPU data structures >> - object model classes and functions >> - migration functions >> - GDB hooks >> >> Co-developed-by:

[PATCH v2 4/5] hvf: more accurately match SDM when setting CR0 and PDPTE registers

More accurately match SDM when setting CR0 and PDPTE registers. Clear PDPTE registers when resetting vcpus. Signed-off-by: Cameron Esfahani --- target/i386/hvf/hvf.c | 8 target/i386/hvf/vmx.h | 18 ++ 2 files changed, 18 insertions(+), 8 deletions(-) diff --git

[PATCH v2 1/5] hvf: non-RAM, non-ROMD memory ranges are now correctly mapped in

If an area is non-RAM and non-ROMD, then remove mappings so accesses will trap and can be emulated. Change hvf_find_overlap_slot() to take a size instead of an end address: it wouldn't return a slot because callers would pass the same address for start and end. Don't always map area as

[PATCH v2 0/5] hvf: stability fixes for HVF

The following patches fix stability issues with running QEMU on Apple Hypervisor Framework (HVF): - non-RAM, non-ROMD areas need to trap so accesses can be correctly emulated. - Current TSC synchronization implementation is insufficient: when running with more than 1 core, TSC values can go

[PATCH v2 2/5] hvf: remove TSC synchronization code because it isn't fully complete

The existing code in QEMU's HVF support to attempt to synchronize TSC across multiple cores is not sufficient. TSC value on other cores can go backwards. Until implementation is fixed, remove calls to hv_vm_sync_tsc(). Pass through TSC to guest OS. Signed-off-by: Cameron Esfahani ---

[PATCH v2 3/5] hvf: correctly handle REX prefix in relation to legacy prefixes

In real x86 processors, the REX prefix must come after legacy prefixes. REX before legacy is ignored. Update the HVF emulation code to properly handle this. Fix some spelling errors in constants. Fix some decoder table initialization issues found by Coverity. Signed-off-by: Cameron Esfahani

[PATCH v2 5/5] hvf: save away type as well as vector so we can reinject them

Save away type as well as vector in hvf_store_events() so we can correctly reinject both in hvf_inject_interrupts(). Make sure to clear ins_len and has_error_code when ins_len isn't valid and error_code isn't set. Signed-off-by: Cameron Esfahani --- target/i386/hvf/hvf.c| 18

Re: [PATCH v36 01/17] target/avr: Add outward facing interfaces and core CPU logic

On Sunday, November 24, 2019, Michael Rolnik wrote: > This includes: > - CPU data structures > - object model classes and functions > - migration functions > - GDB hooks > > Co-developed-by: Michael Rolnik > Co-developed-by: Sarah Harris > Signed-off-by: Michael Rolnik > Signed-off-by: Sarah

Re: [PATCH v36 03/17] target/avr: Add instruction decoding

On Sunday, November 24, 2019, Michael Rolnik wrote: > This includes: > - encoding of all 16 bit instructions > - encoding of all 32 bit instructions > > Signed-off-by: Michael Rolnik > Tested-by: Philippe Mathieu-Daudé > --- License preamble missing. > target/avr/insn.decode | 175

Re: [PATCH v36 16/17] target/avr: Add Avocado test

On Sunday, November 24, 2019, Michael Rolnik wrote: > The test is based on > https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo > demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. > it also demostrates that timer and IRQ are working > > Signed-off-by:

Re: [PATCH v36 01/17] target/avr: Add outward facing interfaces and core CPU logic

On Sunday, November 24, 2019, Michael Rolnik wrote: > This includes: > - CPU data structures > - object model classes and functions > - migration functions > - GDB hooks > > Co-developed-by: Michael Rolnik > Co-developed-by: Sarah Harris > Signed-off-by: Michael Rolnik > Signed-off-by: Sarah

Re: [PATCH v36 10/17] target/avr: Add instruction disassembly function

On Sunday, November 24, 2019, Michael Rolnik wrote: > Provide function disassembles executed instruction when `-d in_asm` is > provided > > Signed-off-by: Michael Rolnik > --- You should add "Suggested-by:"s for Philippe, Richard, and myself in tge commit message. Aleksandar

Re: [PATCH v36 10/17] target/avr: Add instruction disassembly function

On Sunday, November 24, 2019, Michael Rolnik wrote: > Provide function disassembles executed instruction when `-d in_asm` is > provided > > Signed-off-by: Michael Rolnik > --- > target/avr/cpu.h | 1 + > target/avr/cpu.c | 2 +- > target/avr/disas.c | 214

[PATCH v36 11/17] target/avr: Add limited support for USART and 16 bit timer peripherals

On Sunday, November 24, 2019, Michael Rolnik wrote: > From: Sarah Harris > > These were designed to facilitate testing but should provide enough > function to be useful in other contexts. > Only a subset of the functions of each peripheral is implemented, mainly > due to the lack of a standard

Re: [PATCH] linux-user: Improve strace output for read() and getcwd()

On Sunday, November 24, 2019, Helge Deller wrote: > On 24.11.19 13:10, Aleksandar Markovic wrote: > > > > > > On Sunday, November 24, 2019, Helge Deller del...@gmx.de>> wrote: > > > > On 23.11.19 12:34, Aleksandar Markovic wrote: > > > On Thursday, November 21, 2019, Helge Deller

Re: [PATCH] linux-user: Improve strace output for read() and getcwd()

On 24.11.19 13:10, Aleksandar Markovic wrote: > > > On Sunday, November 24, 2019, Helge Deller > wrote: > > On 23.11.19 12:34, Aleksandar Markovic wrote: > > On Thursday, November 21, 2019, Helge Deller

Re: [PATCH v2] linux-user/strace: Improve strace output for read() and getcwd()

Patchew URL: https://patchew.org/QEMU/20191124115656.ga23...@ls3530.fritz.box/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v2] linux-user/strace: Improve strace output for read() and getcwd() Type: series Message-id:

Re: [PATCH 0/5] hvf: stability fixes for HVF

On Thu, 21 Nov 2019 14:54:49 -0800 Cameron Esfahani via wrote: > The following patches fix stability issues with running QEMU on Apple > Hypervisor Framework (HVF): > - non-RAM, non-ROMD areas need to trap so accesses can be correctly > emulated. > - Current TSC synchronization implementation

Re: [PATCH] linux-user: Improve strace output for read() and getcwd()

On Sunday, November 24, 2019, Helge Deller wrote: > On 23.11.19 12:34, Aleksandar Markovic wrote: > > On Thursday, November 21, 2019, Helge Deller del...@gmx.de>> wrote: > > > > The strace functionality in qemu-user lacks the possibility to trace > > which real values get returned to

[PATCH v2] linux-user/strace: Improve strace output for read() and getcwd()

The strace functionality in qemu-user lacks the possibility to trace which real values get returned to pointers in userspace by syscalls. For example, the read() and getcwd() syscalls currently only show the destination address where the syscalls should put the return values: 2532

Re: [PATCH] linux-user: Improve strace output for read() and getcwd()

On 23.11.19 12:34, Aleksandar Markovic wrote: > On Thursday, November 21, 2019, Helge Deller > wrote: > > The strace functionality in qemu-user lacks the possibility to trace > which real values get returned to pointers in userspace by syscalls. > > For example,