Re: [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX

On 2/1/20 11:07 PM, Philippe Mathieu-Daudé wrote: > On 2/1/20 9:12 PM, Philippe Mathieu-Daudé wrote: >> Hi Richard, >> >> On 1/8/20 4:45 AM, Richard Henderson wrote: >>> The separate suffixed functions were used to construct >>> some do_##insn function switched on mmu_idx. The interface >>> is exa

[PATCH v2 12/14] target/arm: Update MSR access to UAO

Signed-off-by: Richard Henderson --- v2: Move reginfo to file scope; avoid setting uao from spsr when the feature is not enabled (pmm). --- target/arm/cpu.h | 6 ++ target/arm/helper-a64.c| 3 +++ target/arm/helper.c| 21 + target/arm/translate-

[PATCH v2 14/14] target/arm: Enable ARMv8.2-UAO in -cpu max

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 57fbc5eade..1359564c55 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -676,6 +676,10 @@ static voi

[PATCH v2 09/14] target/arm: Implement ATS1E1 system registers

This is a minor enhancement over ARMv8.1-PAN. The *_PAN mmu_idx are used with the existing do_ats_write. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Move regdefs to file scope (pmm). --- target/arm/helper.c | 56 - 1 file chang

[PATCH v2 07/14] target/arm: Enforce PAN semantics in get_S1prot

If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 13 + target/arm/helper.c| 3 +++ 2 files changed, 16 insertions(+) diff --git a/target/arm/internals.h b/target/arm/inte

[PATCH v2 08/14] target/arm: Set PAN bit as required on exception entry

The PAN bit is preserved, or set as per SCTLR_ELx.SPAN, plus several other conditions listed in the ARM ARM. Signed-off-by: Richard Henderson --- v2: Tidy preservation of CPSR_PAN in take_aarch32_exception (pmm). --- target/arm/helper.c | 40 +--- 1 file chang

[PATCH v2 06/14] target/arm: Update arm_mmu_idx_el for PAN

Examine the PAN bit for EL1, EL2, and Secure EL1 to determine if it applies. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 90a22921dc..638abe6af0 10

[PATCH v2 13/14] target/arm: Implement UAO semantics

We need only override the current condition under which TBFLAG_A64.UNPRIV is set. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 41 + 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/target/arm/helper

[PATCH v2 04/14] target/arm: Move LOR regdefs to file scope

For static const regdefs, file scope is preferred. Signed-off-by: Richard Henderson --- target/arm/helper.c | 57 +++-- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 739d2d4cc5..795ef727d0 1

[PATCH v2 05/14] target/arm: Update MSR access for PAN

For aarch64, there's a dedicated msr (imm, reg) insn. For aarch32, this is done via msr to cpsr; and writes from el0 are ignored. Since v8.0, the CPSR_RESERVED bits have been allocated. We are not yet implementing ARMv8.0-SSBS or ARMv8.4-DIT, so retain CPSR_RESERVED for now, so that the bits remai

[PATCH v2 10/14] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max

This includes enablement of ARMv8.1-PAN. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 4 target/arm/cpu64.c | 5 + 2 files changed, 9 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b0762a76c4..de733aceeb 100644 --- a/target

[PATCH v2 11/14] target/arm: Add ID_AA64MMFR2_EL1

Add definitions for all of the fields, up to ARMv8.5. Convert the existing RESERVED register to a full register. Query KVM for the value of the register for the host. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h| 17 + target/arm/helper.c

[PATCH v2 00/14] target/arm: Implement PAN, ATS1E1, UAO

Based-on: <20200201192916.31796-1-richard.hender...@linaro.org> ("[v6] target/arm: Implement ARMv8.1-VHE") Version 2 addresses review commentary, and also merges the 4 UAO patches into the PAN + ATS1E1 omnibus patch set. Changes: * Moved reginfo to file scope. * Rename arm_mmu_idx_is_stage1 t

[PATCH v2 03/14] target/arm: Add isar_feature tests for PAN + ATS1E1

Include definitions for all of the bits in ID_MMFR3. We already have a definition for ID_AA64MMFR1.PAN. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 29 + 1 file changed, 29 insertions(+) diff --git a/target/arm/cpu.h b/target/a

[PATCH v2 02/14] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled

To implement PAN, we will want to swap, for short periods of time, to a different privileged mmu_idx. In addition, we cannot do this with flushing alone, because the AT* instructions have both PAN and PAN-less versions. Add the ARMMMUIdx*_PAN constants where necessary next to the corresponding AR

[PATCH v2 01/14] target/arm: Add arm_mmu_idx_is_stage1_of_2

Use a common predicate for querying stage1-ness. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Rename from arm_mmu_idx_is_stage1 to arm_mmu_idx_is_stage1_of_2 --- target/arm/internals.h | 18 ++ target/arm/helper.c| 8 +++- 2 files changed

Re: [PATCH 2/4] target/arm: Update MSR access to UAO

On 12/6/19 10:30 AM, Peter Maydell wrote: >> +if (cpu_isar_feature(aa64_uao, cpu)) { >> +static const ARMCPRegInfo uao_reginfo[] = { >> +{ .name = "UAO", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, >> + .typ

Re: [PATCH 1/4] target/arm: Add ID_AA64MMFR2_EL1

On 12/6/19 10:19 AM, Peter Maydell wrote: >> @@ -549,6 +549,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures >> *ahcf) >>ARM64_SYS_REG(3, 0, 0, 7, 0)); >> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, >>

Re: [PATCH] tests: Silent various warnings with pseries

Hi Greg, On 2/1/20 11:46 PM, Greg Kurz wrote: > Some default features of the pseries machine are only available with > KVM. Warnings are printed when the pseries machine is used with another > accelerator: > > qemu-system-ppc64: warning: TCG doesn't support requested feature, > cap-ccf-assist=on

[PATCH] tests: Silent various warnings with pseries

Some default features of the pseries machine are only available with KVM. Warnings are printed when the pseries machine is used with another accelerator: qemu-system-ppc64: warning: TCG doesn't support requested feature, cap-ccf-assist=on qemu-system-ppc64: warning: Firmware Assisted Non-Maskable

Re: [PATCH] tests/acceptance: Count multiple Tux logos displayed on framebuffer

On 2/1/20 9:58 PM, Aleksandar Markovic wrote: > 21:48 Sub, 01.02.2020. Philippe Mathieu-Daudé > је написао/ла: >> >> Add a test that verifies that each core properly displays the Tux >> logo on the framebuffer device. >> > > Excellent test! > > Glad that Leon blog post wa

[Bug 1861562] Re: piix crashes on mips when using multiple cpus

ACPI GPE was added in: commit 5e3cb5347e9b650bdf8015da3c310b2669219294 Author: aliguori Date: Wed Feb 11 15:21:35 2009 + qemu: initialize hot add system / acpi gpe (Marcelo Tosatti) ACPI GPE support, used by PCI (and CPU) hotplug. From: Glauber Costa Signed-off-b

Re: [PATCH v2 11/12] .travis.yml: probe for number of available processors

Thanks Philippe. For reference, the two machine types in typical use in the Packet system can be referenced as follows: c1.large.arm - 96-core Cavium (Marvell) ThunderX c2.large.arm - 32-core Ampere eMag The Ampere data sheet from their OEM (Lenovo) is below. https://amperecomputing.com/wp-cont

Re: [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX

On 2/1/20 9:12 PM, Philippe Mathieu-Daudé wrote: > Hi Richard, > > On 1/8/20 4:45 AM, Richard Henderson wrote: >> The separate suffixed functions were used to construct >> some do_##insn function switched on mmu_idx. The interface >> is exactly identical to the *_mmuidx_ra functions. Replace >>

Re: [PATCH v4 03/20] hw/arm/allwinner-h3: add Clock Control Unit

Hi Philippe, On Sun, Jan 19, 2020 at 7:34 PM Philippe Mathieu-Daudé wrote: > On 1/19/20 1:50 AM, Niek Linnenbank wrote: > > The Clock Control Unit is responsible for clock signal generation, > > configuration and distribution in the Allwinner H3 System on Chip. > > This commit adds support for t

Re: [PATCH] tests/acceptance: Count multiple Tux logos displayed on framebuffer

21:48 Sub, 01.02.2020. Philippe Mathieu-Daudé је написао/ла: > > Add a test that verifies that each core properly displays the Tux > logo on the framebuffer device. > Excellent test! Glad that Leon blog post was the inspiration. I'll email him about this, if I find his address, one of my colegue

Re: [PATCH v4 01/20] hw/arm: add Allwinner H3 System-on-Chip

On 2/1/20 8:21 PM, Niek Linnenbank wrote: > Hi Philippe, > > I just got back from traveling and will start processing these and the > other comments soon. > > On Sun, Jan 19, 2020 at 7:01 PM Philippe Mathieu-Daudé > mailto:phi...@redhat.com>> wrote: > > On 1/19/20 1:50 AM, Niek Linnenbank wr

[PATCH] tests/acceptance: Count multiple Tux logos displayed on framebuffer

Add a test that verifies that each core properly displays the Tux logo on the framebuffer device. We simply follow the OpenCV "Template Matching with Multiple Objects" tutorial, replacing Lionel Messi by Tux: https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html When OpenCV and

Re: [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX

Hi Richard, On 1/8/20 4:45 AM, Richard Henderson wrote: > The separate suffixed functions were used to construct > some do_##insn function switched on mmu_idx. The interface > is exactly identical to the *_mmuidx_ra functions. Replace > them directly and remove the constructions. > > Cc: Aureli

[PATCH v6 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked

The value computed is fully boolean; using int8_t is odd. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fcee0a2dd4..4ffc09909d 100644 -

[PATCH v6 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps

From: Alex Bennée According to ARM ARM we should only trap from the EL1&0 regime. Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_help

[PATCH v6 33/41] target/arm: Update {fp,sve}_exception_el for VHE

When TGE+E2H are both set, CPACR_EL1 is ignored. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 53 - 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c inde

[PATCH v6 39/41] target/arm: Pass more cpu state to arm_excp_unmasked

Avoid redundant computation of cpu state by passing it in from the caller, which has already computed it for itself. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --g

[PATCH v6 29/41] target/arm: Add VHE timer register redirection and aliasing

Apart from the wholesale redirection that HCR_EL2.E2H performs for EL2, there's a separate redirection specific to the timers that happens for EL0 when running in the EL2&0 regime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 181

[PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v5: Flush all EL2 regimes with TLBI ALLE2 (pmm). --- target/arm/helper.c | 34 +++--- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f9be6b0

[PATCH v6 28/41] target/arm: Add VHE system register redirection and aliasing

Several of the EL1/0 registers are redirected to the EL2 version when in EL2 and HCR_EL2.E2H is set. Many of these registers have side effects. Link together the two ARMCPRegInfo structures after they have been properly instantiated. Install common dispatch routines to all of the relevant registe

[PATCH v6 38/41] target/arm: Move arm_excp_unmasked to cpu.c

This inline function has one user in cpu.c, and need not be exposed otherwise. Code movement only, with fixups for checkpatch. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 111 --- target/arm/cpu.c | 119 +++

[PATCH v6 23/41] target/arm: Update aa64_zva_access for EL2

The comment that we don't support EL2 is somewhat out of date. Update to include checks against HCR_EL2.TDZ. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 26 +- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/a

[PATCH v6 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE

For ARMv8.1, op1 == 5 is reserved for EL2 aliases of EL1 and EL0 registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 992ab2a15f..2aa

[PATCH v6 21/41] target/arm: Update arm_mmu_idx for VHE

Return the indexes for the EL2&0 regime when the appropriate bits are set within HCR_EL2. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v4: Consistently check E2H & TGE & ELUsingAArch32(EL2). Do not apply TGE at EL2. --- target/arm/helper.c | 11 +-- 1 file changed,

[PATCH v6 17/41] target/arm: Rearrange ARMMMUIdxBit

Define via macro expansion, so that renumbering of the base ARMMMUIdx symbols is automatically reflected in the bit definitions. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 39 +++ 1 fi

[PATCH v6 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2d97bf45e1..c80fb5fd43 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -672,6 +672,7 @@ static void aar

[PATCH v6 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt

The fall through organization of this function meant that we would raise an interrupt, then might overwrite that with another. Since interrupt prioritization is IMPLEMENTATION DEFINED, we can recognize these in any order we choose. Unify the code to raise the interrupt in a block at the end. Revi

[PATCH v6 26/41] target/arm: Update timer access for VHE

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 102 +++- 1 file changed, 81 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 996865a3a2..992ab2a15f 100644 --- a/target/arm/hel

[PATCH v6 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits

We are about to expand the number of mmuidx to 10, and so need 4 bits. For the benefit of reading the number out of -d exec, align it to the penultimate nibble. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 16 1 file changed, 8 insertions(+),

[PATCH v6 35/41] target/arm: Update get_a64_user_mem_index for VHE

The EL2&0 translation regime is affected by Load Register (unpriv). The code structure used here will facilitate later changes in this area for implementing UAO and NV. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 9 target/arm/translat

[PATCH v6 25/41] target/arm: Add the hypervisor virtual counter

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 11 + target/arm/cpu.c | 3 ++- target/arm/helper.c | 56 4 files changed, 65 insertions(+), 6 deletions(-) diff --git a/t

[PATCH v6 19/41] target/arm: Reorganize ARMMMUIdx

Prepare for, but do not yet implement, the EL2&0 regime. This involves adding the new MMUIdx enumerators and adjusting some of the MMUIdx related predicates to match. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 134

[PATCH v6 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE

When VHE is enabled, the exception level below EL2 is not EL1, but EL0, and so to identify the entry vector offset for exceptions targeting EL2 we need to look at the width of EL0, not of EL1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++-- 1 f

[PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime

Since we only support a single ASID, flush the tlb when it changes. Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between the two TTBR* registers for the location of the ASID. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 22 ++

[PATCH v6 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2

The EL1&0 regime is the only one that uses 2-stage translation. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 +-- target/arm/internals.h | 2 +- target/arm/helper.c| 57 -- target/arm/translate-a64

[PATCH v6 32/41] target/arm: Update arm_phys_excp_target_el for TGE

The TGE bit routes all asynchronous exceptions to EL2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e2278b5aa..c239711641 100644 --- a/target/arm/hel

[PATCH v6 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*

This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v5: Adjust || indentation (ajb) --- target/arm/cpu.h | 4

[PATCH v6 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2

This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/interna

[PATCH v6 20/41] target/arm: Add regime_has_2_ranges

Create a predicate to indicate whether the regime has both positive and negative addresses. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/internals.h | 18 ++ target/arm/helper.c| 23 ++- target/arm/translate-a64.c | 3

[PATCH v6 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3

This is part of a reorganization to the set of mmu_idx. The EL3 regime only has a single stage translation, and is always secure. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c| 14 +++--

[PATCH v6 08/41] target/arm: Simplify tlb_force_broadcast alternatives

Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 52 + 1 file changed, 24 insertion

[PATCH v6 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*

This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the EL1&0 regime. The ultimate goal is -- Non-secure regimes: ARMMMUIdx_E10_0, ARMMMUIdx_E20_0, ARMMMUIdx_E10_1, ARMMMUIdx_E2, ARMMMUIdx_E20_2, -- Secure regimes: ARMMMUIdx_SE10_0

[PATCH v6 24/41] target/arm: Update ctr_el0_access for EL2

Update to include checks against HCR_EL2.TID2. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 26 +- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e41bece6b5..72b336e3b5

[PATCH v6 22/41] target/arm: Update arm_sctlr for VHE

Use the correct sctlr for EL2&0 regime. Due to header ordering, and where arm_mmu_idx_el is declared, we need to move the function out of line. Use the function in many more places in order to select the correct control. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v3: Use arm

[PATCH v6 06/41] target/arm: Split out vae1_tlbmask

No functional change, but unify code sequences. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 32 +--- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/arm/helper.c b/tar

[PATCH v6 03/41] target/arm: Add CONTEXTIDR_EL2

Not all of the breakpoint types are supported, but those that only examine contextidr are extended to support the new register. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v6: Move reginfo to file scope. --- target/arm/debug_helper.c | 50 +-

[PATCH v6 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01]

This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the Secure EL1&0 regime. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- t

[PATCH v6 07/41] target/arm: Split out alle1_tlbmask

No functional change, but unify code sequences. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v5: Do not confuse things by prefixing "vm". --- target/arm/helper.c | 86 + 1 file changed, 24 insertio

[PATCH v6 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions

Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants. Keep the definitions short by referencing previous symbols. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 16 1 file changed, 8 insertions(+), 8 deletions(-) di

[PATCH v6 04/41] target/arm: Add TTBR1_EL2

At the same time, add writefn to TTBR0_EL2 and TCR_EL2. A later patch will update any ASID therein. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v5: Do not update TCR_EL2 yet; delay that til we handle ASIDs. --- target/arm/helper.c | 13 - 1 file changed, 12 inserti

[PATCH v6 00/41] target/arm: Implement ARMv8.1-VHE

Version 6 moves vhe_reginfo[] to file scope, and one tweak to the vhe register access masking that Peter asked for. All patches now have reviews. r~ Alex Bennée (1): target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson (40): target/arm: Define isar_feature_aa64_vh t

[PATCH v6 05/41] target/arm: Update CNTVCT_EL0 for VHE

The virtual offset may be 0 depending on EL, E2H and TGE. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 40 +--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c ind

[PATCH v6 01/41] target/arm: Define isar_feature_aa64_vh

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 608fcbd0b7..2a53f5d09b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3685,6 +3685,11 @@ static inline bool

[PATCH v6 02/41] target/arm: Enable HCR_E2H for VHE

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h| 7 --- target/arm/helper.c | 6 +- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a53f5d09b..0e68704a90 100644 --- a/target/arm/cpu.h +++ b/targe

[PATCH v6 15/41] target/arm: Recover 4 bits from TBFLAGs

We had completely run out of TBFLAG bits. Split A- and M-profile bits into two overlapping buckets. This results in 4 free bits. We used to initialize all of the a32 and m32 fields in DisasContext by assignment, in arm_tr_init_disas_context. Now we only initialize either the a32 or m32 by assignm

Re: [PATCH v4 01/20] hw/arm: add Allwinner H3 System-on-Chip

Hi Philippe, I just got back from traveling and will start processing these and the other comments soon. On Sun, Jan 19, 2020 at 7:01 PM Philippe Mathieu-Daudé wrote: > On 1/19/20 1:50 AM, Niek Linnenbank wrote: > > The Allwinner H3 is a System on Chip containing four ARM Cortex A7 > > processo

Re: VW ELF loader

On 01/02/20 14:39, Alexey Kardashevskiy wrote: > QEMU needs to load GRUB from the disk. The current workaround is to read > it from qcow2, save in a file and then call load_elf(). Not nice. > > 2 problems with that. > > 1. when load_elf calls address_space_write() - I need to know where and > how

Re: [PATCH for-5.0 3/4] Remove the core bluetooth code

On 01/02/2020 19.53, Philippe Mathieu-Daudé wrote: > On Sat, Feb 1, 2020 at 7:51 PM Thomas Huth wrote: >> On 01/02/2020 17.09, Philippe Mathieu-Daudé wrote: >>> On 11/20/19 10:10 AM, Thomas Huth wrote: It's been deprecated since QEMU v3.1. We've explicitly asked in the deprecation messag

Re: [PATCH for-5.0 3/4] Remove the core bluetooth code

On Sat, Feb 1, 2020 at 7:51 PM Thomas Huth wrote: > On 01/02/2020 17.09, Philippe Mathieu-Daudé wrote: > > On 11/20/19 10:10 AM, Thomas Huth wrote: > >> It's been deprecated since QEMU v3.1. We've explicitly asked in the > >> deprecation message that people should speak up on qemu-devel in case >

Re: [PATCH for-5.0 3/4] Remove the core bluetooth code

On 01/02/2020 17.09, Philippe Mathieu-Daudé wrote: > On 11/20/19 10:10 AM, Thomas Huth wrote: >> It's been deprecated since QEMU v3.1. We've explicitly asked in the >> deprecation message that people should speak up on qemu-devel in case >> they are still actively using the bluetooth part of QEMU,

Re: [PATCH] audio/dsound: fix invalid parameters error

On Mon, Jan 27, 2020 at 02:46:58AM +0100, Zoltán Kővágó wrote: > On 2020-01-18 07:30, Philippe Mathieu-Daudé wrote: > > On 1/17/20 7:26 PM, KJ Liew wrote: > > > QEMU Windows has broken dsound backend since the rewrite of audio API in > > > version 4.2.0. Both playback and capture buffers failed to

[PATCH] Remove support for CLOCK_MONOTONIC not being defined

Some older parts of QEMU's codebase assume that CLOCK_MONOTONIC might not be defined by the host OS, and have workarounds to deal with this. However, more recently (notably in commit 50290c002c045280f8d for qemu-img in mid-2019, but also much earlier in 2011 in commit 22795174a37e0 for ui/spice-dis

[PATCH] ui/cocoa: Drop workarounds for pre-10.12 OSX

Our official OSX support policy covers the last two released versions. Currently that is 10.14 and 10.15. We also may work on older versions, but don't guarantee it. In commit 50290c002c045280f8d in mid-2019 we introduced some uses of CLOCK_MONOTONIC which incidentally broke compilation for pre-1

[Bug 1861562] [NEW] piix crashes on mips when using multiple cpus

Public bug reported: Crash occurred while testing commit 330edfcc84a7: $ qemu-system-mips64el -cpu I6400 -append "clocksource=GIC console=ttyS0" -smp 8 -kernel vmlinux Linux version 4.7.0-rc1 (phil@x1) (gcc version 6.3.0 20170516 (Debian 6.3.0-18) ) #1 SMP Sat Feb 1 13:15:19 UTC 2020 earlycon:

[Bug 1835865] Re: piix crashes on mips when accessing acpi-pci-hotplug

As this is an ACPI bug, adding the acpi tag. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1835865 Title: piix crashes on mips when accessing acpi-pci-hotplug Status in QEMU: New Bug descriptio

[Bug 1861551] Re: Errors while compiling source

Hi. The CLOCK_MONOTONIC facility was added in OSX 10.12; the version of OSX you're using is too old to build QEMU on, I'm afraid. QEMU's policy is to support the last two releases of OSX, so at the moment that's 10.14 and 10.15. Compiling on older versions might work, but it also might not, as you'

Re: [PATCH for-5.0 3/4] Remove the core bluetooth code

On 11/20/19 10:10 AM, Thomas Huth wrote: > It's been deprecated since QEMU v3.1. We've explicitly asked in the > deprecation message that people should speak up on qemu-devel in case > they are still actively using the bluetooth part of QEMU, but nobody > ever replied that they are really still usi

Re: [Qemu-devel] [PATCH v11] ssh: switch from libssh2 to libssh

On Thu, Jun 20, 2019 at 10:36 PM Philippe Mathieu-Daudé wrote: > On 6/20/19 10:08 PM, Pino Toscano wrote: > > Rewrite the implementation of the ssh block driver to use libssh instead > > of libssh2. The libssh library has various advantages over libssh2: > > - easier API for authentication (for

VW ELF loader

Hi! In my effort to "kill SLOF" (the PPC pseries guest firmware), I proceeded to the stage when QEMU needs to load GRUB from the disk. The current workaround is to read it from qcow2, save in a file and then call load_elf(). Not nice. 2 problems with that. 1. when load_elf calls address_space

Re: [PATCH rc4 19/29] target/avr: Add section about AVR into QEMU documentation

On Friday, January 31, 2020, Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > Explains basic ways of using AVR target in QEMU. > > Signed-off-by: Michael Rolnik > Message-Id: <20200118191416.19934-16-mrol...@gmail.com> > Signed-off-by: Richard Henderson > [

[PATCH 3/4] linux-user: fix TARGET_NSIG and _NSIG uses

Valid signal numbers are between 1 (SIGHUP) and SIGRTMAX. System includes define _NSIG to SIGRTMAX + 1, but QEMU (like kernel) defines TARGET_NSIG to TARGET_SIGRTMAX. Fix all the checks involving the signal range. Signed-off-by: Laurent Vivier --- linux-user/signal.c | 51 +

[PATCH 2/4] linux-user: cleanup signal.c

No functionnal changes. Prepare the field for future fixes. Remove memset(.., 0, ...) that is useless on a static array Signed-off-by: Laurent Vivier --- linux-user/signal.c | 37 ++--- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/linux-user/si

[PATCH 0/4] linux-user: fix use of SIGRTMIN

This series fixes the problem of the first real-time signals already in use by the glibc that are not available for the target glibc. Instead of reverting the first and last real-time signals we rely on the value provided by the glibc (SIGRTMIN) to know the first available signal and we map all th

[PATCH 1/4] linux-user: add missing TARGET_SIGRTMIN for hppa

This signal is defined for all other targets and we will need it later Signed-off-by: Laurent Vivier --- linux-user/hppa/target_signal.h | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/hppa/target_signal.h b/linux-user/hppa/target_signal.h index ba159ff8d006..c2a0102ed73d 100644 -

Re: [PATCH rc4 07/29] target/avr: Add instruction helpers

On Friday, January 31, 2020, Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > Add helpers for instructions that need to interact with QEMU. Also, > add stubs for unimplemented instructions. Instructions SPM and WDR > are left unimplemented because they requir

[PATCH 4/4] linux-user: fix use of SIGRTMIN

Some RT signals can be in use by glibc, it's why SIGRTMIN (34) is generally greater than __SIGRTMIN (32). So SIGRTMIN cannot be mapped to TARGET_SIGRTMIN. Instead of swapping only SIGRTMIN and SIGRTMAX, map all the range [TARGET_SIGRTMIN ... TARGET_SIGRTMAX - X] to [__SIGRTMIN + X ... SIGRT

[Bug 1861551] [NEW] Errors while compiling source

Public bug reported: OS type: Mac OS X 10.11.6 List of errors: qemu-io-cmds.c:837:5: warning: implicit declaration of function 'clock_gettime' is invalid in C99 [-Wimplicit-function-declaration] clock_gettime(CLOCK_MONOTONIC, &t1); ^ qemu-io-cmds.c:837:19: error: use of undeclared identif