On Mon, Feb 10, 2020 at 05:05:19PM +0800, Zha Bin wrote:
> From: Liu Jiang
>
> Create a generic irq domain for all architectures which
> supports virtio-mmio. The device offering VIRTIO_F_MMIO_MSI
> feature bit can use this irq domain.
>
> Signed-off-by: Liu Jiang
> Co-developed-by: Zha Bin
>
Cc'ing Eduardo & Markus.
On 2/12/20 7:44 AM, Chenqun (kuhn) wrote:
-Original Message-
From: Philippe Mathieu-Daudé [mailto:phi...@redhat.com]
Sent: Wednesday, February 12, 2020 2:16 PM
To: Chenqun (kuhn) ; qemu-
de...@nongnu.org; i.mitsya...@gmail.com; peter.mayd...@linaro.org
Cc: qemu-t
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 4:17 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 15/25] intel_iommu: process pasid cache invalidation
>
> On Wed, Jan 29, 2020 at 04:16:46AM -0800, Liu, Yi L wrote:
> > From: Liu Yi L
> >
> > This patch adds PASID cache invalidation handling.
On Wed, Feb 12, 2020 at 11:54:53AM +0800, Liu, Jing2 wrote:
>
> On 2/11/2020 3:40 PM, Jason Wang wrote:
>
>
> On 2020/2/11 下午2:02, Liu, Jing2 wrote:
>
>
>
> On 2/11/2020 12:02 PM, Jason Wang wrote:
>
>
> On 2020/2/11 上午11:35, Liu, Jing2 wrote:
>
>
>
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 4:16 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 14/25] intel_iommu: add virtual command capability
> support
>
> On Wed, Jan 29, 2020 at 04:16:45AM -0800, Liu, Yi L wrote:
> > From: Liu Yi L
> >
> > This patch adds virtual command support to
On Wed, Feb 12, 2020 at 10:58:13AM +0800, Liu, Jing2 wrote:
>
> On 2/11/2020 7:19 PM, Michael S. Tsirkin wrote:
> > On Mon, Feb 10, 2020 at 05:05:18PM +0800, Zha Bin wrote:
> > > From: Liu Jiang
> > >
> > > Common functionality is refactored into virtio_mmio_common.h
> > > in order to MSI suppor
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 3:44 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 13/25] intel_iommu: modify x-scalable-mode to be string
> option
>
> On Wed, Jan 29, 2020 at 04:16:44AM -0800, Liu, Yi L wrote:
> > From: Liu Yi L
> >
> > Intel VT-d 3.0 introduces scalable mode
Hi,
On Mon, Feb 10, 2020 at 10:52:55PM +, Richard W.M. Jones wrote:
> But anyway ... could a flag indicating that the whole image is sparse
> be useful, either as well as NBD_INIT_SPARSE or instead of it? You
> could use it to avoid an initial disk trim, which is something that
> mke2fs does:
On 2020/2/12 0:11, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
+static int vs(CPURISCVState *env, int csrno)
+{
+return 0;
+}
This should at least be testing RVV, a-la smode().
Testing RVV is ok.
I'm not quite understand "a -1a smode()" here. Could you give more
de
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 3:32 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 12/25] vfio/common: add pasid_alloc/free support
>
> On Wed, Jan 29, 2020 at 04:16:43AM -0800, Liu, Yi L wrote:
> > From: Liu Yi L
> >
> > This patch adds VFIO pasid alloc/free support to allow
On 2020/2/11 23:56, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
+if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
+error_setg(errp,
+ "Vector extension implementation only supports VLEN "
+ "in
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 3:30 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 11/25] vfio: get stage-1 pasid formats from Kernel
>
> On Wed, Jan 29, 2020 at 04:16:42AM -0800, Liu, Yi L wrote:
> > From: Liu Yi L
> >
> > VFIO checks IOMMU UAPI version when it finds Kernel s
On 2020/2/11 23:53, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
bas
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 3:08 AM
> Subject: Re: [RFC v3 09/25] vfio: check VFIO_TYPE1_NESTING_IOMMU support
>
> On Wed, Jan 29, 2020 at 04:16:40AM -0800, Liu, Yi L wrote:
> > From: Liu Yi L
> >
> > VFIO needs to check VFIO_TYPE1_NESTING_IOMMU support with Kernel
> >
Hi Peter,
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 12:59 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 03/25] hw/iommu: introduce IOMMUContext
>
> On Fri, Jan 31, 2020 at 11:42:13AM +, Liu, Yi L wrote:
> > > I'm not very clear on the relationship betwen an IOMMUContext and a
> > >
On 2/11/20 6:37 PM, Peter Maydell wrote:
The LC bit in the PMCR_EL0 register is supposed to be:
* read/write
* RES1 on an AArch64-only implementation
* an architecturally UNKNOWN value on reset
(and use of LC==0 by software is deprecated).
We were implementing it incorrectly as read-only a
Public bug reported:
Hello,
This is on Arch-linux(latest) and the qemu 4.2.0 version made from git clone
https://github.com/spheenik/qemu.git
with:
./configure --prefix=/opt/qemu-test --python=/usr/bin/python2
--target-list=x86_64-softmmu
--audio-drv-list=pa --disable-werror
added to the buil
On 2/11/20 6:37 PM, Peter Maydell wrote:
The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'.
Correct our #define of PMCRDP and add the missing PMCRX.
We do have the correct behaviour for handling the DP bit being
set, so this fixes a guest-visible bug.
Fixes: 033614c47de
Revi
On 2/11/20 6:37 PM, Peter Maydell wrote:
Add the 64-bit version of the "is this a v8.1 PMUv3?"
ID register check function, and the _any_ version that
checks for either AArch32 or AArch64 support. We'll use
this in a later commit.
We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1,
but
On 2/11/20 6:37 PM, Peter Maydell wrote:
We already define FIELD macros for ID_DFR0, so use them in the
one place where we're doing direct bit value manipulation.
Signed-off-by: Peter Maydell
---
We have lots of this non-FIELD style in the code, of course;
I change this one purely because it ot
>-Original Message-
>From: Philippe Mathieu-Daudé [mailto:phi...@redhat.com]
>Sent: Wednesday, February 12, 2020 2:16 PM
>To: Chenqun (kuhn) ; qemu-
>de...@nongnu.org; i.mitsya...@gmail.com; peter.mayd...@linaro.org
>Cc: qemu-triv...@nongnu.org; Zhanghailiang
>
>Subject: Re: [PATCH] hw/char
On 2/11/20 7:34 PM, Richard Henderson wrote:
On 2/11/20 9:37 AM, Peter Maydell wrote:
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
-assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
-assert(extract32(cpu->
On 2/11/20 6:37 PM, Peter Maydell wrote:
Pull the code that defines the various PMU registers out
into its own function, matching the pattern we have
already for the debug registers.
Apart from one style fix to a multi-line comment, this
is purely movement of code with no changes to it.
Signed-
On 2/5/20 10:05 PM, Gavin Shan wrote:
This allows to inject SError interrupt, which will be used on receiving
QMP/HMP "nmi" command in next patch.
Signed-off-by: Gavin Shan
---
target/arm/cpu.c| 11 +++
target/arm/cpu.h| 12 +---
target/arm/helper.c | 4
3 fil
On 2/9/20 11:42 PM, LIU Zhiwei wrote:
> +/*
> + * As simd_desc supports at most 256 bytes, and in this implementation,
> + * the max vector group length is 2048 bytes. So split it into two parts.
> + *
> + * The first part is floor(maxsz, 64), encoded in maxsz of simd_desc.
> + * The second part is
On 2/10/20 1:01 PM, Peter Maydell wrote:
The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits:
* the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is
8 or 16 bits
* the VMID field in VTTBR_EL2 is extended to 16 bits
* VTCR_EL2.VS lets the guest specify whet
On 2/11/20 6:37 PM, Peter Maydell wrote:
Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv",
define and use an any_predinv isar_feature test function.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 5 +
target/arm/helper.c | 9 +
2 files changed, 6
On 2/11/20 6:37 PM, Peter Maydell wrote:
Our current usage of the isar_feature feature tests almost always
uses an _aa32_ test when the code path is known to be AArch32
specific and an _aa64_ test when the code path is known to be
AArch64 specific. There is just one exception: in the vfp_set_fpsc
On 2/11/20 6:37 PM, Peter Maydell wrote:
Enforce a convention that an isar_feature function that tests a
32-bit ID register always has _aa32_ in its name, and one that
tests a 64-bit ID register always has _aa64_ in its name.
We already follow this except for three cases: thumb_div,
arm_div and j
On 2/12/20 4:36 AM, kuhn.chen...@huawei.com wrote:
From: Chen Qun
It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-properties",
"arguments":{"typename":"exynos4210.uart"}}'
ASAN shows memory leak stack:
#1 0xfffd896d71cb in g_malloc0 (/lib6
On 2/12/20 3:51 AM, Richard Henderson wrote:
Now that we can pass 7 parameters, do not encode register
operands within simd_data.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 45 +++
target/arm/sve_helper.c| 157 ++---
target
On 2/12/20 3:51 AM, Richard Henderson wrote:
Extend the vector generator infrastructure to handle
5 vector arguments.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec.h | 7 +++
tcg/tcg-op-gvec.c | 32
2 files changed, 39 insertions(
On Mon, Feb 03, 2020 at 02:29:38PM +1100, Alexey Kardashevskiy wrote:
> At the moment we enforce 64bit mode on a CPU when reset. This does not
> make difference as SLOF or Linux set the desired mode straight away.
> However if we ever boot something other than these two,
> this might not work as, f
> -Original Message-
> From: Zhanghailiang
> Sent: Wednesday, February 12, 2020 11:18 AM
> To: Dr. David Alan Gilbert ; Daniel Cho
> ; Zhang, Chen
> Cc: qemu-devel@nongnu.org
> Subject: RE: The issues about architecture of the COLO checkpoint
>
> Hi,
>
> Thank you Dave,
>
> I'll rep
On Sun, Feb 09, 2020 at 10:55:51PM -0600, Shivaprasad G Bhat wrote:
> The patchset attempts to implement the virtual NVDIMM for pseries.
>
> PAPR semantics is such that each NVDIMM device is comprising of
> multiple SCM(Storage Class Memory) blocks. The hypervisor is expected
> to prepare the FDT
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1853826
Title:
ELF loader
Public bug reported:
Bug Description:
Run "java -version" in guest VM, java may stuck for a long time (several hours)
and then recover.
Steps to reproduce:
1. Launch VM by attached simple script: launch.sh
2. Execute "java -version" and then print "date" in a loop
while :
do
/home/
On 2/11/2020 3:40 PM, Jason Wang wrote:
On 2020/2/11 下午2:02, Liu, Jing2 wrote:
On 2/11/2020 12:02 PM, Jason Wang wrote:
On 2020/2/11 上午11:35, Liu, Jing2 wrote:
On 2/11/2020 11:17 AM, Jason Wang wrote:
On 2020/2/10 下午5:05, Zha Bin wrote:
From: Liu Jiang
Userspace VMMs (e.g. Qemu micro
On 2020/2/11 下午7:33, Michael S. Tsirkin wrote:
On Mon, Feb 10, 2020 at 05:05:17PM +0800, Zha Bin wrote:
From: Liu Jiang
The standard virtio-mmio devices use notification register to signal
backend. This will cause vmexits and slow down the performance when we
passthrough the virtio-mmio devic
From: Chen Qun
It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-properties",
"arguments":{"typename":"exynos4210.uart"}}'
ASAN shows memory leak stack:
#1 0xfffd896d71cb in g_malloc0 (/lib64/libglib-2.0.so.0+0x571cb)
#2 0xaaad270beee3 in tim
Hi,
Thank you Dave,
I'll reply here directly.
-Original Message-
From: Dr. David Alan Gilbert [mailto:dgilb...@redhat.com]
Sent: Wednesday, February 12, 2020 1:48 AM
To: Daniel Cho ; chen.zh...@intel.com; Zhanghailiang
Cc: qemu-devel@nongnu.org
Subject: Re: The issues about architectu
On 2/11/2020 7:19 PM, Michael S. Tsirkin wrote:
On Mon, Feb 10, 2020 at 05:05:18PM +0800, Zha Bin wrote:
From: Liu Jiang
Common functionality is refactored into virtio_mmio_common.h
in order to MSI support in later patch set.
Signed-off-by: Liu Jiang
Co-developed-by: Zha Bin
Signed-off-by
On 2020/2/11 下午4:58, Zhang, Chen wrote:
-Original Message-
From: Jason Wang
Sent: Monday, January 20, 2020 10:57 AM
To: Zhang, Chen; Paolo Bonzini
; Philippe Mathieu-Daudé;
qemu-dev
Cc: Zhang Chen
Subject: Re: [PATCH V4 0/5] Introduce Advanced Watch Dog module
On 2020/1/19 下午5:10, Zha
Now that we can pass 7 parameters, do not encode register
operands within simd_data.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 45 +++
target/arm/sve_helper.c| 157 ++---
target/arm/translate-sve.c | 68 ++--
3 fil
Based-on: <1580942510-2820-1-git-send-email-tsimp...@quicinc.com>
These functions had been passing arguments by regno,
encoded into simd_data, because we couldn't pass 7 args.
r~
Richard Henderson (2):
tcg: Add tcg_gen_gvec_5_ptr
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
incl
Extend the vector generator infrastructure to handle
5 vector arguments.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec.h | 7 +++
tcg/tcg-op-gvec.c | 32
2 files changed, 39 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/inclu
The NBD URI specification [1] states that only one leading slash at
the beginning of the URI path component is stripped, not all such
slashes. This becomes important to a patch I just proposed to nbdkit
[2], which would allow the exportname to select a file embedded within
an ext2 image: ext2fs de
On Tue, 11 Feb 2020 18:55:16 +0100
Paolo Bonzini wrote:
> Even though MSR_IA32_UCODE_REV has been available long before Linux 5.6,
> which added it to the emulated MSR list, a bug caused the microcode
> version to revert to 0x1 on INIT. As a result, processors other
> than the bootstrap
On Wed, Jan 29, 2020 at 04:16:47AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> This patch adds a PASID cache management infrastructure based on
> new added structure VTDPASIDAddressSpace, which is used to track
> the PASID usage and future PASID tagged DMA address translation
> support in vIOMMU
On Fri, 7 Feb 2020 at 08:20, Andrew Jones wrote:
>
> On Thu, Feb 06, 2020 at 09:48:05PM +, Beata Michalska wrote:
> > On Wed, 5 Feb 2020 at 16:57, Andrew Jones wrote:
> > >
> > > On Wed, Jan 29, 2020 at 08:24:41PM +, Beata Michalska wrote:
> > > > On ARMv7 & ARMv8 some load/store instruct
On 1/30/20 1:38 PM, Stefan Hajnoczi wrote:
> From: Salvador Fandino
>
> NULL is a valid log filename used to indicate we want to use stderr
> but qemu_set_log_filename (which is called by bsd-user/main.c) was not
> handling it correctly.
>
> That also made redundant a couple of NULL checks in ca
Peter Maydell writes:
> On Tue, 11 Feb 2020 at 17:36, Alex Bennée wrote:
>>
>> Through a mechanism I don't quite yet understand we can find ourselves
>> with a left over RCU thread when we exit group. This is a racy failure
>> that occurs for example with:
>>
>> alpha-linux-user running test
On Wed, Jan 29, 2020 at 04:16:45AM -0800, Liu, Yi L wrote:
> +/*
> + * The basic idea is to let hypervisor to set a range for available
> + * PASIDs for VMs. One of the reasons is PASID #0 is reserved by
> + * RID_PASID usage. We have no idea how many reserved PASIDs in future,
> + * so here just a
Hi
On Tue, Feb 11, 2020 at 4:24 PM Boeuf, Sebastien
wrote:
>
> From c073d528b8cd7082832fd1825dc33dd65b305aa2 Mon Sep 17 00:00:00 2001
> From: Sebastien Boeuf
> Date: Tue, 11 Feb 2020 16:01:22 +0100
> Subject: [PATCH] docs: Update vhost-user spec regarding backend program
> conventions
>
> The v
So far we've been converting docs to Sphinx and assigning them
to manuals according to the division originally set out by
Paolo on the wiki: https://wiki.qemu.org/Features/Documentation
* QEMU User-mode Emulation User's Guide (docs/user)
* QEMU System Emulation User's Guide (docs/system)
* QEMU
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Darren Kenny
---
configure | 39 +++
1 file changed, 39 insertions(+)
diff --git a/configure b/configure
index 115dc38085..bd873177ad 100755
--- a
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
---
tests/qtest/fuzz/Makefile.include | 2 +
tests/qtest/fuzz/qos_fuzz.c | 234 ++
tests/qtest/fuzz/qos_fuzz.h | 33 +
3 files changed, 269 insertions(+)
create mode 100644 tests/qtest/f
fork() is a simple way to ensure that state does not leak in between
fuzzing runs. Unfortunately, the fuzzer mutation engine relies on
bitmaps which contain coverage information for each fuzzing run, and
these bitmaps should be copied from the child to the parent(where the
mutation occurs). These b
Ram blocks were marked MADV_DONTFORK breaking fuzzing-tests which
execute each test-input in a forked process.
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Darren Kenny
---
exec.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/ex
The names i2c_send and i2c_recv collide with functions defined in
hw/i2c/core.c. This causes an error when linking against libqos and
softmmu simultaneously (for example when using qtest inproc). Rename the
libqos functions to avoid this.
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajno
The virtio-net fuzz target feeds inputs to all three virtio-net
virtqueues, and uses forking to avoid leaking state between fuzz runs.
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
---
tests/qtest/fuzz/Makefile.include | 1 +
tests/qtest/fuzz/virtio_net_fuzz.c | 198 +
These three targets should simply fuzz reads/writes to a couple ioports,
but they mostly serve as examples of different ways to write targets.
They demonstrate using qtest and qos for fuzzing, as well as using
rebooting and forking to reset state, or not resetting it at all.
Signed-off-by: Alexand
When using qtest "in-process" communication, qtest_sendf directly calls
a function in the server (qtest.c). Previously, bufwrite used
socket_send, which bypasses the TransportOps enabling the call into
qtest.c. This change replaces the socket_send calls with ops->send,
maintaining the benefits of t
The virtio-scsi fuzz target sets up and fuzzes the available virtio-scsi
queues. After an element is placed on a queue, the fuzzer can select
whether to perform a kick, or continue adding elements.
Signed-off-by: Alexander Bulekov
---
tests/qtest/fuzz/Makefile.include | 1 +
tests/qtest/fuzz
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Darren Kenny
---
docs/devel/fuzzing.txt | 116 +
1 file changed, 116 insertions(+)
create mode 100644 docs/devel/fuzzing.txt
diff --git a/docs/devel/fuzzing.txt b/docs/devel/fuzz
This makes it simple to swap the transport functions for qtest commands
to and from the qtest client. For example, now it is possible to
directly pass qtest commands to a server handler that exists within the
same process, without the standard way of writing to a file descriptor.
Signed-off-by: Al
Signed-off-by: Alexander Bulekov
Reviewed-by: Darren Kenny
Reviewed-by: Stefan Hajnoczi
---
Makefile| 15 ++-
Makefile.target | 16
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index f0e1a2fc1d..36ca26f0f5 100644
--- a/M
The handler allows a qtest client to send commands to the server by
directly calling a function, rather than using a file/CharBackend
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Darren Kenny
---
include/sysemu/qtest.h | 1 +
qtest.c| 13 +
tests/fuzz/fuzz.c serves as the entry point for the virtual-device
fuzzer. Namely, libfuzzer invokes the LLVMFuzzerInitialize and
LLVMFuzzerTestOneInput functions, both of which are defined in this
file. This change adds a "FuzzTarget" struct, along with the
fuzz_add_target function, which should b
The moved functions are not specific to qos-test and might be useful
elsewhere. For example the virtual-device fuzzer makes use of them for
qos-assisted fuzz-targets.
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Darren Kenny
---
qtest_server_send is a function pointer specifying the handler used to
transmit data to the qtest client. In the standard configuration, this
calls the CharBackend handler, but now it is possible for other types of
handlers, e.g direct-function calls if the qtest client and server
exist within the
The virtual-device fuzzer must initialize QOM, prior to running
vl:qemu_init, so that it can use the qos_graph to identify the arguments
required to initialize a guest for libqos-assisted fuzzing. This change
prevents errors when vl:qemu_init tries to (re)initialize the previously
initialized QOM m
The qtest-based fuzzer makes use of forking to reset-state between
tests. Keep the callback enabled, so the call_rcu thread gets created
within the child process.
Signed-off-by: Alexander Bulekov
Reviewed-by: Darren Kenny
Acked-by: Stefan Hajnoczi
---
softmmu/vl.c | 12 +++-
1 file cha
A program might rely on functions implemented in vl.c, but implement its
own main(). By placing main into a separate source file, there are no
complaints about duplicate main()s when linking against vl.o. For
example, the virtual-device fuzzer uses a main() provided by libfuzzer,
and needs to perfo
Most qos-related objects were specified in the qos-test-obj-y variable.
qos-test-obj-y also included qos-test.o which defines a main().
This made it difficult to repurpose qos-test-obj-y to link anything
beside tests/qos-test against libqos. This change separates objects that
are libqos-specific an
Signed-off-by: Alexander Bulekov
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Darren Kenny
---
include/qemu/module.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/qemu/module.h b/include/qemu/module.h
index 65ba596e46..684753d808 100644
--- a/include/qemu/module.h
Signed-off-by: Alexander Bulekov
---
Makefile.objs | 2 --
Makefile.target | 1 +
softmmu/Makefile.objs | 2 ++
vl.c => softmmu/vl.c | 0
4 files changed, 3 insertions(+), 2 deletions(-)
create mode 100644 softmmu/Makefile.objs
rename vl.c => softmmu/vl.c (100%)
diff --git a/Mak
524b4c2c5c moves vl.c into softmmu/ , breaking the checkpatch
top-of-kernel-tree check. Replace with checks for softmmu and linux-user
Signed-off-by: Alexander Bulekov
---
scripts/checkpatch.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/ch
Hello,
This series adds a framework for coverage-guided fuzzing of
virtual-devices. Fuzzing targets are based on qtest and can make use of
the libqos abstractions.
V9:
* Fix bug in the virtio-scsi fuzzer. Virtqueues were being kicked only
if free_head != 0 (which it never was).
* Move vl.c a
On Wed, Jan 29, 2020 at 04:16:46AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> This patch adds PASID cache invalidation handling. When guest enabled
> PASID usages (e.g. SVA), guest software should issue a proper PASID
> cache invalidation when caching-mode is exposed. This patch only adds
> the
On Wed, Jan 29, 2020 at 04:16:45AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> This patch adds virtual command support to Intel vIOMMU per
> Intel VT-d 3.1 spec. And adds two virtual commands: allocate
> pasid and free pasid.
>
> Cc: Kevin Tian
> Cc: Jacob Pan
> Cc: Peter Xu
> Cc: Yi Sun
>
On Wed, Jan 29, 2020 at 12:56:53PM +0100, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> Reviewed-by: Dr. David Alan Gilbert
> ---
> configure | 30 ++
> 1 file changed, 30 insertions(+)
This is adding a new 3rd party library to QEMU that we've not previously
* Juan Quintela (quint...@redhat.com) wrote:
> Signed-off-by: Juan Quintela
> ---
> hw/core/qdev-properties.c| 2 +-
> migration/Makefile.objs | 1 +
> migration/migration.c| 9 +
> migration/migration.h| 1 +
> migration/multifd-zstd.c | 337 +
On Wed, Jan 29, 2020 at 04:16:44AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
> related to scalable mode translation, thus there are multiple combinations.
> While this vIOMMU implementation wants simplify it for user b
For the purpose of rebuild_hflags_a64, we do not need to compute
all of the va parameters, only tbi. Moreover, we can compute them
in a form that is more useful to storing in hflags.
This eliminates the need for aa64_va_parameter_both, so fold that
in to aa64_va_parameter. The remaining calls to
Something I noticed while developing and testing VHE.
For v2, fix select as a separate patch.
r~
Richard Henderson (2):
target/arm: Fix select for aa64_va_parameters_both
target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
target/arm/internals.h | 3 -
target/arm/helper.
Select should always be 0 for a regime with one range.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 46 +++--
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7d15d5c933..a008c70c
On Tue, Feb 11, 2020 at 07:13:48PM +, Peter Maydell wrote:
> On Tue, 11 Feb 2020 at 08:12, Philippe Mathieu-Daudé
> wrote:
> >
> > On 2/7/20 11:48 PM, Guenter Roeck wrote:
> > > On Fri, Feb 07, 2020 at 02:04:09PM -0800, no-re...@patchew.org wrote:
> > >> Patchew URL:
> > >> https://patchew.o
On Wed, Jan 29, 2020 at 04:16:43AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> This patch adds VFIO pasid alloc/free support to allow host intercept
> in PASID allocation for VM by adding VFIO implementation of
> DualStageIOMMUOps.pasid_alloc/free callbacks.
>
> Cc: Kevin Tian
> Cc: Jacob Pan
On Wed, Jan 29, 2020 at 04:16:42AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> VFIO checks IOMMU UAPI version when it finds Kernel supports
> VFIO_TYPE1_NESTING_IOMMU. It is enough for UAPI compatibility
> check. However, IOMMU UAPI may support multiple stage-1 pasid
> formats in a specific UAPI
On Tue, 11 Feb 2020 at 08:12, Philippe Mathieu-Daudé wrote:
>
> On 2/7/20 11:48 PM, Guenter Roeck wrote:
> > On Fri, Feb 07, 2020 at 02:04:09PM -0800, no-re...@patchew.org wrote:
> >> Patchew URL:
> >> https://patchew.org/QEMU/20200207174548.9087-1-li...@roeck-us.net/
> >>
> >>
> >>
> >> Hi,
> >>
On Wed, Jan 29, 2020 at 04:16:40AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> VFIO needs to check VFIO_TYPE1_NESTING_IOMMU
> support with Kernel before further using it.
> e.g. requires to check IOMMU UAPI version.
>
> Cc: Kevin Tian
> Cc: Jacob Pan
> Cc: Peter Xu
> Cc: Eric Auger
> Cc: Yi
On Thu, Jan 30, 2020 at 09:03:00AM +0100, Markus Armbruster wrote:
> Juan Quintela writes:
>
> > It will indicate which level use for compression.
> >
> > Signed-off-by: Juan Quintela
>
> This is slightly confusing (there is no zlib compression), unless you
> peek at the next patch (which adds
On 2/11/20 9:37 AM, Peter Maydell wrote:
> The LC bit in the PMCR_EL0 register is supposed to be:
> * read/write
> * RES1 on an AArch64-only implementation
> * an architecturally UNKNOWN value on reset
> (and use of LC==0 by software is deprecated).
>
> We were implementing it incorrectly as re
On 2/11/20 9:37 AM, Peter Maydell wrote:
> The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'.
> Correct our #define of PMCRDP and add the missing PMCRX.
>
> We do have the correct behaviour for handling the DP bit being
> set, so this fixes a guest-visible bug.
>
> Signed-off-by
On Wed, Jan 29, 2020 at 12:56:48PM +0100, Juan Quintela wrote:
> This will store the compression method to use. We start with none.
>
> Signed-off-by: Juan Quintela
> Reviewed-by: Markus Armbruster
> Reviewed-by: Dr. David Alan Gilbert
> ---
> hw/core/qdev-properties.c| 13 +
>
On 2/11/20 9:37 AM, Peter Maydell wrote:
> Set the ID register bits to provide ARMv8.4-PMU (and implicitly
> also ARMv8.1-PMU) in the 'max' CPU.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/cpu64.c | 8
> 1 file changed, 8 insertions(+)
Reviewed-by: Richard Henderson
r~
On 2/11/20 9:37 AM, Peter Maydell wrote:
> The ARMv8.4-PMU extension adds:
> * one new required event, STALL
> * one new system register PMMIR_EL1
>
> (There are also some more L1-cache related events, but since
> we don't implement any cache we don't provide these, in the
> same way we don't pr
* Juan Quintela (quint...@redhat.com) wrote:
> Signed-off-by: Juan Quintela
> ---
> migration/migration.c | 15 +++
> monitor/hmp-cmds.c| 4
> qapi/migration.json | 29 ++---
> 3 files changed, 45 insertions(+), 3 deletions(-)
>
> diff --git a/migr
On 2/11/20 9:37 AM, Peter Maydell wrote:
> The ARMv8.1-PMU extension requires:
> * the evtCount field in PMETYPER_EL0 is 16 bits, not 10
> * MDCR_EL2.HPMD allows event counting to be disabled at EL2
> * two new required events, STALL_FRONTEND and STALL_BACKEND
> * ID register bits in ID_AA64DFR
1 - 100 of 288 matches
Mail list logo
