Aleksandar Markovic wrote:
> On Thursday, February 27, 2020, Juan Quintela wrote:
>
> Marc-André Lureau wrote:
> > Hi Juan
> >
> > On Wed, Jan 8, 2020 at 2:08 PM Juan Quintela wrote:
> >>
> >> Marc-André Lureau wrote:
> >> n> Check the host pointer is correctly aligned, otherwise we may
While 32mb is certainly usable a full system boot ends up flushing the
codegen buffer nearly 100 times. Increase the default on 64 bit hosts
to take advantage of all that spare memory. After this change I can
boot my tests system without any TB flushes.
As we usually run more CONFIG_USER binaries
On Thu, 27 Feb 2020 20:07:24 +0100
Niek Linnenbank wrote:
> Hi Richard,
>
> On Thu, Feb 27, 2020 at 1:57 PM Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
> > On 2/27/20 4:31 AM, Alex Bennée wrote:
> > >> It does not make sense for a linux-user chroot, running make -jN, on
>
Philippe Mathieu-Daudé writes:
> From: Alistair Francis
>
> Replace a large number of the fprintf(stderr, "*\n" calls with
> error_report(). The functions were renamed with these commands and then
> compiler issues where manually fixed.
>
> find ./* -type f -exec sed -i \
> 'N;N;N;N;N;N;N;N;
>-Original Message-
>From: Kevin Wolf [mailto:kw...@redhat.com]
>Sent: Thursday, February 27, 2020 6:31 PM
>To: Chenqun (kuhn)
>Cc: qemu-devel@nongnu.org; qemu-triv...@nongnu.org;
>peter.mayd...@linaro.org; Zhanghailiang ;
>Euler Robot ; Ronnie Sahlberg
>; Paolo Bonzini ; Peter
>Lieven ; M
This example may be used as a template for custom benchmark.
It illustrates three things to prepare:
- define bench_func
- define test environments (columns)
- define test cases (rows)
And final call of simplebench API.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/bench
Hi all!
v3:
move all to scripts/simplebench
add myself as a maintainer of this thing
Here is simple benchmarking utility, to generate performance
comparison tables, like the following:
-- - - -
backup-1 backup-2 mirror
ss
Add simple benchmark table creator.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/simplebench.py | 128 +
1 file changed, 128 insertions(+)
create mode 100644 scripts/simplebench/simplebench.py
diff --git a/scripts/simplebench/simplebench.py
b
Add block-job benchmarking helper functions.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/bench_block_job.py | 119 +
1 file changed, 119 insertions(+)
create mode 100755 scripts/simplebench/bench_block_job.py
diff --git a/scripts/simplebench/benc
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5e5e3e52d6..16d069adc5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2038,6 +2038,11 @@ F: python/qemu/*py
F: scripts/*.py
F: tests/*.py
+Bench
Philippe Mathieu-Daudé writes:
> On 2/27/20 3:55 PM, Philippe Mathieu-Daudé wrote:
>> On 2/27/20 3:52 PM, Markus Armbruster wrote:
>>> Philippe Mathieu-Daudé writes:
>>>
This fixes when adding a 'Since' tag:
In file included from qapi/qapi-schema.json:105:
qapi/machine.
27.02.2020 23:09, Eduardo Habkost wrote:
Sorry, this is due to lack of bandwidth of maintainers who can
review those patches.
I have one suggestion: if you make your script self-contained
inside a scripts/ subdirectory, it would be simpler to merge it
without detailed reviews from others.
That
On 2020/2/28 13:46, Richard Henderson wrote:
On 2/25/20 6:43 PM, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 395 +++
target/riscv/insn32.decode | 127 +++
target/riscv/insn_trans/trans_rvv.inc.c | 671 +++-
targe
On 2020/2/28 11:33, Richard Henderson wrote:
On 2/27/20 5:50 PM, LIU Zhiwei wrote:
This is not what I had in mind, and looks wrong as well.
int idx = (index * mlen) / 64;
int pos = (index * mlen) % 64;
return (((uint64_t *)v0)[idx] >> pos) & 1;
You also might consider passing
On Thu, Feb 27, 2020 at 07:42:49AM -0600, Shivaprasad G Bhat wrote:
> Fixes Coverity issue,
> CID 1419883: Error handling issues (CHECKED_RETURN)
>Calling "qemu_uuid_parse" without checking return value
>
> nvdimm_set_uuid() already verifies if the user provided uuid is valid o
On 2/25/20 6:43 PM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 395 +++
> target/riscv/insn32.decode | 127 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 671 +++-
> target/riscv/vector_helper.c| 1308 +
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> +if (s->sew < 2) {
> +return false;
> +}
This could just as easily be in amo_check?
> +
> +if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> +#ifdef CONFIG_ATOMIC64
> +fn = fns[0][seq][s->sew - 2];
> +#else
> +gen_helper_exit_
> > +static coroutine_fn void vu_client_next_trip(VuClient *client);
> > +
> > +static coroutine_fn void vu_client_trip(void *opaque)
> > +{
> > +VuClient *client = opaque;
> > +
> > +vu_dispatch(&client->parent);
> > +client->co_trip = NULL;
> > +if (!client->closed) {
> > +
When malta is coupled with MIPS64 cpu which have 64bit
address space, it is possible to have more than 2G RAM.
So we removed ram_size check and overwrite memory
layout for these targets.
Signed-off-by: Jiaxun Yang
Suggested-by: Yunqiang Su
---
hw/mips/mips_malta.c | 24 ++--
> On Feb 26, 2020, at 1:42 AM, Laszlo Ersek wrote:
>
> Hi Andrew,
>
> On 02/25/20 22:35, Andrew Fish wrote:
>
>> Laszlo,
>>
>> The FLASH offsets changing breaking things makes sense.
>>
>> I now realize this is like updating the EFI ROM without rebooting the
>> system. Thus changes in how
On 2/27/20 5:50 PM, LIU Zhiwei wrote:
>> This is not what I had in mind, and looks wrong as well.
>>
>> int idx = (index * mlen) / 64;
>> int pos = (index * mlen) % 64;
>> return (((uint64_t *)v0)[idx] >> pos) & 1;
>>
>> You also might consider passing log2(mlen), so the multiplication
Hi Laszlo,
> -Original Message-
> From: Qemu-devel
> [mailto:qemu-devel-bounces+jianjay.zhou=huawei@nongnu.org] On Behalf
> Of Laszlo Ersek
> Sent: Wednesday, February 26, 2020 5:42 PM
> To: Andrew Fish ; de...@edk2.groups.io
> Cc: berra...@redhat.com; qemu-devel@nongnu.org; Dr. David
And intialize buffer_is_zero() with it, when Intel AVX512F is
available on host.
This function utilizes Intel AVX512 fundamental instructions which
is faster than its implementation with AVX2 (in my unit test, with
4K buffer, on CascadeLake SP, ~36% faster, buffer_zero_avx512() V.S.
buffer_zero_av
If it is enabled, config-host.mak will have CONFIG_AVX512F_OPT defined.
AVX512F instruction set is available since Intel Skylake, and can be enabled in
compiling with -mavx512f.
More info:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programm
1) Introduce {enable,disable}-avx512f configure option
2) Implement new buffer_zero_avx512() with AVX512F instructions
Changes in v3:
In init_accel(), init length_to_accel value in every accel case, because
in unit test, it will be invoked several times with different accel cases.
(Thanks Richard
On 2020/2/28 4:03, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+GEN_VEXT_LD_ELEM(vlbff_v_b, int8_t, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(vlbff_v_h, int8_t, int16_t, H2, ldsb)
+GEN_VEXT_LD_ELEM(vlbff_v_w, int8_t, int32_t, H4, ldsb)
+GEN_VEXT_LD_ELEM(vlbff_v_d, int8_t, in
On 2020/2/28 3:49, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+vsxb_v ... 011 . . . 000 . 0100111 @r_nfvm
+vsxh_v ... 011 . . . 101 . 0100111 @r_nfvm
+vsxw_v ... 011 . . . 110 . 0100111 @r_nfvm
+vsxe_v ... 011 . . ...
On 2020/2/28 3:36, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t, int64_
On 2020/2/28 3:17, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
+{
+int legal = widen ? 2 << s->lmul : 1 << s->lmul;
+
+return !((s->lmul == 0x3 && widen) || (reg % legal));
+}
+
+static bool vext_
Public bug reported:
i am trying to run Windows 10 x64 on Windows 10 x64 host with intel haxm
as kernel accelerator, but the system never boots, as far i read the
documentation everything should be fine...
the logs are qemu:
`
D:\vm>qemu-system-x86_64 -d
guest_errors,out_asm,in_asm,op,op_opt,o
HAXM covers below files:
include/sysemu/hax.h
target/i386/hax-*
V2: Add HAXM github page for wiki and issue tracking.
Cc: Wenchao Wang
Cc: Hang Yuan
Reviewed-by: Hang Yuan
Signed-off-by: Colin Xu
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/M
I hope to fix it tomorrow, but I can't be sure. Maybe it will fix itself
and I'll just abandon the digest for today. Very few people use the
digest feature, normally it goes out at noonish eastern time.
All I've had time to do done is grab a stack trace, seems like there's
some characters in an em
On 2020-02-27 16:00, Philippe Mathieu-Daudé wrote:
On 2/27/20 8:56 AM, Philippe Mathieu-Daudé wrote:
Cc'ing qemu-trivial@
On 2/26/20 5:32 AM, Colin Xu wrote:
HAXM covers below files:
include/sysemu/hax.h
target/i386/hax-*
Cc: Wenchao Wang
Cc: Hang Yuan
Signed-off-by: Colin Xu
Please ke
On 2/27/2020 5:48 PM, Jack Wang wrote:
Chenyi Qiang 于2020年2月27日周四 上午10:07写道：
According to the Intel Icelake family list, Icelake-Client uses model
number 126(0x7D)
0x7D is 125 in hex, so the commit message needs to be fixed.
Sorry, my mistake.
Cheers
Jack Wang
On Thu, Feb 27, 2020 at 10:12 PM Stefan Ring wrote:
> Victory! I have a reproducer in the form of a plain C libgfapi client.
>
> However, I have not been able to trigger corruption by just executing
> the simple pattern in an artificial way. Currently, I need to feed my
> reproducer 2 GB of data t
The Cubieboard machine does not support the -bios argument.
Report an error when -bios is used and exit immediately.
Signed-off-by: Niek Linnenbank
---
hw/arm/cubieboard.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 6c55d9056f..871b1
These patches change the Cubieboard machine definition to use the
correct CPU type, which is ARM Cortex-A8 instead of ARM Cortex-A9.
Additionally, add some sanity checks for the machine input
arguments in the initialization function.
Niek Linnenbank (4):
hw/arm/cubieboard: use ARM Cortex-A8 as
The Cubieboard contains either 512MiB or 1GiB of onboard RAM [1].
Prevent changing RAM to a different size which could break user programs.
[1] http://linux-sunxi.org/Cubieboard
Signed-off-by: Niek Linnenbank
---
hw/arm/cubieboard.c | 8
1 file changed, 8 insertions(+)
diff --git a/h
The Cubieboard is a singleboard computer with an Allwinner A10 System-on-Chip
[1].
As documented in the Allwinner A10 User Manual V1.5 [2], the SoC has an ARM
Cortex-A8 processor. Currently the Cubieboard machine definition specifies the
ARM Cortex-A9 in its description and as the default CPU.
Th
The Cubieboard has an ARM Cortex-A8. Prevent changing the CPU
to a different type which could break user programs.
Signed-off-by: Niek Linnenbank
---
hw/arm/cubieboard.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index
On Wed, Feb 26, 2020 at 5:41 PM LIU Zhiwei wrote:
>
>
>
> On 2020/2/27 3:20, Alistair Francis wrote:
> > On Fri, Feb 21, 2020 at 1:45 AM LIU Zhiwei wrote:
> >> vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
> >> should update after configure instructions. The (ill, lm
On Wed, Feb 26, 2020 at 02:24:53PM +0100, Greg Kurz wrote:
> On Tue, 25 Feb 2020 10:37:17 +1100
> David Gibson wrote:
>
> > When the LPCR is written, we update the env->rmls field with the RMA limit
> > it implies. Simplify things by just calculating the value directly from
> > the LPCR value wh
On Wed, Feb 26, 2020 at 08:56:40AM +0100, Greg Kurz wrote:
> On Wed, 26 Feb 2020 12:04:13 +1100
> David Gibson wrote:
>
> > On Tue, Feb 25, 2020 at 11:47:25PM +0100, Greg Kurz wrote:
> > > On Tue, 25 Feb 2020 18:05:31 +0100
> > > Greg Kurz wrote:
> > >
> > > > On Tue, 25 Feb 2020 10:37:15 +1100
On Wed, Feb 26, 2020 at 02:37:51PM +0100, Greg Kurz wrote:
> On Tue, 25 Feb 2020 10:37:23 +1100
> David Gibson wrote:
>
> > Move the calculation of the Real Mode Area (RMA) size into a helper
> > function. While we're there clean it up and correct it in a few ways:
> > * Add comments making it
On Thu, Feb 27, 2020 at 10:14:47PM +0100, Auger Eric wrote:
> Hi Peter,
Hi, Eric,
[...]
> > + * the KVM resample fd kick is skipped. The userspace
> > + * needs to remember the resamplefd and kick it when we
> > + * receive EOI of this IRQ.
>
On Thu, Feb 27, 2020 at 1:44 PM Peter Maydell wrote:
>
> On Thu, 27 Feb 2020 at 21:37, Alistair Francis wrote:
> > I do hit this problem, Peter described a workaround in the previous
> > version of this patch, that is to link at address 0 instead of the
> > alias address.
>
> Do you happen to hav
On Thu, 27 Feb 2020 at 21:37, Alistair Francis wrote:
> I do hit this problem, Peter described a workaround in the previous
> version of this patch, that is to link at address 0 instead of the
> alias address.
Do you happen to have a simple test case you can send me
that demonstrates the bug? Tha
On Thu, Feb 27, 2020 at 5:32 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Stephanos,
>
> On 2/27/20 12:51 PM, Stephanos Ioannidis wrote:
> > The ARMv7-M CPU reset handler, which loads the initial SP and PC
> > register values from the vector table, is currently executed before
> > the ROM reset handler
> -Original Message-
> From: Eduardo Habkost
> Sent: Thursday, February 27, 2020 1:10 PM
> To: Sunil Muthuswamy
> Cc: Paolo Bonzini ; Richard Henderson
> ; qemu-devel@nongnu.org; Stefan Weil
>
> Subject: [EXTERNAL] Re: [PATCH] WHPX: Use QEMU values for trapped CPUID
>
> On Thu, Feb 27,
Hi Peter,
On 2/27/20 8:19 PM, Peter Xu wrote:
> On Thu, Feb 27, 2020 at 07:22:08PM +0100, Auger Eric wrote:
>> Hi Peter,
>>
>> On 2/27/20 7:00 PM, Peter Xu wrote:
>>> On Thu, Feb 27, 2020 at 06:42:09PM +0100, Auger Eric wrote:
Hi Peter,
On 2/27/20 6:00 PM, Peter Xu wrote:
> This
On Tue, Feb 25, 2020 at 3:12 PM Stefan Ring wrote:
>
> I find many instances with the following pattern:
>
> current file length (= max position + size written): p
> write request n writes from (p + hole_size), thus leaving a hole
> request n+1 writes exactly hole_size, starting from p, thus compl
On Thu, Feb 27, 2020 at 09:01:04PM +, Sunil Muthuswamy wrote:
> Currently, WHPX is using some default values for the trapped CPUID
> functions. These were not in sync with the QEMU values because the
> CPUID values were never set with WHPX during VCPU initialization.
> Additionally, at the mome
Currently, WHPX is using some default values for the trapped CPUID
functions. These were not in sync with the QEMU values because the
CPUID values were never set with WHPX during VCPU initialization.
Additionally, at the moment, WHPX doesn't support setting CPUID
values in the hypervisor at runtime
On Thursday, February 27, 2020, Juan Quintela wrote:
> Marc-André Lureau wrote:
> > Hi Juan
> >
> > On Wed, Jan 8, 2020 at 2:08 PM Juan Quintela
> wrote:
> >>
> >> Marc-André Lureau wrote:
> >> n> Check the host pointer is correctly aligned, otherwise we may fail
> >> > during migration in ram
On Thu, Feb 13, 2020 at 10:17:08PM +0100, Juan Quintela wrote:
> This parameter specifies the zstd compression level. The next patch
> will put it to use.
>
> Signed-off-by: Juan Quintela
> Acked-by: Markus Armbruster
(I didn't look at the rest of patches, but this single patch looks
sane to m
On 2/27/20 7:02 AM, Halil Pasic wrote:
> On Wed, 26 Feb 2020 11:52:26 -0500
> "Michael S. Tsirkin" wrote:
>
>> On Wed, Feb 26, 2020 at 04:36:18PM +0100, Halil Pasic wrote:
>>> On Wed, 26 Feb 2020 08:37:13 -0500
>>> "Michael S. Tsirkin" wrote:
>>>
On Wed, Feb 26, 2020 at 02:28:39PM +0100, Ha
On 2/21/20 1:45 AM, LIU Zhiwei wrote:
> vlen is the vector register length in bits.
> elen is the max element size in bits.
> vext_spec is the vector specification version, default value is v0.7.1.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/cpu.c | 7 +++
> target/riscv/cpu.h | 5 +++
On 2/21/20 1:45 AM, LIU Zhiwei wrote:
> The 32 vector registers will be viewed as a continuous memory block.
> It avoids the convension between element index and (regno, offset).
> Thus elements can be directly accessed by offset from the first vector
> base address.
>
> Signed-off-by: LIU Zhiwei
On Thu, Feb 27, 2020 at 04:21:56PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/27/20 3:55 PM, Philippe Mathieu-Daudé wrote:
> > On 2/27/20 3:52 PM, Markus Armbruster wrote:
> > > Philippe Mathieu-Daudé writes:
> > >
> > > > This fixes when adding a 'Since' tag:
> > > >
> > > > In file include
Sorry, this is due to lack of bandwidth of maintainers who can
review those patches.
I have one suggestion: if you make your script self-contained
inside a scripts/ subdirectory, it would be simpler to merge it
without detailed reviews from others.
The python/ subdirectory is supposed to appear o
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> +GEN_VEXT_LD_ELEM(vlbff_v_b, int8_t, int8_t, H1, ldsb)
> +GEN_VEXT_LD_ELEM(vlbff_v_h, int8_t, int16_t, H2, ldsb)
> +GEN_VEXT_LD_ELEM(vlbff_v_w, int8_t, int32_t, H4, ldsb)
> +GEN_VEXT_LD_ELEM(vlbff_v_d, int8_t, int64_t, H8, ldsb)
> +GEN_VEXT_LD_ELEM(vlhff
On Thu, 27 Feb 2020 at 08:55, Michael S. Tsirkin wrote:
>
> On Wed, Feb 26, 2020 at 04:01:02AM -0500, Michael S. Tsirkin wrote:
> > changes from v1:
> > dropped vhost changes, hope this fixes build on Mac OS.
> >
> > The following changes since commit 9a8abceb5f01d1066d3a1ac5a33aabcbaeec1860:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> +vsxb_v ... 011 . . . 000 . 0100111 @r_nfvm
> +vsxh_v ... 011 . . . 101 . 0100111 @r_nfvm
> +vsxw_v ... 011 . . . 110 . 0100111 @r_nfvm
> +vsxe_v ... 011 . . . 111 . 0100111 @r_nfvm
> +vsuxb_v
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> +GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb)
> +GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb)
> +GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb)
> +GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t, int64_t, H8, ldsb)
> +GEN_VEXT_LD_ELEM(vlsh_v_h,
On Thu, Feb 27, 2020 at 07:22:08PM +0100, Auger Eric wrote:
> Hi Peter,
>
> On 2/27/20 7:00 PM, Peter Xu wrote:
> > On Thu, Feb 27, 2020 at 06:42:09PM +0100, Auger Eric wrote:
> >> Hi Peter,
> >>
> >> On 2/27/20 6:00 PM, Peter Xu wrote:
> >>> This is majorly only for X86 because that's the only on
On Wed, Feb 26, 2020 at 7:12 PM Alex Bennée wrote:
> There is no particular reason to use a static codegen buffer on 64 bit
> hosts as we have address space to burn. Allow the common CONFIG_USER
> case to use the mmap'ed buffers like SoftMMU.
>
> Signed-off-by: Alex Bennée
> ---
> accel/tcg/tra
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> +static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
> +{
> +int legal = widen ? 2 << s->lmul : 1 << s->lmul;
> +
> +return !((s->lmul == 0x3 && widen) || (reg % legal));
> +}
> +
> +static bool vext_check_overlap_mask(DisasContext *
Correcting Zhang email.
On 2/19/20 10:47 AM, pannengy...@huawei.com wrote:
From: Pan Nengyuan
'list' forgot to free at the end of dump_vmstate_json_to_file(), although it's
called only once, but seems like a clean code.
Fix the leak as follow:
Direct leak of 16 byte(s) in 1 object(s) allocat
On Thu, 27 Feb 2020 at 01:56, Eric Blake wrote:
>
> The following changes since commit db736e0437aa6fd7c1b7e4599c17f9619ab6b837:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2020-02-25 13:31:16 +)
>
> are available in the Git repository at:
>
> http
Document the list returned by object_class_get_list() must be
released with g_slist_free() to avoid memory leaks.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/qom/object.h b/include/qom/object.h
index 29546496c1.
Hi Richard,
On Thu, Feb 27, 2020 at 1:57 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 2/27/20 4:31 AM, Alex Bennée wrote:
> >> It does not make sense for a linux-user chroot, running make -jN, on
> just about
> >> any host. For linux-user, I could be happy with a modest incre
On 2/19/20 10:59 AM, Dr. David Alan Gilbert wrote:
* pannengy...@huawei.com (pannengy...@huawei.com) wrote:
From: Pan Nengyuan
'list' forgot to free at the end of dump_vmstate_json_to_file(), although it's
called only once, but seems like a clean code.
Fix the leak as follow:
Direct leak of
Hi Alex,
On Thu, Feb 27, 2020 at 1:19 PM Alex Bennée wrote:
>
> Niek Linnenbank writes:
>
> > Hi Alex,
> >
> > On Wed, Feb 26, 2020 at 7:13 PM Alex Bennée
> wrote:
> >
> >> While 32mb is certainly usable a full system boot ends up flushing the
> >> codegen buffer nearly 100 times. Increase the
On 2/27/20 11:02 AM, Max Reitz wrote:
Test that qemu-img check reports the number of leaks and corruptions
fixed in its JSON report (after a successful run).
Signed-off-by: Max Reitz
---
tests/qemu-iotests/138 | 41 --
tests/qemu-iotests/138.out | 14 +
On 2/27/20 11:02 AM, Max Reitz wrote:
Similarly to peek_file_[bl]e, we may want to write binary integers into
a file. Currently, this often means messing around with poke_file and
raw binary strings. I hope these functions make it a bit more
comfortable.
Signed-off-by: Max Reitz
---
tests/q
Marc-André Lureau wrote:
> Hi Juan
>
> On Wed, Jan 8, 2020 at 2:08 PM Juan Quintela wrote:
>>
>> Marc-André Lureau wrote:
>> n> Check the host pointer is correctly aligned, otherwise we may fail
>> > during migration in ram_block_discard_range().
>> >
>> > Signed-off-by: Marc-André Lureau
>>
>>
zhanghailiang wrote:
> This helper has been called twice which is wrong.
> Left the one where called while get COLO enable message
> from source side.
>
> Signed-off-by: zhanghailiang
Reviewed-by: Juan Quintela
zhanghailiang wrote:
> This commit "migration: Create migration_is_running()" broke
> COLO. Becuase there is a process broken by this commit.
>
> colo_process_checkpoint
> ->colo_do_checkpoint_transaction
>->migrate_set_block_enabled
> ->qmp_migrate_set_capabilities
>
> It can be fixed b
The file_cluster_offset field of Qcow2AioTask stores a cluster-aligned
host offset. In practice this is not very useful because all users(*)
of this structure need the final host offset into the cluster, which
they calculate using
host_offset = file_cluster_offset + offset_into_cluster(s, offse
qcow2_get_cluster_offset() takes an (unaligned) guest offset and
returns the (aligned) offset of the corresponding cluster in the qcow2
image.
In practice none of the callers need to know where the cluster starts
so this patch makes the function calculate and return the final host
offset directly.
Hi,
this is something I did while working on the subcluster series but
it's independent from it so I thought to send it already.
In short: qcow2_get_cluster_offset() returns a host cluster offset but
none of the callers actually wants the offset of the cluster, they
want the host offset into the
On 2/27/20 11:02 AM, Max Reitz wrote:
There are two problems with qemu-img check's report on how many leaks
and/or corruptions have been fixed:
(1) ImageCheck.has_leaks_fixed and ImageCheck.has_corruptions_fixed are
only true when ImageCheck.leaks or ImageCheck.corruptions (respectively)
are non
Hi Peter,
On 2/27/20 7:00 PM, Peter Xu wrote:
> On Thu, Feb 27, 2020 at 06:42:09PM +0100, Auger Eric wrote:
>> Hi Peter,
>>
>> On 2/27/20 6:00 PM, Peter Xu wrote:
>>> This is majorly only for X86 because that's the only one that supports
>>> split irqchip for now.
>>>
>>> When the irqchip is split
This patch allows bdrv_reopen() (and therefore the x-blockdev-reopen QMP
command) to attach a node as the new backing file even if the node is in
a different AioContext than the parent if one of both nodes can be moved
to the AioContext of the other node.
Signed-off-by: Kevin Wolf
---
block.c
Kevin Wolf (2):
iotests: Refactor blockdev-reopen test for iothreads
block: bdrv_reopen() with backing file in different AioContext
block.c| 36 +-
tests/qemu-iotests/245 | 40 --
tests/qemu-iotests/24
We'll want to test more than one successful case in the future, so
prepare the test for that by a refactoring that runs each scenario in a
separate VM.
test_iothreads_switch_{backing,overlay} currently produce errors, but
these are cases that should actually work, by switching either the
backing f
On Wed, 26 Feb 2020 at 07:39, Alex Bennée wrote:
>
> The following changes since commit db736e0437aa6fd7c1b7e4599c17f9619ab6b837:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2020-02-25 13:31:16 +)
>
> are available in the Git repository at:
>
> htt
wrote:
> From: Pan Nengyuan
>
> 'list' forgot to free at the end of dump_vmstate_json_to_file(), although
> it's called only once, but seems like a clean code.
>
> Fix the leak as follow:
> Direct leak of 16 byte(s) in 1 object(s) allocated from:
> #0 0x7fb946abd768 in __interceptor_malloc (
wrote:
> From: Chen Qun
>
> There is memleak in test_load_qlist().It's not a big deal,
> but test-vmstate will fail if sanitizers is enabled.
>
> In addition, "ret" is written twice with the same value
> in test_gtree_load_iommu().
>
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
Review
wrote:
> From: Chen Qun
>
> The "ret" has been assigned in all branches. It didn't need to be
> assigned separately.
>
> Clang static code analyzer show warning:
> migration/vmstate.c:365:17: warning: Value stored to 'ret' is never read
> ret = 0;
> ^ ~
>
>
On Thu, Feb 27, 2020 at 06:42:09PM +0100, Auger Eric wrote:
> Hi Peter,
>
> On 2/27/20 6:00 PM, Peter Xu wrote:
> > This is majorly only for X86 because that's the only one that supports
> > split irqchip for now.
> >
> > When the irqchip is split, we face a dilemma that KVM irqfd will be
> > ena
Hi Peter,
On 2/27/20 6:00 PM, Peter Xu wrote:
> This is majorly only for X86 because that's the only one that supports
> split irqchip for now.
>
> When the irqchip is split, we face a dilemma that KVM irqfd will be
> enabled, however the slow irqchip is still running in the userspace.
> It means
On 2/27/20 6:20 PM, Marc-André Lureau wrote:
Hi
On Thu, Feb 27, 2020 at 5:32 PM Philippe Mathieu-Daudé
wrote:
Use error_setg_win32() which adds a hint similar to strerror(errno)).
Signed-off-by: Philippe Mathieu-Daudé
---
qga/channel-win32.c | 3 ++-
qga/commands-win32.c | 6 +++---
2
Hi,
That’s intentional. The man page says this:
--force-share (-U)
If specified, "qemu-img" will open the image in shared mode,
allowing other QEMU processes to open it in write mode. For
example, this can be used to get the image information (with
On Tue, 25 Feb 2020 at 20:32, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > Add patterns for the new instructions in the v8.3-RCPC and
> > v8.4-RCPC extensions.
> >
> > Signed-off-by: Peter Maydell
> > ---
> > This is what I used for testing the RCPC QEMU patches I sent out
> > the other
On Thu, Feb 27, 2020 at 5:32 PM Philippe Mathieu-Daudé
wrote:
>
> Use error_setg_win32() which adds a hint similar to strerror(errno)).
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Marc-André Lureau
> ---
> util/osdep.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletion
On Thu, Feb 27, 2020 at 5:32 PM Philippe Mathieu-Daudé
wrote:
>
> The string returned by g_win32_error_message() has to be
> deallocated with g_free().
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Marc-André Lureau
> ---
> qga/channel-win32.c | 4 ++--
> 1 file changed, 2 insertion
Hi
On Thu, Feb 27, 2020 at 5:32 PM Philippe Mathieu-Daudé
wrote:
>
> Use error_setg_win32() which adds a hint similar to strerror(errno)).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> qga/channel-win32.c | 3 ++-
> qga/commands-win32.c | 6 +++---
> 2 files changed, 5 insertions(+), 4 del
On Mon, Feb 24, 2020 at 03:55:39PM -0500, Jagannathan Raman wrote:
> From: Elena Ufimtseva
>
> Validate the incoming commands to confirm that they would not cause any
> errors in the remote process.
>
> Signed-off-by: Elena Ufimtseva
> Signed-off-by: Jagannathan Raman
> Signed-off-by: John G J
On Thu, Feb 27, 2020 at 12:00:48PM -0500, Peter Xu wrote:
> +static inline void kvm_resample_fd_remove(int gsi)
> +{
> +KVMResampleFd *rfd;
> +
> +QLIST_FOREACH(rfd, &kvm_resample_fd_list, node) {
> +if (rfd->gsi == gsi) {
> +QLIST_REMOVE(rfd, node);
Oops, rfd is leaked
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