On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 33 +++
> target/riscv/insn32.decode | 8 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 10
> target/riscv/vector_helper.c| 74 +
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
> +{
> +uint64_t hi_64, lo_64, abs_s2 = s2;
> +
> +if (s2 < 0) {
> +abs_s2 = -s2;
> +}
> +mulu64(&lo_64, &hi_64, abs_s2, s1);
> +if ((int64_t)(s2 ^ s1) < 0) {
Why would the sign
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Integer Min/Max Instructions */
> +GEN_OPIVV_GVEC_TRANS(vminu_vv, umin)
> +GEN_OPIVV_GVEC_TRANS(vmin_vv, smin)
> +GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax)
> +GEN_OPIVV_GVEC_TRANS(vmax_vv, smax)
> +GEN_OPIVX_TRANS(vminu_vx, opivx_check)
> +GEN_OPIVX_T
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Integer Comparison Instructions */
> +#define DO_MSEQ(N, M) ((N == M) ? 1 : 0)
> +#define DO_MSNE(N, M) ((N != M) ? 1 : 0)
> +#define DO_MSLTU(N, M) ((N < M) ? 1 : 0)
> +#define DO_MSLT(N, M) ((N < M) ? 1 : 0)
> +#define DO_MSLEU(N, M) ((N <= M) ?
On 2020/3/14 14:16, Richard Henderson wrote:
On 3/13/20 10:58 PM, Richard Henderson wrote:
C ? N + M <= N : N + M < N
Ho hum. N + M + 1 <= N.
I'm sure you saw the typo...
You give the corner case and the very precise answer.
Thanks very much.
Zhiwei
r~
On 3/13/20 10:58 PM, Richard Henderson wrote:
> C ? N + M <= N : N + M < N
Ho hum. N + M + 1 <= N.
I'm sure you saw the typo...
r~
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 13
> target/riscv/insn32.decode | 6 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 91 +
> target/riscv/vector_helper.c| 14
On 2020/3/14 13:58, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+#define DO_MADC(N, M, C) ((__typeof(N))(N + M + C) < N ? 1 : 0)
Incorrect. E.g N = 1, M = UINT_MAX, C = 1, adds to 1, which is not less than
N, despite the carry-out.
Yes, it really the corner case. I shoul
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, GVSUF)
> \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
> +{
> \
> +
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 25
> target/riscv/insn32.decode | 9 +
> target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
> target/riscv/vector_helper.c| 51
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +#define DO_MADC(N, M, C) ((__typeof(N))(N + M + C) < N ? 1 : 0)
Incorrect. E.g N = 1, M = UINT_MAX, C = 1, adds to 1, which is not less than
N, despite the carry-out.
You want
C ? N + M <= N : N + M < N
> +#define DO_MSBC(N, M, C) ((__typeof(N))(N -
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 49
> target/riscv/insn32.decode | 16 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 154
> target/riscv/vector_helper.c
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +if (a->vm && s->vl_eq_vlmax) { \
> +tcg_gen_gvec_##GVSUF(8 << s->sew, vreg_ofs(s, a->rd), \
> +vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), \
> +MAXSZ(s), MAXSZ(s));
On 2020/3/14 12:28, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+static gen_helper_amo *const fnsw[9] = {
...
+static gen_helper_amo *const fnsd[18] = {
...
+fn = fnsw[seq];
+#ifdef TARGET_RISCV64
+if (s->sew == 3) {
+fn = fnsd[seq];
Alexander Bulekov writes:
> On 200313 1805, Markus Armbruster wrote:
>> Signed-off-by: Markus Armbruster
>
>
>> index 1a99277d60..aa9eee6ebf 100644
>> --- a/tests/qtest/fuzz/qos_fuzz.c
>> +++ b/tests/qtest/fuzz/qos_fuzz.c
>> @@ -57,8 +57,7 @@ static void qos_set_machines_devices_available(void)
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static gen_helper_amo *const fnsw[9] = {
...
> +static gen_helper_amo *const fnsd[18] = {
...
> +fn = fnsw[seq];
> +#ifdef TARGET_RISCV64
> +if (s->sew == 3) {
> +fn = fnsd[seq];
> +}
> +#endif
This indexing is wr
On Thu, Mar 5, 2020 at 11:18 AM Philippe Mathieu-Daudé
wrote:
>
> Please post new patches as v2, and do not post them as reply to v1.
>
> On 3/3/20 1:41 AM, Jiaxun Yang wrote:
> > When malta is coupled with MIPS64 cpu which have 64bit
> > address space, it is possible to have more than 2G RAM.
> >
>-Original Message-
>From: Peter Maydell [mailto:peter.mayd...@linaro.org]
>Sent: Friday, March 13, 2020 10:29 PM
>To: Chenqun (kuhn)
>Cc: QEMU Developers ; QEMU Trivial triv...@nongnu.org>; Zhanghailiang ;
>Euler Robot ; Jason Wang
>; Peter Chubb
>Subject: Re: [PATCH v4] hw/net/imx_fec:
On Fri, Mar 13, 2020 at 1:28 AM Lirong Yuan wrote:
>
> This change updates TASK_UNMAPPED_BASE (the base address for guest programs)
> for aarch64. It is needed to allow qemu to work with Thread Sanitizer (TSan),
> which has specific boundary definitions for memory mappings on different
> platfo
On Sat, Mar 14, 2020 at 3:35 AM Corey Wharton wrote:
>
> The sifive-e34 cpu type is the same as the sifive-e31 with the
> single precision floating-point extension enabled.
>
> Signed-off-by: Corey Wharton
> ---
> v2: Added missing RVU flag
>
> target/riscv/cpu.c | 10 ++
> target/riscv/
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> The unit-stride fault-only-fault load instructions are used to
> vectorize loops with data-dependent exit conditions(while loops).
> These instructions execute as a regular load except that they
> will only take a trap on element 0.
>
> Signed-off-by: LIU Zh
On 2020/3/14 9:26, Richard Henderson wrote:
On 3/13/20 2:32 PM, LIU Zhiwei wrote:
+/* check functions */
+static bool vext_check_isa_ill(DisasContext *s, target_ulong isa)
+{
+ return !s->vill && ((s->misa & isa) == isa);
+}
I don't think we need a new function to check ISA.
I don't thin
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static inline void vext_ldst_index(void *vd, void *v0, target_ulong base,
> +void *vs2, CPURISCVState *env, uint32_t desc,
> +vext_get_index_addr get_index_addr,
> +vext_ldst_elem_fn ldst_elem,
> +vext_ld_clear_elem clear_elem
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Vector strided operations access the first memory element at the base address,
> and then access subsequent elements at address increments given by the byte
> offset contained in the x register specified by rs2.
>
> Vector unit-stride operations access eleme
On 3/13/20 2:32 PM, LIU Zhiwei wrote:
>>> +/* check functions */
>>> +static bool vext_check_isa_ill(DisasContext *s, target_ulong isa)
>>> +{
>>> + return !s->vill && ((s->misa & isa) == isa);
>>> +}
>> I don't think we need a new function to check ISA.
> I don't think so.
>
> Although there i
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl * a)
> +{
> +TCGv s1, s2, dst;
> +s2 = tcg_temp_new();
> +dst = tcg_temp_new();
> +
> +/* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> +if (a->rs1 == 0) {
> +
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> The v0.7.1 specification does not define vector status within mstatus.
> A future revision will define the privileged portion of the vector status.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/cpu_bits.h | 15 +
> target/riscv/csr.c | 75
On 2020/3/14 8:02, Alistair Francis wrote:
On Thu, Mar 12, 2020 at 8:15 AM LIU Zhiwei wrote:
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element o
Hi
On Fri, Mar 13, 2020 at 7:42 PM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Without looking at the rest of the series, I fail to see the
improvement, quite the opposite. A bit of context?
> ---
> qapi/char.json | 32
> qapi/m
Patchew URL:
https://patchew.org/QEMU/cover.1584143748.git.alistair.fran...@wdc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v8 0/4] linux-user: generate syscall_nr.sh for RISC-V
Message-id: cover.1584143748.git.alistai
Jason Andryuk, le jeu. 12 mars 2020 08:55:21 -0400, a ecrit:
> usb-serial has issues with xHCI controllers where data is lost in the
> VM. Inspecting the URBs in the guest, EHCI starts every 64 byte boundary
> (wMaxPacketSize) with a header. EHCI hands packets into
> usb_serial_token_in() with si
Signed-off-by: Alistair Francis
Reviewed-by: Laurent Vivier
---
linux-user/riscv/syscall32_nr.h | 295 +++
linux-user/riscv/syscall64_nr.h | 301
linux-user/riscv/syscall_nr.h | 294 +--
3 files changed, 5
Add support for host and target futex_time64. If futex_time64 exists on
the host we try that first before falling back to the standard futux
syscall.
Signed-off-by: Alistair Francis
---
linux-user/syscall.c | 144 +++
1 file changed, 131 insertions(+), 13
Add support for the clock_gettime64/clock_settime64 syscalls.
If your host is 64-bit or is 32-bit with the *_time64 syscall then the
timespec will correctly be a 64-bit time_t. Otherwise the host will
return a 32-bit time_t which will be rounded to 64-bits. This will be
incorrect after y2038.
Sig
New y2038 safe 32-bit architectures (like RISC-V) don't support old
syscalls with a 32-bit time_t. The kernel defines new *_time64 versions
of these syscalls. Add some more #ifdefs to syscall.c in linux-user to
allow us to compile without these old syscalls.
Signed-off-by: Alistair Francis
Review
This series updates the RISC-V syscall_nr.sh based on the 5.5 kernel.
There are two parts to this. One is just adding the new syscalls, the
other part is updating the RV32 syscalls to match the fact that RV32 is
a 64-bit time_t architectures (y2038) safe.
We need to make some changes to syscall.c
On Thu, Mar 12, 2020 at 8:15 AM LIU Zhiwei wrote:
>
> Vector AMOs operate as if aq and rl bits were zero on each element
> with regard to ordering relative to other instructions in the same hart.
> Vector AMOs provide no ordering guarantee between element operations
> in the same vector AMO instru
Jason Andryuk, le jeu. 12 mars 2020 08:55:20 -0400, a ecrit:
> We'll be adding a loop, so move the code into a helper function. breaks
> are replaced with returns.
>
> Signed-off-by: Jason Andryuk
Reviewed-by: Samuel Thibault
> ---
> hw/usb/dev-serial.c | 77 +
On Fri, Mar 13, 2020 at 2:45 PM Laurent Vivier wrote:
> Le 13/03/2020 à 01:28, Lirong Yuan a écrit :
> > This change updates TASK_UNMAPPED_BASE (the base address for guest
> programs) for aarch64. It is needed to allow qemu to work with Thread
> Sanitizer (TSan), which has specific boundary defin
On Fri, Mar 13, 2020 at 3:17 PM LIU Zhiwei wrote:
>
>
>
> On 2020/3/14 6:05, Alistair Francis wrote:
> > On Fri, Mar 13, 2020 at 2:32 PM LIU Zhiwei wrote:
> >>
> >>
> >> On 2020/3/14 4:38, Alistair Francis wrote:
> >>> On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote:
> Vector strided opera
On 13/03/2020 22:07, Philippe Mathieu-Daudé wrote:
On 3/12/20 5:54 PM, Liran Alon wrote:
diff --git a/include/hw/i386/vmport.h b/include/hw/i386/vmport.h
index 34cc050b1ffa..aee809521aa0 100644
--- a/include/hw/i386/vmport.h
+++ b/include/hw/i386/vmport.h
@@ -12,6 +12,7 @@ typedef enum {
On 13/03/2020 22:05, Philippe Mathieu-Daudé wrote:
On 3/13/20 8:59 PM, Philippe Mathieu-Daudé wrote:
On 3/12/20 5:54 PM, Liran Alon wrote:
--- a/include/hw/i386/vmport.h
+++ b/include/hw/i386/vmport.h
@@ -4,12 +4,21 @@
#define TYPE_VMPORT "vmport"
typedef uint32_t (VMPortReadFunc)(void *o
On 2020/3/14 6:24, Alistair Francis wrote:
On Thu, Mar 12, 2020 at 8:13 AM LIU Zhiwei wrote:
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will onl
On 13/03/2020 21:59, Philippe Mathieu-Daudé wrote:
On 3/12/20 5:54 PM, Liran Alon wrote:
No functional change.
Defining an enum for all VMPort commands have the following advantages:
* It gets rid of the error-prone requirement to update VMPORT_ENTRIES
when new VMPort commands are added to QE
On 13/03/2020 21:57, Philippe Mathieu-Daudé wrote:
On 3/12/20 5:54 PM, Liran Alon wrote:
No functional change. This is mere refactoring.
Suggested-by: Michael S. Tsirkin
Signed-off-by: Liran Alon
---
hw/i386/pc.c | 1 +
hw/i386/vmmouse.c | 1 +
hw/i386/vmport.c
On 3/13/20 12:36 PM, Peter Maydell wrote:
> Raise ConfigError rather than VersionRequirementError when we detect
> that the Python being used by Sphinx is too old.
>
> Currently the way we flag the Python version problem up to the user
> causes Sphinx to print an unnecessary Python stack trace
Le 13/03/2020 à 19:36, Philippe Mathieu-Daudé a écrit :
> Do not build the virtiofsd helper when configured with
> --disable-system.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Makefile | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Makefile b/Makefile
> inde
On Thu, Mar 12, 2020 at 10:26 PM Richard Henderson
wrote:
>
> On 3/12/20 3:10 PM, Alistair Francis wrote:
> >> I still think this must be a guest (or nested guest) bug related to
> >> clearing
> >> PTE bits and failing to flush the TLB properly.
> >
> > It think so as well now. I have changed the
On Thu, Mar 12, 2020 at 8:13 AM LIU Zhiwei wrote:
>
> The unit-stride fault-only-fault load instructions are used to
> vectorize loops with data-dependent exit conditions(while loops).
> These instructions execute as a regular load except that they
> will only take a trap on element 0.
>
> Signed-
Le 13/03/2020 à 23:13, Alistair Francis a écrit :
> On Fri, Mar 13, 2020 at 3:12 PM Alistair Francis wrote:
>>
>> On Fri, Mar 13, 2020 at 1:14 AM Laurent Vivier wrote:
>>>
>>> Le 12/03/2020 à 23:13, Alistair Francis a écrit :
Add support for host and target futex_time64. If futex_time64 exis
On 2020/3/14 6:05, Alistair Francis wrote:
On Fri, Mar 13, 2020 at 2:32 PM LIU Zhiwei wrote:
On 2020/3/14 4:38, Alistair Francis wrote:
On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote:
Vector strided operations access the first memory element at the base address,
and then access subseq
On Fri, 13 Mar 2020, BALATON Zoltan wrote:
The pci_ide_create_devs() function takes a hd_table parameter but all
callers just pass what ide_drive_get() returns so we can do it locally
simplifying callers and removing hd_table parameter.
Signed-off-by: BALATON Zoltan
---
hw/alpha/dp264.c
On Fri, Mar 13, 2020 at 1:14 AM Laurent Vivier wrote:
>
> Le 12/03/2020 à 23:13, Alistair Francis a écrit :
> > Add support for host and target futex_time64. If futex_time64 exists on
> > the host we try that first before falling back to the standard futux
> > syscall.
> >
> > Signed-off-by: Alist
On Fri, Mar 13, 2020 at 3:12 PM Alistair Francis wrote:
>
> On Fri, Mar 13, 2020 at 1:14 AM Laurent Vivier wrote:
> >
> > Le 12/03/2020 à 23:13, Alistair Francis a écrit :
> > > Add support for host and target futex_time64. If futex_time64 exists on
> > > the host we try that first before falling
On 3/13/20 4:54 PM, Markus Armbruster wrote:
I append my hacked up version of auto-propagated-errp.cocci. It
produces the same patch as yours for the complete tree.
// Use ERRP_AUTO_PROPAGATE (see include/qapi/error.h)
//
//
// Usage example:
// spatch --sp-file scripts/coccinelle/auto-p
On Fri, Mar 13, 2020 at 2:32 PM LIU Zhiwei wrote:
>
>
>
> On 2020/3/14 4:38, Alistair Francis wrote:
> > On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote:
> >> Vector strided operations access the first memory element at the base
> >> address,
> >> and then access subsequent elements at address
Le 10/03/2020 à 12:07, Laurent Vivier a écrit :
> This series adds a script to generate syscall_nr.h for
> architectures that don't use syscall.tbl but asm-generic/unistd.h
>
> The script uses several cpp passes and filters result with a grep/sed/tr
> sequence.
> The result must be checked before
It's too late in my day for a full review. Just one observation for
now.
Eric Blake writes:
> We've had all the required pieces for doing a type-safe representation
> of netdev_add as a flat union for quite some time now (since
> 0e55c381f6 in v2.7.0, released in 2016), but did not make the fin
On 3/2/20 4:05 AM, Vladimir Sementsov-Ogievskiy wrote:
NBD driver may has max_pwrite_zeroes but doesn't has
max_pwrite_zeroes_no_fallback limit. This means, that (when
BDRV_REQ_NO_FALLBACK is supported) it is beneficial to try send request
with BDRV_REQ_NO_FALLBACK instead of splitting the reques
Vladimir Sementsov-Ogievskiy writes:
> 13.03.2020 18:42, Markus Armbruster wrote:
>> Vladimir Sementsov-Ogievskiy writes:
>>
>>> 12.03.2020 19:36, Markus Armbruster wrote:
I may have a second look tomorrow with fresher eyes, but let's get this
out now as is.
Vladimir Sementso
Le 10/03/2020 à 11:33, Laurent Vivier a écrit :
> This series copies the files syscall.tbl from linux v5.5 and generates
> the file syscall_nr.h from them.
>
> This is done for all the QEMU targets that have a syscall.tbl
> in the linux source tree: mips, mips64, i386, x86_64, sparc, s390x,
> ppc,
On 2020/3/14 5:41, Alistair Francis wrote:
On Thu, Mar 12, 2020 at 10:00 AM LIU Zhiwei wrote:
Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
"-cpu rv64,v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vect
Le 12/03/2020 à 23:14, Alistair Francis a écrit :
> Signed-off-by: Alistair Francis
> Reviewed-by: Laurent Vivier
> ---
> linux-user/riscv/syscall32_nr.h | 295 +++
> linux-user/riscv/syscall64_nr.h | 301
> linux-user/riscv/syscall_nr
Le 12/03/2020 à 23:13, Alistair Francis a écrit :
> Add support for the clock_gettime64/clock_settime64 syscalls.
>
> If your host is 64-bit or is 32-bit with the *_time64 syscall then the
> timespec will correctly be a 64-bit time_t. Otherwise the host will
> return a 32-bit time_t which will be
On 3/2/20 4:05 AM, Vladimir Sementsov-Ogievskiy wrote:
It's wrong to update head using num in this place, as num may be
reduced during the iteration, and we'll have wrong head value on next
iteration.
Instead update head at iteration end.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Vladimir Semen
Le 12/03/2020 à 23:13, Alistair Francis a écrit :
> New y2038 safe 32-bit architectures (like RISC-V) don't support old
> syscalls with a 32-bit time_t. The kernel defines new *_time64 versions
> of these syscalls. Add some more #ifdefs to syscall.c in linux-user to
> allow us to compile without th
Le 13/03/2020 à 01:28, Lirong Yuan a écrit :
> This change updates TASK_UNMAPPED_BASE (the base address for guest programs)
> for aarch64. It is needed to allow qemu to work with Thread Sanitizer (TSan),
> which has specific boundary definitions for memory mappings on different
> platforms:
> ht
Le 13/03/2020 à 01:28, Lirong Yuan a écrit :
> This change updates TASK_UNMAPPED_BASE (the base address for guest programs)
> for aarch64. It is needed to allow qemu to work with Thread Sanitizer (TSan),
> which has specific boundary definitions for memory mappings on different
> platforms:
> ht
Le 12/03/2020 à 17:55, Laurent Vivier a écrit :
> print_socket_type() doesn't manage flags and the correct type cannot
> be displayed
>
> Signed-off-by: Laurent Vivier
> ---
>
> Notes:
> v2: replace gemu_log() by qemu_log() as it has been removed from qemu
>
> linux-user/strace.c | 8 +
On Thu, Mar 12, 2020 at 10:00 AM LIU Zhiwei wrote:
>
> Vector extension is default off. The only way to use vector extension is
> 1. use cpu rv32 or rv64
> 2. turn on it by command line
> "-cpu rv64,v=true,vlen=128,elen=64,vext_spec=v0.7.1".
>
> vlen is the vector register length, default value is
On 3/12/20 4:22 AM, Denis Plotnikov wrote:
The patch adds some preparation parts for incompatible compression type
feature to qcow2 allowing the use different compression methods for
image clusters (de)compressing.
It is implied that the compression type is set on the image creation and
can be c
On 2020/3/14 4:38, Alistair Francis wrote:
On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote:
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified
There are several definitions of MAX_IDE_BUS in different boards (some
of them unused) with the same value. Move it to include/hw/ide/internal.h
to have it in a central place.
Signed-off-by: BALATON Zoltan
---
hw/alpha/dp264.c | 2 --
hw/hppa/machine.c | 2 --
hw/i386/pc_piix.c
After previous clean ups we can drop direct inclusion of hw/ide.h from
several places.
Signed-off-by: BALATON Zoltan
---
hw/hppa/hppa_sys.h | 1 -
hw/hppa/machine.c | 1 -
hw/i386/pc_piix.c | 1 -
hw/isa/piix4.c | 1 -
hw/mips/mips_fulong2e.c | 1 -
hw/ppc/mac_newworld.
This removes pci_piix3_ide_init() and pci_piix3_xen_ide_init()
functions similar to clean up done to other ide devices.
Signed-off-by: BALATON Zoltan
---
hw/i386/pc_piix.c | 10 +-
hw/ide/pci.c | 1 +
hw/ide/piix.c | 21 +
include/hw/ide.h | 2 --
4 files
We can move it next to the MAX_IDE_BUS define now that less files use
it.
Signed-off-by: BALATON Zoltan
---
include/hw/ide.h | 2 --
include/hw/ide/internal.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/hw/ide.h b/include/hw/ide.h
index d52c211f32..c5ce5
The pci_ide_create_devs() function takes a hd_table parameter but all
callers just pass what ide_drive_get() returns so we can do it locally
simplifying callers and removing hd_table parameter.
Signed-off-by: BALATON Zoltan
---
hw/alpha/dp264.c | 13 +++--
hw/i386/pc_piix.c
After previous patches we don't need hw/pci/pci.h any more in
hw/ide.h. Some files depended on implicit inclusion by this header
which are also fixed up here.
Signed-off-by: BALATON Zoltan
---
hw/ide/ahci_internal.h| 1 +
include/hw/ide.h | 1 -
include/hw/ide/pci.h
This removes pci_piix4_ide_init() function similar to clean up done to
other ide devices.
Signed-off-by: BALATON Zoltan
---
hw/ide/piix.c| 12 +---
hw/isa/piix4.c | 5 -
include/hw/ide.h | 1 -
3 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/hw/ide/piix.c b/hw
These are some clean ups to remove more legacy init functions and
lessen dependence on include/hw/ide.h with some simplifications in
board code. There should be no functional change.
BALATON Zoltan (8):
hw/ide: Get rid of piix3_init functions
hw/ide: Get rid of piix4_init function
hw/ide: Re
Spaces are required around a + operator and if statements should have
braces even for single line. Also make it simpler by reversing the
condition instead of breaking the loop.
Signed-off-by: BALATON Zoltan
---
hw/ide/pci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On Thu, Mar 12, 2020 at 8:11 AM LIU Zhiwei wrote:
>
> Vector indexed operations add the contents of each element of the
> vector offset operand specified by vs2 to the base effective address
> to give the effective address of each element.
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Fran
Patchew URL: https://patchew.org/QEMU/20200313184153.11275-1-phi...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
Patchew URL: https://patchew.org/QEMU/20200313184153.11275-1-phi...@redhat.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export
On 3/2/20 4:05 AM, Vladimir Sementsov-Ogievskiy wrote:
NBD spec is updated, so that max_block doesn't relate to
Maybe: The NBD spec was recently updated to clarify that max_block...
NBD_CMD_WRITE_ZEROES with NBD_CMD_FLAG_FAST_ZERO (which mirrors Qemu
flag BDRV_REQ_NO_FALLBACK). To drop the re
On Fri, 13 Mar 2020, John Snow wrote:
On 3/13/20 4:24 AM, Mark Cave-Ayland wrote:
Following on from the earlier thread "Implement "non 100% native mode"
in via-ide", here is an updated patchset based upon the test cases
sent to me off-list.
The VIA IDE controller is similar to early versions of
On Thu, 12 Mar 2020 23:23:27 +0530
Kirti Wankhede wrote:
> Added a check such that only singleton IOMMU groups can pin pages.
> From the point when vendor driver pins any pages, consider IOMMU group
> dirty page scope to be limited to pinned pages.
>
> To optimize to avoid walking list often, ad
On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote:
>
> Vector strided operations access the first memory element at the base address,
> and then access subsequent elements at address increments given by the byte
> offset contained in the x register specified by rs2.
>
> Vector unit-stride operation
On 3/13/20 7:44 AM, Halil Pasic wrote:
> [..]
>>> CCing Tom. @Tom does vhost-vsock work for you with SEV and current qemu?
>>>
>>> Also, one can specify iommu_platform=on on a device that ain't a part of
>>> a secure-capable VM, just for the fun of it. And that breaks
>>> vhost-vsock. Or is setti
Signed-off-by: Philippe Mathieu-Daudé
---
qapi/machine.json | 20
qapi/misc.json| 21 -
hw/acpi/vmgenid.c | 2 +-
stubs/vmgenid.c | 2 +-
4 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index c
On 3/12/20 5:54 PM, Liran Alon wrote:
This command returns to guest information on LAPIC bus frequency and TSC
frequency.
One can see how this interface is used by Linux vmware_platform_setup()
introduced in Linux commit 88b094fb8d4f ("x86: Hypervisor detection and
get tsc_freq from hypervisor")
On 3/13/20 8:59 PM, Philippe Mathieu-Daudé wrote:
On 3/12/20 5:54 PM, Liran Alon wrote:
No functional change.
Defining an enum for all VMPort commands have the following advantages:
* It gets rid of the error-prone requirement to update VMPORT_ENTRIES
when new VMPort commands are added to QEMU.
On Fri, Mar 13, 2020 at 11:38 AM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> exec.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/exec.c b/exec.c
> index 7bc9828c5b..f258502966 100644
> --- a/exec.c
> ++
On Fri, Mar 13, 2020 at 11:44 AM Philippe Mathieu-Daudé
wrote:
>
> Commit ffaee83bcb2 moved qmp_query_target but forgot to remove
> this include.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> arch_init.c | 1 -
> 1 file changed, 1 deletion(-)
>
> di
On Fri, Mar 13, 2020 at 11:39 AM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>
On Fri, Mar 13, 2020 at 12:37 PM Corey Wharton wrote:
>
> The sifive-e34 cpu type is the same as the sifive-e31 with the
> single precision floating-point extension enabled.
>
> Signed-off-by: Corey Wharton
Reviewed-by: Alistair Francis
Alistair
> ---
> v2: Added missing RVU flag
>
> target/
On 3/12/20 5:54 PM, Liran Alon wrote:
No functional change.
Defining an enum for all VMPort commands have the following advantages:
* It gets rid of the error-prone requirement to update VMPORT_ENTRIES
when new VMPort commands are added to QEMU.
* It makes it clear to know by looking at one plac
On 3/12/20 5:54 PM, Liran Alon wrote:
No functional change. This is mere refactoring.
Suggested-by: Michael S. Tsirkin
Signed-off-by: Liran Alon
---
hw/i386/pc.c | 1 +
hw/i386/vmmouse.c| 1 +
hw/i386/vmport.c | 1 +
include/hw/i386/pc.h | 13 ---
On 3/12/20 5:54 PM, Liran Alon wrote:
vmware-vmx-version is a number returned from CMD_GETVERSION which specifies
to guest VMware Tools the the host VMX version. If the host reports a number
that is different than what the guest VMware Tools expects, it may force
guest to upgrade VMware Tools. (S
On 3/12/20 5:54 PM, Liran Alon wrote:
No functional change.
This is done as a preparation for the following patches that will
introduce several device properties.
Reviewed-by: Nikita Leshenko
Signed-off-by: Liran Alon
---
hw/i386/vmport.c | 6 ++
1 file changed, 6 insertions(+)
diff -
1 - 100 of 312 matches
Mail list logo
