Hi Huacai,
On 4/27/20 11:33 AM, Huacai Chen wrote:
> Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
> R1/R2. Loongson-3A R4 is the newest and its ISA is almost the superset
> of all others. To reduce complexity, we just define a "Loongson-3A" CPU
> which is corresponding to
On 27.04.20 16:03, Eric Blake wrote:
> On 4/27/20 5:00 AM, Max Reitz wrote:
>> On 24.04.20 21:09, Eric Blake wrote:
>>> There are several callers that need to create a new block backend from
>>> an existing BDS; make the task slightly easier with a common helper
>>> routine.
>>>
>>> Suggested-by: M
On 27.04.20 19:59, Dr. David Alan Gilbert wrote:
> * Max Reitz (mre...@redhat.com) wrote:
>> Currently, setup_mounts() bind-mounts the shared directory without
>> MS_REC. This makes all submounts disappear.
>>
>> Pass MS_REC so that the guest can see submounts again.
>
> Thanks!
>
>> Fixes: 3ca8
What is your host machine? And could you please try with the latest
version of QEMU (v5.0)?
** Changed in: qemu
Status: New => Incomplete
** Information type changed from Private Security to Public
--
You received this bug notification because you are a member of qemu-
devel-ml, which is
On 27.04.20 21:26, Denis Plotnikov wrote:
>
>
> On 27.04.2020 15:35, Max Reitz wrote:
>> On 21.04.20 10:11, Denis Plotnikov wrote:
>>> zstd significantly reduces cluster compression time.
>>> It provides better compression performance maintaining
>>> the same level of the compression ratio in com
27.04.2020 18:36, Markus Armbruster wrote:
Markus Armbruster writes:
Markus Armbruster writes:
QEMU's Error was patterned after GLib's GError. Differences include:
[...]
* Return value conventions
Common: non-void functions return a distinct error value on failure
when such a valu
Patchew URL: https://patchew.org/QEMU/20200428022232.18875-1-pauld...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v4 0/7] dwc-hsotg (aka dwc2) USB host controller emulation
Message-id: 20200428022232.18875-1-pauld.
And this one. 3 patches for HAX.
Thanks in advance.
--
Best Regards,
Colin Xu
On Mon, 20 Apr 2020, Colin Xu wrote:
Looks good to me.
Reviewed-by: Colin Xu
--
Best Regards,
Colin Xu
On Mon, 6 Apr 2020, WangBowen wrote:
Dynamic allocating vcpu state structure according to smp value to b
Hi Paolo,
Would you also help queue this one for PULL?
--
Best Regards,
Colin Xu
On Mon, 20 Apr 2020, Colin Xu wrote:
Looks good to me.
Reviewed-by: Colin Xu
--
Best Regards,
Colin Xu
On Fri, 10 Apr 2020, WangBowen wrote:
This commit tried to obtain max vcpu of haxm driver by calling
HA
Hi Paolo,
Would you please queue this one?
--
Best Regards,
Colin Xu
On Mon, 30 Mar 2020, Colin Xu wrote:
Looks good to me.
Reviewed-by: Colin Xu
On 2020-03-30 11:25, hang.y...@linux.intel.com wrote:
From: Hang Yuan
Add ROM and ROM device memory region support in HAX. Their memory regi
Patchew URL:
https://patchew.org/QEMU/20200428012810.10877-1-vishal.l.ve...@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/3] account for NVDIMM nodes during SRAT generation
Message-id: 20200428012810.10877-1-visha
The dwc-hsotg (dwc2) USB host depends on a short packet to
indicate the end of an IN transfer. The usb-storage driver
currently doesn't provide this, so fix it.
I have tested this change rather extensively using a PC
emulation with xhci, ehci, and uhci controllers, and have
not observed any regres
Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test
Signed-off-by: Paul Zimmerman
---
tests/acceptance/boot_linux_console.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acce
Add the dwc-hsotg (dwc2) USB host controller emulation code.
Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.
Note that to use this with the dwc-otg driver in the Raspbian
kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on
the kernel command line.
Emulation of slave mode and of descr
Wire the dwc-hsotg (dwc2) emulation into Qemu
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 21 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bc
Import the dwc-hsotg (dwc2) register definitions file from the
Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
mainline Linux kernel, the only changes being two instances of
'u32' changed to 'uint32_t' to allow it to compile.
Signed-off-by: Paul Zimmerman
---
include/hw/usb/dwc2-
Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.h | 173 ++
1 file changed, 173 insertions(+)
create mode 100644 hw/usb/hcd-dwc2.h
diff --git a/hw/us
This patch series adds emulation for the dwc-hsotg USB controller,
which is used on the Raspberry Pi 3 and earlier, as well as a number
of other development boards. The main benefit for Raspberry Pi is that
this enables networking on these boards, since the network adapter is
attached via USB.
The
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 17 +++
Request for a vote.
Fixes: https://github.com/oasis-tcs/virtio-spec/issues/76
Thanks,
David
On Fri, Mar 20, 2020 at 3:41 PM Gerd Hoffmann wrote:
>
> On Thu, Mar 19, 2020 at 11:18:21AM +0900, David Stevens wrote:
> > Hi all,
> >
> > This is the next iteration of patches for adding support for sh
Update the expected SRAT files for the change to account for NVDIMM numa
nodes in the SRAT.
AML Diff:
--- /tmp/asl-V49YJ0.dsl 2020-04-27 18:50:52.680043327 -0600
+++ /tmp/asl-48AZJ0.dsl 2020-04-27 18:50:52.679043344 -0600
@@ -3,7 +3,7 @@
* AML/ASL+ Disassembler version 201905
In anticipation of a change to the SRAT generation in qemu, add the AML
file to diffs-allowed.
Signed-off-by: Vishal Verma
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-te
NVDIMMs can belong to their own proximity domains, as described by the
NFIT. In such cases, the SRAT needs to have Memory Affinity structures
in the SRAT for these NVDIMMs, otherwise Linux doesn't populate node
data structures properly during NUMA initialization. See the following
for an example fa
On the command line, one can specify a NUMA node for NVDIMM devices. If
we set up the topology to give NVDIMMs their own nodes, i.e. not
containing any CPUs or regular memory, qemu doesn't populate SRAT memory
affinity structures for these nodes. However the NFIT does reference
those proximity doma
On Mon, Apr 27, 2020 at 11:37:43PM +0800, Dr. David Alan Gilbert wrote:
> * Yan Zhao (yan.y.z...@intel.com) wrote:
> > On Sat, Apr 25, 2020 at 03:10:49AM +0800, Dr. David Alan Gilbert wrote:
> > > * Yan Zhao (yan.y.z...@intel.com) wrote:
> > > > On Tue, Apr 21, 2020 at 08:08:49PM +0800, Tian, Kevin
From: Alexander Duyck
Add support for free page reporting. The idea is to function very similar
to how the balloon works in that we basically end up madvising the page as
not being used. However we don't really need to bother with any deflate
type logic since the page will be faulted back into th
From: Alexander Duyck
We need to make certain to advertise support for page poison reporting if
we want to actually get data on if the guest will be poisoning pages.
Add a value for reporting the poison value being used if page poisoning is
enabled in the guest. With this we can determine if we
From: Alexander Duyck
Sync the latest upstream changes for free page reporting. To be
replaced by a full linux header sync.
Signed-off-by: Alexander Duyck
---
include/standard-headers/linux/virtio_balloon.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/standard-headers/linux/v
From: Alexander Duyck
In an upcoming patch a feature named Free Page Reporting is about to be
added. In order to avoid any confusion we should drop the use of the word
'report' when referring to Free Page Hinting. So what this patch does is go
through and replace all instances of 'report' with 'h
This series provides an asynchronous means of reporting free guest pages
to QEMU through virtio-balloon so that the memory associated with those
pages can be dropped and reused by other processes and/or guests on the
host. Using this it is possible to avoid unnecessary I/O to disk and
greatly impro
From: Alexander Duyck
Sync to the latest upstream changes for free page hinting. To be
replaced by a full linux header sync.
Signed-off-by: Alexander Duyck
---
include/standard-headers/linux/virtio_balloon.h | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/incl
On Mon, Apr 27, 2020 at 11:23 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Add support for SD.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c | 31 +++
> include/hw/arm/xlnx-versal
On Mon, Apr 27, 2020 at 11:20 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Embedd the APUs into the SoC type.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal-virt.c| 4 ++--
> hw/arm/
On Mon, Apr 27, 2020 at 11:22 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Embedd the ADMAs into the SoC type.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c | 14 +++---
On Mon, Apr 27, 2020 at 11:20 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Fix typo xlnx-ve -> xlnx-versal.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal-virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Mon, Apr 27, 2020 at 11:20 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Embedd the GEMs into the SoC type.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c | 15 ---
On Mon, Apr 27, 2020 at 11:17 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Embedd the UARTs into the SoC type.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c | 12 ++--
>
On Sat, Apr 18, 2020 at 11:01 AM Jose Martins wrote:
>
> When vs interrupts (2, 6, 10) are enabled, pending and not delegated
> in hideleg, they are not always forwarded to hs mode after a return to
> vs mode. This happens independently of the state of spie and sie on
> the hs-level sstatus before
Signed-off-by: Stephen Long
---
target/arm/crypto_helper.c | 36 +---
target/arm/sve.decode | 10 ++
target/arm/translate-sve.c | 20
3 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/target/arm/crypto_helper.c b/tar
Signed-off-by: Stephen Long
---
target/arm/crypto_helper.c | 12
target/arm/helper-sve.h| 1 +
target/arm/helper.h| 2 ++
target/arm/sve.decode | 4
target/arm/sve_helper.c| 8
target/arm/translate-sve.c | 30 ++
6 fi
Signed-off-by: Stephen Long
---
target/arm/cpu.h | 5 +
target/arm/crypto_helper.c | 38 ++
target/arm/helper-sve.h| 2 ++
target/arm/sve.decode | 6 ++
target/arm/sve_helper.c| 8
target/arm/translate-sve.c | 14
Modified some of the crypto functions in crypto_helper.c to take in a
desc parameter.
Didn't add a desc parameter to SM4E and SM4EKEY since it is used in
translate-a64.c and the functions in there need crypto_sm4e and
crypto_sm4ekey to stay the same type (i.e. take 2 or 3 parameters)
Stephen Long
I am confusing why only inexact are set then we can use hard-float.
And PPC always clearing inexact flag before calling to soft-float
funcitons. so we can not
optimize it with hard-float.
I need some resouces about ineact flag and why always clearing inexcat in
PPC FP simualtion.
I am looking fo
Patchew URL:
https://patchew.org/QEMU/20200427201120.1500504-1-aman...@gmail.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
exp
On Mon, Apr 27, 2020 at 1:11 PM Amanieu d'Antras wrote:
>
> These now match the field layout used by the kernel.
>
> Signed-off-by: Amanieu d'Antras
Thanks for the patch!
Unfortunately this fixed has already been applied to the RISC-V tree
(https://github.com/alistair23/qemu/tree/riscv-to-apply
On 4/27/20 10:31 AM, Eric Auger wrote:
Instead of using a compat in the mach-virt machine to force
PPI off for all virt machines (PPI not supported by the
tpm-tis-device device), let's simply change the default value
in the sysbus device.
There is no change in behavior on any arm machine due to
On Mon, Apr 27, 2020 at 11:25 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Move misplaced comment.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Mon, Apr 27, 2020 at 11:17 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Remove inclusion of arm_gicv3_common.h, this already gets
> included via xlnx-versal.h.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c | 1 -
These now match the field layout used by the kernel.
Signed-off-by: Amanieu d'Antras
---
linux-user/riscv/signal.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index 83ecc6f799..2b15e32a7b 100644
--- a/linux-user/r
Patchew URL: https://patchew.org/QEMU/20200427182440.92433-1-jus...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
On 27.04.2020 15:35, Max Reitz wrote:
On 21.04.20 10:11, Denis Plotnikov wrote:
zstd significantly reduces cluster compression time.
It provides better compression performance maintaining
the same level of the compression ratio in comparison with
zlib, which, at the moment, is the only compre
* Cédric Le Goater (c...@kaod.org) wrote:
> From: "Dr. David Alan Gilbert"
>
> Reimplement it based on qmp_qom_get() to avoid converting QObjects back
> to strings.
I'd love to see this or something similar in; what does it's output
look like for structures - I think that was the main problem
* Adalbert Lazăr (ala...@bitdefender.com) wrote:
> From: Marian Rotariu
>
> It is possible that the introspection tool has made some changes inside
> the introspected VM which can make the guest crash if the introspection
> connection is suddenly closed.
>
> When the live migration starts, for n
On Mon, 27 Apr 2020 at 17:45, Richard Henderson
wrote:
> We *can* indicate fault from MemSingleNF for any reason whatsoever, or no
> reason whatsoever.
>
> > // Implementation may suppress NF load for any reason
> > if ConstrainUnpredictableBool(Unpredictable_NONFAULT) then
> > return (bits(8*si
A little cleanup is possible because of hotplug_pdev introduction.
Signed-off-by: Julia Suvorova
---
hw/pci/pcie.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 6b48d04d2c..abc99b6eff 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@
From: "Edgar E. Iglesias"
Add support for the RTC.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 0afee48672..7e749e1926 100644
--- a/hw/arm/x
Raise an error when trying to hot-plug/unplug a device through QMP to a device
with disabled hot-plug capability. This makes the device behaviour more
consistent and provides an explanation of the failure in the case of
asynchronous unplug.
Signed-off-by: Julia Suvorova
---
v2:
* Change error
Julia Suvorova (2):
hw/pci/pcie: Forbid hot-plug if it's disabled on the slot
hw/pci/pcie: Replace PCI_DEVICE() casts with existing variable
hw/pci/pcie.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
--
2.25.3
From: "Edgar E. Iglesias"
Move misplaced comment.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index c73b2fe755..cc696e44c0 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/ar
From: "Edgar E. Iglesias"
Add support for SD.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 46 +++
1 file changed, 46 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index d7be1ad494..0afee48672 100644
--
From: "Edgar E. Iglesias"
Embedd the ADMAs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 14 +++---
include/hw/arm/xlnx-versal.h | 3 ++-
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/hw/arm/xlnx-ve
From: "Edgar E. Iglesias"
Add support for SD.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 31 +++
include/hw/arm/xlnx-versal.h | 12
2 files changed, 43 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
inde
From: "Edgar E. Iglesias"
hw/arm: versal: Add support for the RTC.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 21 +
include/hw/arm/xlnx-versal.h | 8
2 files changed, 29 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal
From: "Edgar E. Iglesias"
Embedd the GEMs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 15 ---
include/hw/arm/xlnx-versal.h | 3 ++-
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/arm/xlnx-v
From: "Edgar E. Iglesias"
Fix typo xlnx-ve -> xlnx-versal.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 878a275140..8a608074d1 100644
--- a/hw/arm/x
From: "Edgar E. Iglesias"
Embedd the APUs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c| 4 ++--
hw/arm/xlnx-versal.c | 19 +--
include/hw/arm/xlnx-versal.h | 2 +-
3 files changed, 8 insertions(+),
From: "Edgar E. Iglesias"
Embedd the UARTs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 12 ++--
include/hw/arm/xlnx-versal.h | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/arm/xlnx-vers
From: "Edgar E. Iglesias"
This series starts with some basic cleaning, continues with embedding
devices into the Versal SoC (as suggested by Peter in another review).
We then connect SD and the RTC to the Versal SoC and hook it all up
into the Versal Virt board.
Cheers,
Edgar
Edgar E. Iglesias
From: "Edgar E. Iglesias"
Remove inclusion of arm_gicv3_common.h, this already gets
included via xlnx-versal.h.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 94460f2343..c73b2fe755
On Mon 27 Apr 2020 09:49:00 AM CEST, Max Reitz wrote:
>> The point is this: Consider 'write -P 0xff 0 64k', then 'write -z 16k
>> 16k', then 'read 0 64k'. For normal clusters, we can just do a
>> scatter-gather iov read of read 0-16k and 32-64k, plus a memset of
>> 16-32k. But for compressed cluste
Patchew URL: https://patchew.org/QEMU/20200427152148.283771-1-and...@daynix.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
* Max Reitz (mre...@redhat.com) wrote:
> Currently, setup_mounts() bind-mounts the shared directory without
> MS_REC. This makes all submounts disappear.
>
> Pass MS_REC so that the guest can see submounts again.
Thanks!
> Fixes: 3ca8a2b1c83eb185c232a4e87abbb65495263756
Should this actually be
Patchew URL: https://patchew.org/QEMU/20200427152148.283771-1-and...@daynix.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
expor
On 4/27/20 9:32 AM, Peter Maydell wrote:
+ * From this point on, all memory operations are MemSingleNF.
+ *
+ * Per the MemSingleNF pseudocode, a no-fault load from Device memory
+ * must not actually hit the bus -- it returns (UNKNOWN, FAULT)
instead.
On Mon, 27 Apr 2020 at 17:16, Richard Henderson
wrote:
>
> On 4/27/20 4:03 AM, Peter Maydell wrote:
> > On Wed, 22 Apr 2020 at 05:33, Richard Henderson
> > wrote:
> >>
> >> With sve_cont_ldst_pages, the differences between first-fault and no-fault
> >> are minimal, so unify the routines. With cp
On 4/27/20 4:03 AM, Peter Maydell wrote:
> On Wed, 22 Apr 2020 at 05:33, Richard Henderson
> wrote:
>>
>> With sve_cont_ldst_pages, the differences between first-fault and no-fault
>> are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
>> to make progress through pages with
On Mon, Mar 30, 2020 at 10:03:56PM +0100, Peter Maydell wrote:
> This is obviously not 5.0 material, but I figured it would be better
> to push it out for review now rather than hang on to it and forget...
>
> TTS2UXN is an ARMv8.2 extension which changes the 'XN' field in stage
> 2 translation ta
On 4/27/20 3:48 AM, Peter Maydell wrote:
> probe_access() handles watchpoints. Why doesn't probe_access_flags()
> have to do that?
Because we are explicitly deferring that work to the caller. That's a good
fraction of the point of the new interface.
>> +/* Handle clean RAM pages. */
>>
On 27.04.20 17:57, Alexander Duyck wrote:
> On Mon, Apr 27, 2020 at 8:11 AM David Hildenbrand wrote:
>>
>> On 27.04.20 17:08, Alexander Duyck wrote:
>>> On Mon, Apr 27, 2020 at 1:15 AM David Hildenbrand wrote:
There is only one wrong comment remaining I think. Something like
d
On Mon, Apr 27, 2020 at 8:11 AM David Hildenbrand wrote:
>
> On 27.04.20 17:08, Alexander Duyck wrote:
> > On Mon, Apr 27, 2020 at 1:15 AM David Hildenbrand wrote:
> >>
> >> There is only one wrong comment remaining I think. Something like
> >>
> >> diff --git a/hw/virtio/virtio-balloon.c b/hw/vi
Am 24.04.2020 um 14:54 hat Kevin Wolf geschrieben:
> v7:
> - Allocate smaller zero buffer [Vladimir]
> - Added missing error_setg_errno() [Max]
> - Code cleanup in the iotest, enabled mapping for 'metadata' [Vladimir]
> - Don't assign to errp twice [Eric]
Thanks for the review, applied to the bloc
* Yan Zhao (yan.y.z...@intel.com) wrote:
> On Sat, Apr 25, 2020 at 03:10:49AM +0800, Dr. David Alan Gilbert wrote:
> > * Yan Zhao (yan.y.z...@intel.com) wrote:
> > > On Tue, Apr 21, 2020 at 08:08:49PM +0800, Tian, Kevin wrote:
> > > > > From: Yan Zhao
> > > > > Sent: Tuesday, April 21, 2020 10:37 A
Markus Armbruster writes:
> Markus Armbruster writes:
>
>> QEMU's Error was patterned after GLib's GError. Differences include:
> [...]
>> * Return value conventions
>>
>> Common: non-void functions return a distinct error value on failure
>> when such a value can be defined. Patterns:
>>
Signed-off-by: Stephen Long
---
target/arm/helper-sve.h| 3 +++
target/arm/sve.decode | 4
target/arm/sve_helper.c| 20
target/arm/translate-sve.c | 30 ++
4 files changed, 57 insertions(+)
diff --git a/target/arm/helper-sve.h
Signed-off-by: Stephen Long
---
target/arm/helper-sve.h| 3 +++
target/arm/sve.decode | 10 ++
target/arm/sve_helper.c| 15 +++
target/arm/translate-sve.c | 18 ++
4 files changed, 46 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/ar
Used one macro to cover the helper functions for
SVE2 AESC, AESIMC, AESE, AESD.
No macro was used to implement the helper functions for
SM4E, SM4EKEY, RAX1.
Stephen Long (3):
target/arm: Implement SVE2 AESMC, AESIMC
target/arm: Implement SVE2 AESE, AESD, SM4E
target/arm: Implement SVE2 SM4E
Signed-off-by: Stephen Long
---
target/arm/cpu.h | 5 +
target/arm/helper-sve.h| 4
target/arm/sve.decode | 6 ++
target/arm/sve_helper.c| 11 +++
target/arm/translate-sve.c | 16
5 files changed, 42 insertions(+)
diff --git a/targe
On Mon, Apr 27, 2020 at 04:41:38PM +0200, Philippe Mathieu-Daudé wrote:
> On 4/27/20 4:28 PM, Cleber Rosa wrote:
> > On Mon, 27 Apr 2020 12:51:36 +0200
> > Philippe Mathieu-Daudé wrote:
> >
> > > On 4/27/20 7:12 AM, Cleber Rosa wrote:
> > > > On Thu, 23 Apr 2020 23:28:21 +0200
> > > > Philippe Ma
On Mon, 27 Apr 2020 16:41:38 +0200
Philippe Mathieu-Daudé wrote:
> On 4/27/20 4:28 PM, Cleber Rosa wrote:
> >
> > What I mean is: would you blame such a developer for *not* having a
> > machine himself/herself that he/she can try to reproduce the
> > failure? And would you consider a "Raspberry
On Mon, Apr 27, 2020 at 1:07 AM Anup Patel wrote:
>
> This series improves QEMU Spike machine to:
> 1. Allow loading OpenBI firmware using -bios option
> 2. Allow more than one CPUs
>
> Changes since v2:
> - Rebased on QEMU v5.0-rc4
>
> Changes since v1:
> - Rebased on QEMU master (commit 2ac031
On Mon, Apr 27, 2020 at 1:09 AM Anup Patel wrote:
>
> This patch adds an optional function pointer, "sym_cb", to
> riscv_load_firmware() which provides the possibility to access
> the symbol table during kernel loading.
>
> The pointer is ignored, if supplied with flat (non-elf) firmware image.
>
On Mon, Apr 27, 2020 at 1:21 AM David Hildenbrand wrote:
>
> Except one minor nit, looks good to me. We'll have to take care of
> compat handling regarding patch #4 as soon as we have 5.0 compat
> machines in place.
I will clean up the one comment and submit later today if there is no
other follo
On 27.04.20 17:08, Alexander Duyck wrote:
> On Mon, Apr 27, 2020 at 1:15 AM David Hildenbrand wrote:
>>
>> There is only one wrong comment remaining I think. Something like
>>
>> diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
>> index a1d6fb52c8..1b2127c04c 100644
>> --- a/hw
On Mon, Apr 27, 2020 at 1:08 AM Anup Patel wrote:
>
> This patch extends Spike machine support to allow loading OpenSBI
> firmware (fw_jump.elf) separately using -bios option.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/spike.c | 24 +
On Mon, Apr 27, 2020 at 1:09 AM Anup Patel wrote:
>
> Currently, the upstream Spike ISA simulator allows more than
> one CPUs so we update QEMU Spike machine on similar lines to
> allow more than one CPUs.
>
> The maximum number of CPUs for QEMU Spike machine is kept
> same as QEMU Virt machine.
>
On Mon, Apr 27, 2020 at 1:15 AM David Hildenbrand wrote:
>
> There is only one wrong comment remaining I think. Something like
>
> diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
> index a1d6fb52c8..1b2127c04c 100644
> --- a/hw/virtio/virtio-balloon.c
> +++ b/hw/virtio/virtio-
From: Andrew Melnychenko
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Added ICR clearing if there is IMS bit - according to the note by
section 13.3.27 of the 8257X developers manual.
Signed-off-by: Andrew Melnychenko
---
hw/net/e1000e_core.c | 9 +
hw/net/trace-events
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Stefan Hajnoczi
---
block/io.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/block/io.c b/block/io.c
index 94ab8eaa0f..880871e691 100644
--- a/block/io.c
+++ b/block/io.c
@@ -3125,31 +3125,38
We'll need a bdrv_co_pwrite_zeroes version without inc/dec in_flight to
be used in further implementation of bdrv_make_zero.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Stefan Hajnoczi
---
block/io.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
di
We are going to use bdrv_co_pwritev_part and bdrv_co_preadv_part in
bdrv_rw_co_entry, so move it down.
Note: Comment formatting was changed to conform to coding style and
function order was changed. Otherwise the code is unmodified.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Stefan
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