Paolo Bonzini writes:
> Are we sure that qdev_realize is never called with user-provided input? If
The only way to call qdev_realize() with a user-provided bus is -device
/ device_add via qdev_device_add(). qdev_device_add() carefully checks
the user-provided bus before passing it to qdev_reali
In production, the VM with insentive memory activity maybe failed to migrate,
because of the change of memory in the VM greater than the throughtput of the
network interface, and we want to identify it before migration.
1. dirty tracking start:
virsh qemu-monitor-command --hmp dirty_track
2. wai
From: Klaus Jensen
Bump the supported NVM Express version to v1.3.
Signed-off-by: Klaus Jensen
Reviewed-by: Maxim Levitsky
Reviewed-by: Dmitry Fomichev
---
hw/block/nvme.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index e39841579
From: Klaus Jensen
0x is not an allowed value for NCQR and NSQR in Set Features on
Number of Queues.
Signed-off-by: Klaus Jensen
Acked-by: Keith Busch
Reviewed-by: Maxim Levitsky
Reviewed-by: Dmitry Fomichev
---
hw/block/nvme.c | 8
1 file changed, 8 insertions(+)
diff --git a
From: Klaus Jensen
The NvmeFeatureVal does not belong with the spec-related data structures
in include/block/nvme.h that is shared between the block-level nvme
driver and the emulated nvme device.
Move it into the nvme device specific header file as it is the only
user of the structure. Also, re
From: Klaus Jensen
Reject the nsid broadcast value (0x) and 0xfffe in the
Active Namespace ID list.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index fc58f3d76530..af39126cd8d1 100
From: Klaus Jensen
Add support for the Asynchronous Event Request command. Required for
compliance with NVMe revision 1.3d. See NVM Express 1.3d, Section 5.2
("Asynchronous Event Request command").
Mostly imported from Keith's qemu-nvme tree. Modified with a max number
of queued events (controll
From: Klaus Jensen
Since we are not providing the NGUID or EUI64 fields, we must support
the Namespace UUID. We do not have any way of storing a persistent
unique identifier, so conjure up a UUID that is just the namespace id.
Signed-off-by: Klaus Jensen
Reviewed-by: Dmitry Fomichev
---
hw/bl
From: Klaus Jensen
Add missing fields in the Identify Controller and Identify Namespace
data structures to bring them in line with NVMe v1.3.
This also adds data structures and defines for SGL support which
requires a couple of trivial changes to the nvme block driver as well.
Signed-off-by: Kl
From: Klaus Jensen
Support returning Command Sequence Error if Set Features on Number of
Queues is called after queues have been created.
Signed-off-by: Klaus Jensen
Reviewed-by: Maxim Levitsky
Reviewed-by: Dmitry Fomichev
---
hw/block/nvme.c | 12
hw/block/nvme.h | 1 +
2 file
From: Klaus Jensen
The SUBNQN field is mandatory in NVM Express 1.3.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 07d58aa945f2..e3984157926b 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@
From: Klaus Jensen
Add support for any remaining mandatory controller operating parameters
(features).
Signed-off-by: Klaus Jensen
Reviewed-by: Dmitry Fomichev
---
hw/block/nvme.c | 56 ++-
hw/block/trace-events | 2 ++
include/block/nvme.h | 10
From: Klaus Jensen
Mark firmware slot 1 as read-only and only support that slot.
Signed-off-by: Klaus Jensen
Reviewed-by: Dmitry Fomichev
---
hw/block/nvme.c | 3 ++-
include/block/nvme.h | 4
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/n
From: Klaus Jensen
If the write cache is disabled with a Set Features command, flush it if
currently enabled.
Signed-off-by: Klaus Jensen
Reviewed-by: Dmitry Fomichev
---
hw/block/nvme.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 80c7285bc1
From: Klaus Jensen
Since the device does not have any persistent state storage, no
features are "saveable" and setting the Save (SV) field in any Set
Features command will result in a Feature Identifier Not Saveable status
code.
Similarly, if the Select (SEL) field is set to request saved values
From: Klaus Jensen
It might seem weird to implement this feature for an emulated device,
but it is mandatory to support and the feature is useful for testing
asynchronous event request support, which will be added in a later
patch.
Signed-off-by: Klaus Jensen
Acked-by: Keith Busch
Reviewed-by:
From: Klaus Jensen
Fix a missing cpu_to conversion by moving conversion to just before
returning instead.
Signed-off-by: Klaus Jensen
Suggested-by: Philippe Mathieu-Daudé
---
hw/block/nvme.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/n
From: Klaus Jensen
Required for compliance with NVMe revision 1.3d. See NVM Express 1.3d,
Section 5.1 ("Abort command").
The Abort command is a best effort command; for now, the device always
fails to abort the given command.
Signed-off-by: Klaus Jensen
Signed-off-by: Klaus Jensen
Acked-by: K
From: Klaus Jensen
This adds mandatory features of NVM Express v1.3 to the emulated NVMe
device.
v3:
* hw/block/nvme: additional tracing
- Reverse logic in nvme_cid(). (Philippe)
- Move nvme_cid() and nvme_sqid() to source file. (Philippe)
* hw/block/nvme: fix missing endian convers
From: Klaus Jensen
Add support for the Get Log Page command and basic implementations of
the mandatory Error Information, SMART / Health Information and Firmware
Slot Information log pages.
In violation of the specification, the SMART / Health Information log
page does not persist information ov
From: Klaus Jensen
Add various additional tracing and streamline nvme_identify_ns and
nvme_identify_nslist (they do not need to repeat the command, it is
already in the trace name).
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 33 +
hw/block/trace-eve
Ping.
On 26.06.2020 13:19, Pavel Dovgalyuk wrote:
GDB remote protocol supports reverse debugging of the targets.
It includes 'reverse step' and 'reverse continue' operations.
The first one finds the previous step of the execution,
and the second one is intended to stop at the last breakpoint th
Vladimir Sementsov-Ogievskiy writes:
> Introduce a new ERRP_AUTO_PROPAGATE macro, to be used at start of
> functions with an errp OUT parameter.
>
> It has three goals:
>
> 1. Fix issue with error_fatal and error_prepend/error_append_hint: user
> can't see this additional information, because exi
Peter Maydell writes:
> On Tue, 30 Jun 2020 at 14:39, Philippe Mathieu-Daudé wrote:
>>
>> As we have no interest in the underlying block geometry,
>> directly call blk_getlength(). We have to care about machines
>> creating SD card with not drive attached (probably incorrect
>> API use). Simply
Hi,
I patched configure file and makefile. The output is listed below.
The project is configured as :
#../configure --target-list=dsp-softmmu --cross-prefix=x86_64-w64-mingw32-
--enable-gtk --enable-sdl --enable-debug --enable-plugins
--extra-cflags="-DBUILDING_DLL"
But running make ye
On 04.07.20 20:34, Michael S. Tsirkin wrote:
> On Tue, Jun 16, 2020 at 06:50:34AM +0200, Halil Pasic wrote:
>> The atomic_cmpxchg() loop is broken because we occasionally end up with
>> old and _old having different values (a legit compiler can generate code
>> that accessed *ind_addr again to p
Vladimir Sementsov-Ogievskiy writes:
> If we want to add some info to errp (by error_prepend() or
> error_append_hint()), we must use the ERRP_AUTO_PROPAGATE macro.
> Otherwise, this info will not be added when errp == &error_fatal
> (the program will exit prior to the error_append_hint() or
> er
On Sun, Jul 05, 2020 at 07:22:11PM +0200, BALATON Zoltan wrote:
> Several callers of load_elf() pass pointers for lowaddr and highaddr
> parameters which are then not used for anything. This may stem from a
> misunderstanding that load_elf need a value here but in fact it can
> take NULL to ignore
Public bug reported:
Hello,
This reproducer causes a heap-use-after free. QEMU Built with
--enable-sanitizers:
cat << EOF | ./i386-softmmu/qemu-system-i386 -M q35,accel=qtest \
-qtest stdio -nographic -monitor none -serial none
outl 0xcf8 0x80001010
outl 0xcfc 0xe102
outl 0xcf8 0x80001014
out
On Sun, 28 Jun 2020, at 23:56, erik-smit wrote:
> The test of the write of the dblac register was testing the old value
> instead of the new value. This would accept the write of an invalid value
> but subsequently refuse any following valid writes.
>
> Signed-off-by: erik-smit
> ---
> Changes
When NMI is configured it is taken regardless of INTENABLE SR contents,
PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken.
Add nmi_level to XtensaConfig, puth there NMI level from the overlay or
XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to
INTENABLE SR and
On Mon, 6 Jul 2020, at 08:11, Philippe Mathieu-Daudé wrote:
> All the callers of aspeed_i2c_get_bus() have a AspeedI2CState and
> cast it to a DeviceState with DEVICE(), then aspeed_i2c_get_bus()
> cast the DeviceState to an AspeedI2CState with ASPEED_I2C()...
>
> Simplify aspeed_i2c_get_bus()
在 2020/7/3 18:44, Stefan Brankovic 写道:
Add disassembler for Loongson 2F instruction set.
Testing is done by comparing qemu disassembly output, obtained by
using -d in_asm command line option, with appropriate objdump output.
This disassembler is written as a generic disassembler that can be
Maybe below patch will reduce some overhead, because currently it will exit to
main loop to handle interrupt but if with (env->regs[CR_STATUS] &
CR_STATUS_PIE) = False, it does nothing except set env->irq_pending again.
diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c
index 1c1989d5..5ea7e52
Thanks, I think we can get this series merged currently.
-Original Message-
From: Peter Maydell
Sent: Monday, July 6, 2020 1:10 AM
To: Wu, Wentong
Cc: QEMU Developers ; QEMU Trivial
; Chris Wulff ; Marek Vasut
Subject: Re: [PATCH 3/3] target/nios2: Use gen_io_start around wrctl instr
This instruction aims to give a way to choose which memory accesses
do not need to be tracked in the TSX read set, which is defined as
CPUID.(EAX=7,ECX=0):EDX[bit 16].
The release spec link is as follows:
https://software.intel.com/content/dam/develop/public/us/en/documents/\
architecture-instruct
The availability of the SERIALIZATION instruction is indicated
by the presence of the CPUID feature flag SERIALIZE, which is
defined as CPUID.(EAX=7,ECX=0):ECX[bit 14].
The release spec link is as follows:
https://software.intel.com/content/dam/develop/public/us/en/documents/\
architecture-instruc
This patchset is to add two new features for intel processors
which support them, like Sapphire Rapids. SERIALIZE is a faster
serializing instruction which does not modify registers,
arithmetic flags or memory, will not cause VM exit. TSX suspend
load tracking instruction aims to give a way to choo
We use "create_simple" names for functions that allocate, initialize,
configure and realize device objects: pci_create_simple(),
isa_create_simple(), usb_create_simple(). For consistency, rename
i2c_create_slave() as i2c_slave_create_simple(). Since we have
to update all the callers, also let it re
In commit d88c42ff2c we added new prototype but neglected to
add their documentation. Fix that.
Reported-by: Peter Maydell
Reviewed-by: Corey Minyard
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i2c/i2c.h | 48
1 file changed, 48 insertions(
We use "new" names for functions that allocate and initialize
device objects: pci_new(), isa_new(), usb_new().
Let's call this one i2c_slave_new(). Since we have to update
all the callers, also let it return a I2CSlave object.
Suggested-by: Markus Armbruster
Reviewed-by: Markus Armbruster
Signed
All the callers of aspeed_i2c_get_bus() have a AspeedI2CState and
cast it to a DeviceState with DEVICE(), then aspeed_i2c_get_bus()
cast the DeviceState to an AspeedI2CState with ASPEED_I2C()...
Simplify aspeed_i2c_get_bus() callers by using AspeedI2CState
argument.
Reviewed-by: Markus Armbruster
The other i2c functions are called i2c_slave_FOO(). Rename as
i2c_slave_realize_and_unref() to be consistent.
Suggested-by: Markus Armbruster
Reviewed-by: Corey Minyard
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i2c/i2c.h | 2 +-
hw/arm/aspeed.c | 10 ++
hw/i2c/core.c
In commit d88c42ff2c we added 2 methods: i2c_try_create_slave()
and i2c_realize_and_unref().
Markus noted their name could be improved for consistency [1],
and Peter reported the lack of documentation [2]. Fix that now.
Since v1:
- Addressed Markus review comments
- Added Markus/Corey R-b tags
[1
Since commit 510ef98dca5, qdev_realize() aborts if bus-less
device is realized on a bus. Be kind with the developer by
displaying a hint about what is wrong.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Use errp (bonzini suggestion)
Paolo, I was tempted to check errp is really &error_abort else
SD cards be used with SPI, SD or MMC protocol.
Unfortunately, maintaining the SPI protocol make improving the
MMC mode very difficult. As of 2020 users are more interested
in using cards with the MMC protocol.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/system/deprecated.rst | 5 +
1 fil
This device duplicate the SPI mode of the sd-card device. The
SPI protocol is better handler in the sd-card, however as the
TYPE_SSI_SLAVE is not an interface, the sd-card can not implement
it easily to be pluggable on a SPI bus. Meanwhile the ssi-sd
device acts as a bridge, but is bitroting. Depre
I tried to maintain the SPI mode because it is useful in
tiny embedded devices, and thought it would be helpful for
the AVR MCUs.
As AVR was blocked, I thought it was wise to deprecate the
SPI mode as users are interested in the faster MMC mode.
Today Thomas surprised me by posting an update of it!
Avoid declaring PXA2xxMMCIState local variable, return it directly.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pxa2xx_mmci.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
index 9482b9212d..2996a2ef17 100644
--- a/hw/sd/pxa2x
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :) Let the machine/board object
create and plug the SD cards when required.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/pxa.h | 3 +--
hw/arm/pxa2xx.c | 39 +
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in
This series move the SD card creation to the machine/board code.
Regards,
Phil.
Philippe Mathieu-Daudé (2):
hw/sd/pxa2xx_mmci: Do not create SD card within the SDHCI controller
hw/sd/pxa2xx_mmci: Tri
On 7/5/20 4:03 PM, Thomas Huth wrote:
> From: Michael Rolnik
>
> Make AVR support buildable.
>
> [AM: Remove word 'Atmel' from filenames and all elements of code]
> Suggested-by: Aleksandar Markovic
> Signed-off-by: Michael Rolnik
> Signed-off-by: Richard Henderson
> Signed-off-by: Aleksandar
As we will modify milkymist_memcard_create(), move it first
to the source file where it is used.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lm32/milkymist-hw.h | 11 ---
hw/lm32/milkymist.c| 11 +++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/lm32/mi
We don't need to wait until realize() to create the SDBus,
create it in init() directly.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/milkymist-memcard.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
index afdb8
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :)
This series move the SD card creation to the machine/board code.
Regards,
Phil.
Philippe Mathieu-Daudé (4):
hw/lm32/milkymist: Un-inline milkymist_memcard_create()
hw/lm32/milkymist: Comment to re
The 'card is readonly' and 'card inserted' IRQs are not wired.
Add a comment in case someone know where to wire them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lm32/milkymist.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
index 469e3c4322..1179
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :) Let the machine/board object
create and plug the SD cards when required.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lm32/milkymist.c | 13 +
hw/sd/milkymist-memcard.c | 55 +
On Sun, Jul 5, 2020 at 11:16 AM Max Filippov wrote:
> On Sun, Jul 5, 2020 at 10:09 AM Peter Maydell
> wrote:
> > On Thu, 2 Jul 2020 at 19:53, Richard Henderson
> > wrote:
> > > This isn't right. Not so much the gen_io_start portion, but the entire
> > > existence of helper_check_interrupt.
> >
sd_data_ready() belongs to the legacy API. As its last user has
been converted to the SDBus API, make it static.
Reviewed-by: Alistair Francis
Message-Id: <20180216022933.10945-7-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sd.h | 1 -
hw/sd/sd.c | 2 +-
2 fi
omap_mmc.c is the last device left using the legacy sdcard API.
Move the prototype declarations into a separate header, to
make it clear this is a legacy API.
Reviewed-by: Alistair Francis
Message-Id: <20180216022933.10945-8-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :) Let the machine/board object
create and plug the SD cards when required.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/integratorcp.c | 13 +
hw/arm/realview.c | 12
hw/
Convert disabled DPRINTF() to trace events and remove ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pl181.c | 26 +-
hw/sd/trace-events | 10 ++
2 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index f
To make the code easier to manage/review/use, rename the
cardstatus[0] variable as 'card_readonly' and name the GPIO
"card-read-only".
Similarly with cardstatus[1], renamed as 'card_inserted' and
name its GPIO "card-inserted".
Adapt the users accordingly by using the qdev_init_gpio_out_named()
fun
The 'card is readonly' and 'card inserted' IRQs are not wired.
Add a comment in case someone know where to wire them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/versatilepb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index e596b8170f.
From: Alistair Francis
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr,
"\(.*\)\\n"\(.*\))
Add TODO to use Fifo32 API from "qemu/fifo32.h".
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pl181.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index 3fc2cdd71a..86219c851d 100644
--- a/hw/sd/pl181.c
+++ b/hw/sd/pl181.c
@@ -57,7 +57,7 @@
Hi,
Since v3:
- rebased (was from Feb 2018)
- use named GPIOs
- addressed Peter review comment (adding TYPE_PL181_BUS object)
- convert DPRINF to trace events
Since v2:
- pl181: remove legacy sd_set_cb() (Peter)
Since v1:
- rebased on /master (Peter sdcard reset() patches)
- fix milkymist-mmc fr
Convert the controller to the SDBus API:
- add the a TYPE_PL181_BUS object of type TYPE_SD_BUS,
- adapt the SDBusClass set_inserted/set_readonly handlers
- create the bus in the PL181 controller
- switch legacy sd_*() API to the sdbus_*() API.
Signed-off-by: Philippe Mathieu-Daudé
---
Since v3:
A
pl181_send_command() do a bus transaction (send or receive),
rename it as pl181_do_command().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pl181.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index 649386ec3d..3fc2cdd71a 100644
--- a/hw
On Sat, Jul 4, 2020, 16:50 Philippe Mathieu-Daudé wrote:
> Various machine/board/soc models create OHCI device instances
> with the generic QDEV API, and don't need to access USB internals.
>
> Simplify header inclusions by moving the QOM type names into a
> simple header, with no need to include
Public bug reported:
which gives an error when run on a system that uses dash for /bin/sh.
The problem is at line 6464 which has
if test "$have_keyring" == "yes"
the double equal sign is non-posix bash syntax that isn't accepted by posix
shells like dash. This was added 2020-05-25 according
On Sun, 5 Jul 2020 at 19:31, Thomas Huth wrote:
>
> Am Sun, 5 Jul 2020 07:29:06 -0700 (PDT)
> schrieb no-re...@patchew.org:
>
> > Patchew URL:
> > https://patchew.org/QEMU/20200705140315.260514-1-h...@tuxfamily.org/
> [...]
> > === OUTPUT BEGIN ===
> > 1/30 Checking commit b5e3116a3591 (target/avr
Am Sun, 5 Jul 2020 07:29:06 -0700 (PDT)
schrieb no-re...@patchew.org:
> Patchew URL:
> https://patchew.org/QEMU/20200705140315.260514-1-h...@tuxfamily.org/
[...]
> === OUTPUT BEGIN ===
> 1/30 Checking commit b5e3116a3591 (target/avr: Add basic parameters
> of the new platform) WARNING: added, move
On Fri, 3 Jul 2020 at 17:54, Peter Maydell wrote:
>
> From: Eric Auger
>
> This patch implements the PROBE request. At the moment,
> only THE RESV_MEM property is handled. The first goal is
> to report iommu wide reserved regions such as the MSI regions
> set by the machine code. On x86 this will
On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote:
>
> From: LIU Zhiwei
>
> Vector AMOs operate as if aq and rl bits were zero on each element
> with regard to ordering relative to other instructions in the same hart.
> Vector AMOs provide no ordering guarantee between element operations
> in t
On Sun, Jul 5, 2020 at 10:09 AM Peter Maydell wrote:
> On Thu, 2 Jul 2020 at 19:53, Richard Henderson
> wrote:
> > This isn't right. Not so much the gen_io_start portion, but the entire
> > existence of helper_check_interrupt.
>
> I agree that it looks bogus (xtensa has a similar helper as well,
On 07.02.20 07:43, Jan Kiszka wrote:
From: Jan Kiszka
This is helpful when debugging stuck guest timers.
As we need apic_get_current_count for that, and it is really not
emulation specific, move it to apic_common.c and export it. Fix its
style at this chance as well.
Signed-off-by: Jan Kiszka
On Sun, 5 Jul 2020, David Gibson wrote:
On Tue, Jun 30, 2020 at 11:45:42PM +0200, BALATON Zoltan wrote:
On Tue, 30 Jun 2020, Mark Cave-Ayland wrote:
On 29/06/2020 19:55, BALATON Zoltan wrote:
The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
the rom region and fall back to l
Several callers of load_elf() pass pointers for lowaddr and highaddr
parameters which are then not used for anything. This may stem from a
misunderstanding that load_elf need a value here but in fact it can
take NULL to ignore these values. Remove such unused variables and
pass NULL instead from ca
Since added in commit 2bea128c3d, each SDHCI is wired with a SD
card, using empty card when no block drive provided. This is not
the desired behavior. The SDHCI exposes a SD bus to plug cards
on, if no card available, it is fine to have an unplugged bus.
Avoid creating unnecessary SD card device w
On 7/5/20 12:26 AM, Philippe Mathieu-Daudé wrote:
> On 7/5/20 12:18 AM, Philippe Mathieu-Daudé wrote:
>> On 7/5/20 12:10 AM, Philippe Mathieu-Daudé wrote:
>>> On 7/4/20 1:42 AM, Philippe Mathieu-Daudé wrote:
On 7/3/20 5:16 PM, Philippe Mathieu-Daudé wrote:
> On 7/3/20 3:23 PM, Peter Maydel
On Mon, 29 Jun 2020 at 09:17, Wentong Wu wrote:
>
> wrctl instruction on nios2 target will cause checking cpu
> interrupt but tcg_handle_interrupt() will call cpu_abort()
> if the CPU gets an interrupt while it's not in 'can do IO'
> state, so add gen_io_start around wrctl instruction. Also
> at t
On Thu, 2 Jul 2020 at 19:53, Richard Henderson
wrote:
> This isn't right. Not so much the gen_io_start portion, but the entire
> existence of helper_check_interrupt.
I agree that it looks bogus (xtensa has a similar helper as well, incidentally),
but fixing all that stuff up is more effort than
On Sunday, July 5, 2020, Aleksandar Markovic <
aleksandar.qemu.de...@gmail.com> wrote:
>
>
> On Saturday, July 4, 2020, Aleksandar Markovic <
> aleksandar.qemu.de...@gmail.com> wrote:
>
>>
>>
>> On Friday, July 3, 2020, Stefan Brankovic
>> wrote:
>>
>>> Add disassembler for Loongson 2F instructio
On Saturday, July 4, 2020, Aleksandar Markovic <
aleksandar.qemu.de...@gmail.com> wrote:
>
>
> On Friday, July 3, 2020, Stefan Brankovic
> wrote:
>
>> Add disassembler for Loongson 2F instruction set.
>>
>> Testing is done by comparing qemu disassembly output, obtained by
>> using -d in_asm comma
Patchew URL:
https://patchew.org/QEMU/20200705140315.260514-1-h...@tuxfamily.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH rc6 00/30] target/avr merger
Type: series
Message-id: 20200705140315.260514-1-h...@tuxfamily.org
在 2020/7/5 4:04, Philippe Mathieu-Daudé 写道:
Hi Stefan,
On 7/3/20 12:44 PM, Stefan Brankovic wrote:
Add disassembler for Loongson 2F instruction set.
Testing is done by comparing qemu disassembly output, obtained by
using -d in_asm command line option, with appropriate objdump output.
This
From: Michael Rolnik
Add a single code line that will automatically provide 'machine none'
test.
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Reviewed-by: Thomas Huth
Sig
From: Michael Rolnik
These were designed to facilitate testing but should provide enough
function to be useful in other contexts. Only a subset of the functions
of each peripheral is implemented, mainly due to the lack of a standard
way to handle electrical connections (like GPIO pins).
[AM: Re
From: Michael Rolnik
This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT
Signed-off-by: Michael Rolnik
Signed-off-by: Richa
From: Michael Rolnik
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by:
From: Michael Rolnik
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philip
The new section explains basic ways of using AVR target in QEMU.
Signed-off-by: Michael Rolnik
[thuth: Converted doc from texi to Sphinx syntax]
Signed-off-by: Thomas Huth
---
docs/system/target-avr.rst | 37 +
docs/system/targets.rst| 1 +
2 files chang
From: Michael Rolnik
Print out 'T' through serial port.
The Arduino Duemilanove is based on a AVR5 CPU, while the
Arduino MEGA2560 on a AVR6 CPU.
Signed-off-by: Michael Rolnik
Signed-off-by: Philippe Mathieu-Daudé
[rth: Squash Arduino adjustments from f4bug]
Tested-by: Richard Henderson
Sign
From: Philippe Mathieu-Daudé
Add avr_load_firmware() function to load firmware in ELF or
raw binary format.
[AM: Corrected the type of the variable containing e_flags]
[AM: Moved definition of e_flags conversion function to boot.c]
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathi
From: Michael Rolnik
Start implementation of instructions by adding register definitions.
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
From: Michael Rolnik
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
As the path name demonstrates, the FreeRTOS tests target a
b
From: Michael Rolnik
Add helpers for instructions that need to interact with QEMU. Also,
add stubs for unimplemented instructions. Instructions SPM and WDR
are left unimplemented because they require emulation of complex
peripherals. The implementation of instruction SLEEP is very limited
due to
From: Michael Rolnik
Add AVR related definitions into QEMU.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksandar Markovic
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé
Add some AVR microcontrollers from the ATmega family:
- middle range: ATmega168 and ATmega328
- high range: ATmega1280 and ATmega2560
For product comparison:
https://www.microchip.com/wwwproducts/ProductCompare/ATmega168P/ATmega328P
https://www.microchip.com
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