From: Filip Bozuta
Implementation of syscall 'utimensat()' in 'syscall.c' uses functions
target_to_host/host_to_target_timespec() to convert values of
'struct timespec' between host and target. However, the implementation
doesn't check whether the conversion succeeds and thus can cause an
inappro
From: Filip Bozuta
This patch implements functionality of following ioctls:
BTRFS_IOC_INO_LOOKUP - Reading tree root id and path
Read tree root id and path for a given file or directory.
The name and tree root id are returned in an ioctl's third
argument that represents a pointer to
From: Andrew
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1857668
Added AER capability for virtio-pci devices.
Also added property for devices, by default AER is enabled.
Signed-off-by: Andrew Melnychenko
---
hw/virtio/virtio-pci.c | 16
hw/virtio/virtio-pci.h | 4 +++
From: Filip Bozuta
This patch implements functionality for following ioctl:
BTRFS_IOC_DEFAULT_SUBVOL - Setting a default subvolume
Set a default subvolume for a btrfs filesystem. The third
ioctl's argument is a '__u64' (unsigned long long) which
represents the id of a subvolume that
From: Andrew
Removed hardcoded offset for ats. Added cap offset counter
for future capabilities like AER.
Signed-off-by: Andrew Melnychenko
---
hw/virtio/virtio-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index cc
From: Filip Bozuta
This patch implements functionality for following time64 syscalls:
*clock_getres_time64
This a year 2038 safe variant of syscall:
int clock_getres(clockid_t clockid, struct timespec *res)
--finding the resoultion of a specified clock--
man page: https://m
From: Filip Bozuta
This patch implements functionality for following ioctls:
BTRFS_IOC_SCAN_DEV - Scanning device for a btrfs filesystem
Scan a device for a btrfs filesystem. The device that is to
be scanned is passed in the ioctl's third argument which
represents a pointer to a 'st
From: Filip Bozuta
This patch implements functionality for following ioctls:
BTRFS_IOC_SCRUB - Starting a btrfs filesystem scrub
Start a btrfs filesystem scrub. The third ioctls argument
is a pointer to a following type:
struct btrfs_ioctl_scrub_args {
__u64 devid;
From: Filip Bozuta
Functions 'target_to_host_itimerspec()' and 'host_to_target_itimerspec()'
are used to convert values of type 'struct itimerspec' between target and
host. This type has 'struct timespec' as its fields. That is the reason
why this patch introduces a little modification to the con
From: Filip Bozuta
This patch implements functionality of following ioctls:
BTRFS_IOC_SUBVOL_CREATE - Creating a btrfs subvolume
Create a btrfs subvolume. The subvolume is created using the ioctl's
third argument which represents a pointer to a following structure
type:
struct
From: Filip Bozuta
This patch implements functionality for following ioctls:
BTRFS_IOC_GET_FEATURES - Getting feature flags
Read feature flags for a btrfs filesystem. The feature flags
are returned inside the ioctl's third argument which represents
a pointer to a following structure
From: Filip Bozuta
This patch implements functionality for following ioctls:
BTRFS_IOC_SNAP_CREATE - Creating a subvolume snapshot
Create a snapshot of a btrfs subvolume. The snapshot is created using the
ioctl's third argument that is a pointer to a 'struct btrfs_ioctl_vol_args'
(w
From: Richard Henderson
Executable guest pages are never directly executed by
the host, but do need to be readable for translation.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-Id: <20200519185645.3915-3-richard.hender...@linaro.org>
The following changes since commit d0ed6a69d399ae193959225cdeaa9382746c91cc:
Update version for v5.1.0 release (2020-08-11 17:07:03 +0100)
are available in the Git repository at:
git://github.com/vivier/qemu.git tags/linux-user-for-5.2-pull-request
for you to fetch changes up to 04275cad60c
From: Filip Bozuta
Function "print_fdset()" in "strace.c" is used to print the file descriptor
values in "print__newselect()" which prints arguments of syscall _newselect().
Until changes from this patch, this function was printing "," even after the
last value of the fd_set argument. This was ch
From: Richard Henderson
The kernel will return -EINVAL for bits set in the prot argument
that are unknown or invalid. Previously we were simply cropping
out the bits that we care about.
Introduce validate_prot_to_pageflags to perform this check in a
single place between the two syscalls. Diffe
On Wed, Aug 12, 2020 at 06:31:11PM +0200, Andrew Jones wrote:
> On Wed, Aug 12, 2020 at 08:10:47AM -0700, Richard Henderson wrote:
> > On 8/12/20 4:00 AM, Andrew Jones wrote:
> > > On Tue, Aug 11, 2020 at 11:53:38PM -0700, Richard Henderson wrote:
> > >> The crypto overhead of emulating pauth can b
On 2020/8/10 下午3:46, Yan Zhao wrote:
driver is it handled by?
It looks that the devlink is for network device specific, and in
devlink.h, it says
include/uapi/linux/devlink.h - Network physical device Netlink
interface,
Actually not, I think there used to have some discussion last year and
Hi Alistair,
Thanks for the feedback and tips. Not sure whether I get it right. I gave a
try with -drive and -device options as below.
$ qemu-system-riscv64 -M sifive_u -drive if=none,format=raw,file=otp.img
-device riscv.sifive.u.otp
qemu-system-riscv64: -device riscv.sifive.u.otp: Parameter 'dr
With gcrypt, most of the dispatch happens in the library,
so there aren't many classes to create. However, we can
still create separate dispatch for CTR mode, and for
CONFIG_QEMU_PRIVATE_XTS, which avoids needing to check
for these modes at runtime.
Signed-off-by: Richard Henderson
---
crypto/c
Use separate classes for each cipher entry point: des_rfb, des3,
aes128, aes192, aes256, cast128, serpent, and twofish.
Generate wrappers for XTS only for CONFIG_QEMU_PRIVATE_XTS.
This eliminates unreachable wrappers for DES_RFB, DES3 and
CAST128, which have blocksizes that do not allow XTS mode.
We had a second set of function pointers in QCryptoCipherBuiltin,
which are redundant with QCryptoCipherDriver. Split the AES and
DES implementations to avoid one level of indirection.
Signed-off-by: Richard Henderson
---
crypto/cipher-builtin.inc.c | 553 +++-
1
This allows the in memory structures to be read-only.
Signed-off-by: Richard Henderson
---
crypto/cipherpriv.h | 2 +-
include/crypto/cipher.h | 2 +-
crypto/cipher-afalg.c | 2 +-
crypto/cipher-builtin.inc.c | 2 +-
crypto/cipher-gcrypt.inc.c | 2 +-
crypto/cipher-nettle
The fourth argument to xts_encrypt should be the decrypt
callback; we were accidentally passing encrypt twice.
Signed-off-by: Richard Henderson
---
crypto/cipher-nettle.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/crypto/cipher-nettle.inc.c b/crypto/cipher-nettle.inc
Split into encrypt/decrypt functions, dropping the "enc" argument.
Now that the function is private to this file, we know that "len"
is a multiple of AES_BLOCK_SIZE. So drop the odd block size code.
Name the functions do_aes_*crypt_cbc to match the *_ecb functions.
Reorder and re-type the argumen
Both qemu/osdep.h and cipherpriv.h have already been
included by the parent cipher.c.
Signed-off-by: Richard Henderson
---
crypto/cipher-builtin.inc.c | 2 --
crypto/cipher-gcrypt.inc.c | 2 --
crypto/cipher-nettle.inc.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/crypto/cipher-built
By making the function private, we will be able to make further
simplifications. Re-indent the migrated code and fix the missing
braces for CODING_STYLE.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h| 4 ---
crypto/aes.c| 51 -
We verified that the data block is properly sized modulo
AES_BLOCK_SIZE within qcrypto_builtin_cipher_{en,de}crypt.
Therefore we will never have to handle odd sized blocks.
Signed-off-by: Richard Henderson
---
crypto/cipher-builtin.inc.c | 40 +++--
1 file changed
There's no real reason we need two separate helper functions here.
Standardize on the function signature required for xts_encrypt.
Rename to do_aes_{en,de}crypt_ecb, since the helper does not
itself do anything with respect to xts.
Signed-off-by: Richard Henderson
---
crypto/cipher-builtin.inc.c
QEMU standard procedure for included c files is to use *.inc.c.
E.g. there are a different set of checks that are applied.
Signed-off-by: Richard Henderson
---
crypto/{cipher-builtin.c => cipher-builtin.inc.c} | 0
crypto/{cipher-gcrypt.c => cipher-gcrypt.inc.c} | 0
crypto/{cipher-nettle.c =>
The class vtable should be set by the class initializer.
This will also allow additional subclassing, reducing the
amount of indirection in the hierarchy.
Signed-off-by: Richard Henderson
---
crypto/cipherpriv.h | 2 --
crypto/cipher-afalg.c | 5 -
crypto/cipher-builtin.inc.c |
Signed-off-by: Richard Henderson
---
crypto/cipher.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/crypto/cipher.c b/crypto/cipher.c
index 6e25f68f5c..2fe12a4fdc 100644
--- a/crypto/cipher.c
+++ b/crypto/cipher.c
@@ -25,7 +25,7 @@
#include "cipherpriv.h"
-static s
This will allow the pointer to be used in crypto/cipher.h,
and not just in code using cipherpriv.h.
Signed-off-by: Richard Henderson
---
crypto/cipherpriv.h | 2 --
include/qemu/typedefs.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/crypto/cipherpriv.h b/crypto/ciphe
Mostly this is intended to cleanup the class hierarchy
used for the ciphers. We currently have multiple levels
of dispatch, and multiple separate allocations. The final
patches rearrange this to one level of indirect call, and
all memory allocated contiguously.
But on the way there are a number
Merge the allocation of "opaque" into the allocation of "cipher".
This is step one in reducing the indirection in these classes.
Signed-off-by: Richard Henderson
---
crypto/afalgpriv.h | 3 ++
crypto/cipherpriv.h | 2 +-
include/crypto/cipher.h | 1 -
crypto/cipher-afalg.
The check in the encode/decode path using full division has a
noticeable amount of overhead. By asserting the blocksize is
a power of 2, we can reduce this check to a mask.
Signed-off-by: Richard Henderson
---
crypto/cipher-builtin.c | 4 ++--
crypto/cipher-gcrypt.c | 5 +++--
crypto/cipher-ne
This allows header files to declare pointers without pulling
in the entire crypto subsystem.
Signed-off-by: Richard Henderson
---
include/crypto/cipher.h | 2 --
include/qemu/typedefs.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/crypto/cipher.h b/include/crypto/
On Wed, Aug 12, 2020 at 11:21 PM Alistair Francis wrote:
>
> On Tue, Jul 28, 2020 at 1:29 AM Zong Li wrote:
> >
> > The minimum granularity of PMP is 4 bytes, it is small than 4KB page
> > size, therefore, the pmp checking would be ignored if its range doesn't
> > start from the alignment of one
On 8/12/20 9:03 PM, David Gibson wrote:
On Wed, Aug 12, 2020 at 02:33:33PM -0700, Richard Henderson wrote:
On 8/11/20 8:32 AM, Gustavo Romero wrote:
Currently if option '-icount auto' is passed to the QEMU TCG to enable
counting instructions the VM crashes with the following error report when
L
On 2020/8/13 3:13, Alistair Francis wrote:
This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6.1 draft implementation.
THis includes support for the new 2-stage lookup instructions and the new
CSRs.
It also includes the new 0.6.1 support for the virtual instruction
f
On 2020/8/13 6:30, Alistair Francis wrote:
From: Richard Henderson
If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan. The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.
Signed-off-by: Richard Hende
Hi Stefan,
On 2020/8/12 21:51, Stefan Hajnoczi wrote:
> On Mon, Aug 10, 2020 at 10:52:44PM +0800, Zhenyu Ye wrote:
>> Before doing qmp actions, we need to lock the qemu_global_mutex,
>> so the qmp actions should not take too long time.
>>
>> Unfortunately, some qmp actions need to acquire aio cont
Alexander Bulekov 于2020年8月13日周四 上午12:56写道：
>
> On 200813 0024, Li Qiang wrote:
> > Alexander Bulekov <1891...@bugs.launchpad.net> 于2020年8月13日周四 上午12:21写道：
> > >
> > > Public bug reported:
> > >
> > > Hello,
> > > Reproducer:
> > >
> > > cat << EOF | ./i386-softmmu/qemu-system-i386 -device nec-usb-
Cornelia Huck writes:
> On Thu, 30 Jul 2020 11:45:41 +0200
> Cornelia Huck wrote:
>
>> On Tue, 28 Jul 2020 21:51:33 -0300
>> Thiago Jung Bauermann wrote:
>>
>> > Hi,
>> >
>> > Cornelia Huck writes:
>> >
>> > > On Wed, 22 Jul 2020 23:56:57 -0300
>> > > Thiago Jung Bauermann wrote:
>> >
The QTests perform five tests on the Xilinx ZynqMP CAN controller:
Tests the CAN controller in loopback, sleep and snoop mode.
Tests filtering of incoming CAN messages.
Reviewed-by: Francisco Iglesias
Signed-off-by: Vikram Garhwal
---
tests/qtest/Makefile.include | 2 +
tests/qtest/xl
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Example for using single CAN:
-object can-bus,id=canbus0 \
-machine xlnx-zcu102.canbus0=canbus0 \
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0886eb3..14d9b73 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1536,6 +1536,14 @@ F: hw/net/o
Connect CAN0 and CAN1 on the ZynqMP.
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
hw/arm/xlnx-zcu102.c | 20
hw/arm/xlnx-zynqmp.c | 34 ++
include/hw/arm/xlnx-zynqmp.h | 8
Changelog:
v8 -> v9:
Use g_autofree to do automatic cleanup the object_get_canonical_path() used.
v7 -> v8:
Change CAN controller to keep one canbus per controller.
Add canbus connections at machine level.
Remove ctrl_idx from CAN controller.
v6 -> v7:
Remove '-m 4G' option f
On Wed, Aug 12, 2020 at 02:33:33PM -0700, Richard Henderson wrote:
> On 8/11/20 8:32 AM, Gustavo Romero wrote:
> > Currently if option '-icount auto' is passed to the QEMU TCG to enable
> > counting instructions the VM crashes with the following error report when
> > Linux runs on it:
> >
> > qemu
On Wed, Jul 29, 2020 at 4:32 AM Anup Patel wrote:
>
> When RISCV_FEATURE_TINST feature is enabled, we should write
> transformed instruction encoding of the trapped instruction
> in MTINST/HTINST CSR at time of taking trap.
>
> We update riscv_cpu_do_interrupt() as-per above.
>
> Signed-off-by: An
tags/20200812-xtensa
for you to fetch changes up to f64fa1494d5f92d4e4f0cc6a0ef3c7e3cc12763d:
target/xtensa: import DSP3400 core (2020-08-12 15:56:51 -0700)
target/xtensa updates for 5.2:
- add NMI support;
- add DFPU option
After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
55765822804f5a58594e "riscv: plic: Add a couple of mising
sifive_plic_update calls"
Signed-off-by: Alistair Francis
Cc: Jessica Clarke
Reviewed-by: Philippe Mathieu-D
From: Zong Li
The minimum granularity of PMP is 4 bytes, it is small than 4KB page
size, therefore, the pmp checking would be ignored if its range doesn't
start from the alignment of one page. This patch detects the pmp entries
and sets the small page size to TLB if there is a PMP entry which cov
From: Bin Meng
It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <1595227748-24720-
From: Bin Meng
Now we need to ship the OpenSBI fw_dynamic.elf image for the
RISC-V Spike machine, it requires us to create symbolic links
for pc-bios/*.elf files.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <1596439832-29238-2-git-send-email-bmeng...@gmail.com>
Signed-off
On Wed, Jul 29, 2020 at 4:29 AM Anup Patel wrote:
>
> The RISC-V spec allows implementations to provide trapped instruction
> opcode in MTVAL/STVAL CSR for illegal/virtual instruction traps. This
> is totally optional and most RISC-V implementations always set zero
> in the MTVAL/STVAL CSR for ill
From: Bin Meng
Upgrade OpenSBI from v0.7 to v0.8.
The v0.8 release includes the following commits:
1bb00ab lib: No need to provide default PMP region using platform callbacks
a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback
6585fab lib: utils: Add SiFive test device
From: Hou Weiying
First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.
If the
From: Bin Meng
The RISC-V generic platform is a flattened device tree (FDT) based
platform where all platform specific functionality is provided based
on FDT passed by previous booting stage. The support was added in
the upstream OpenSBI v0.8 release recently.
Update our Makefile to build the ge
This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
priorities" does and ensures that the highest priority interrupt will be
serviced first.
Signed-off-by: Alistair Francis
Cc: Jessica Clarke
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
---
hw/intc/ibex_plic.c | 15 ++
From: Richard Henderson
If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Message-Id: <20200724002807.441147-5-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
target/riscv/i
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Message-Id: <20200626205917.4545-5-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson
Message-Id: <20200724002807.441147-8-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans
Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.
Signed-off-by: Alistair Francis
Message-Id:
<394c3f070615ff2b4fab61a1cf9cb
From: Richard Henderson
Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Message-Id: <20200724002807.441147-4-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
From: LIU Zhiwei
Use tcg_gen_extu_tl_i64 to avoid the ifdef.
Signed-off-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Message-Id: <20200626205917.4545-7-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson
Message-Id: <20200724002807.441147-7-richard.hender...@linaro.org>
Signed-off-by: A
From: Zong Li
The real physical address should add the 12 bits page offset. It also
causes the PMP wrong checking due to the minimum granularity of PMP is
4 byte, but we always get the physical address which is 4KB alignment,
that means, we always use the start address of the page to check PMP fo
From: Richard Henderson
Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Message-Id: <20200724002807.441147-2-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
target/ri
From: Richard Henderson
Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno. Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Message-Id: <20200724002807.44
From: Bin Meng
This updates the GitLab CI opensbi job to build opensbi bios images
for the generic platform.
Signed-off-by: Bin Meng
Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Message-Id: <1596439832-29238-7-git-send-email-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
.
The following changes since commit d0ed6a69d399ae193959225cdeaa9382746c91cc:
Update version for v5.1.0 release (2020-08-11 17:07:03 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200812
for you to fetch changes up to
From: Richard Henderson
If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan. The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Message-Id: <2020
---
tcg/tcg-op-gvec.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
qemu was generating buggy tcg for arm64's vectorized absolute value
insn when the machine didn't support avx insns.
Subtracting a mask of -1 for each negative element doesn't
add 1 to each negative element. For exam
On 8/11/20 8:32 AM, Gustavo Romero wrote:
> Currently if option '-icount auto' is passed to the QEMU TCG to enable
> counting instructions the VM crashes with the following error report when
> Linux runs on it:
>
> qemu-system-ppc64: Bad icount read
>
> This happens because read/write access to t
Quoting Philippe Mathieu-Daudé (2020-08-06 05:44:44)
> On 8/6/20 11:03 AM, Tomáš Golembiovský wrote:
> > The command guest-get-fsinfo can be used to list information about disks and
> > partitions but it is limited only to mounted disks with filesystem. This new
> > command allows listing informati
Quoting Tomáš Golembiovský (2020-08-06 04:03:06)
> The command guest-get-fsinfo can be used to list information about disks and
> partitions but it is limited only to mounted disks with filesystem. This new
> command allows listing information about attached root disks of the VM. This
> is
> usefu
On Wed, Aug 12, 2020 at 04:33:24PM +0200, Eugenio Perez Martin wrote:
> On Tue, Aug 11, 2020 at 9:28 PM Peter Xu wrote:
> >
> > Hi, Eugenio,
> >
> > On Tue, Aug 11, 2020 at 08:10:44PM +0200, Eugenio Perez Martin wrote:
> > > Using this patch as a reference, I'm having problems to understand:
> > >
On Wed, Aug 12, 2020 at 11:03 AM Andrey Konovalov
wrote:
> On Wed, Aug 12, 2020 at 7:52 PM Richard Henderson
> wrote:
> >
> > On 8/12/20 10:38 AM, Andrey Konovalov wrote:
> > > On Wed, Aug 12, 2020 at 7:19 PM Richard Henderson
> > > wrote:
> > >>
> > >> As reported by Andrey, I was missing the
When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 46
target/riscv/op_helper.c | 18
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 40
2 files changed, 43 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 573d85da41..d88e2ea30d 100644
--- a/target/riscv/cpu
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f9ac21d687..390ef781e4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -836,12 +836,21 @@ static int write_satp(CPURISCVSta
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 16 ++--
target/riscv/op_helper.c | 8 ++--
target/riscv/translate.c | 10 --
4 files changed, 9 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/targ
On Wed, Aug 05, 2020 at 03:02:20PM +0200, Philippe Mathieu-Daudé wrote:
> Commit c7f419f584 moved softmmu-only files out of the root
> directory, but forgot to move the trace events, which should
> no longer be generated to "trace-root.h". Fix that by adding
> softmmu/trace-events.
>
> Signed-off-
On Thu, Aug 06, 2020 at 04:13:30PM +0200, Markus Armbruster wrote:
> Philippe's "[PATCH] softmmu: Add missing trace-events file" made me
> look for more. Enjoy!
>
> Based-on: <20200805130221.24487-1-phi...@redhat.com>
>
> Markus Armbruster (4):
> scripts/cleanup-trace-events: Fix for vcpu prop
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6a96a01b1c..0f035d33b1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -922,7 +922,6 @@ static int read_htinst(CPURISCVState *env, in
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 60 ---
1 file changed, 25 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 68abccc993..10c9f8b63b 100644
--- a/target/riscv/cpu_helper.c
+++
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 6 +++
target/riscv/helper.h | 1 +
target/riscv/csr.c | 64 -
target/riscv/insn_trans/trans_rvh.inc.c | 2 +-
target/riscv/op_helper.c|
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/helper.h | 3 +
target/riscv/insn32-64.decode | 5 +
target/riscv/insn32.decode | 11 +
target/riscv/insn_trans/trans_rvh.inc.c | 340 +++
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fb6a3e9092..573d85da41 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -437,
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 390ef781e4..5e50683c58 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -840,6 +840,8 @@ static int read_hstatus(CPURISCVState *
This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6.1 draft implementation.
THis includes support for the new 2-stage lookup instructions and the new
CSRs.
It also includes the new 0.6.1 support for the virtual instruction
fault.
This was tested by running 32-bit and 64-
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 5 +++--
target/riscv/cpu_helper.c | 24
target/riscv/csr.c| 6 +++---
3 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7abae42
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b5f4264525..9ab3ca4675 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -909,
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 18 ++
3 files changed, 21 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a804a5d0ba..383808bf88 100644
--- a/target/risc
On Wed, 12 Aug 2020 19:29:26 +0200
Laurent Vivier wrote:
> Le 12/08/2020 à 19:08, Greg Kurz a écrit :
> > Since commit 61f20b9dc5b7 ("spapr_nvram: Pre-initialize the NVRAM to
> > support the -prom-env parameter"), pseries machines can pre-initialize
> > the "system" partition in the NVRAM with th
To have a better idea of how big is the region where the offset
belongs, display the value with the width of the region size
(i.e. a region of 0x1000 bytes uses 0x000 format).
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
Since v1: Use DIV_ROUND_UP (rth)
---
include/h
To quickly notice the access size, display the value with the
width of the access (i.e. 16-bit access is displayed 0x,
while 8-bit access 0x00).
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/unimp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
To better align the read/write accesses, display the value after
the offset (read accesses only display the offset).
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/unimp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/misc/unimp
This series aims to ease looking at the '-d unimp' output reported
by the UnimplementedDevice.
- read/write accesses are now aligned
- the value format width uses the access size
- the offset (address) uses the size of the memory region it belongs
Series fully reviewed.
Since v1:
- Use DIV_ROUND
On 8/12/20 7:34 PM, Richard Henderson wrote:
> On 8/7/20 7:37 AM, Philippe Mathieu-Daudé wrote:
>> +s->offset_fmt_width = ROUND_UP(64 - clz64(s->size - 1), 4) >> 2;
>
> Better with DIV_ROUND_UP, I think. Otherwise,
Thanks for the tip! (and for reviewing the other series) :)
>
> Reviewed-by
1 - 100 of 291 matches
Mail list logo
