Re: [PATCH 6/7] add ninja to dockerfiles, CI configurations and test VMs

Paolo Bonzini writes: > Signed-off-by: Paolo Bonzini Acked-by: Alex Bennée > --- > .cirrus.yml| 6 +++--- > .travis.yml| 13 + > tests/docker/dockerfiles/centos7.docker| 1 + > tests/docker/dockerfiles/centos

Re: [PATCH] meson.build: don't condition iconv detection on library detection

On 10/15/20 6:33 AM, 罗勇刚(Yonggang Luo) wrote: On Thu, Oct 15, 2020 at 6:19 AM Bruce Rogers > wrote: > > It isn't necessarily the case that use of iconv requires an additional > library. For that reason we shouldn't conditionalize iconv detection on > libiconv.found

[PATCH v2 2/6] hw/sd/sdcard: Introduce the INVALID_ADDRESS definition

'0' is used as a value to indicate an invalid (or unset) address. Use a definition instead of a magic value. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 2606b969e34..30ae435d6

[PATCH v2 5/6] hw/sd/sdcard: Do not attempt to erase out of range addresses

While the Spec v3 is not very clear, v6 states: If the host provides an out of range address as an argument to CMD32 or CMD33, the card shall indicate OUT_OF_RANGE error in R1 (ERX) for CMD38. If an address is out of range, do not attempt to erase it: return R1 with the error bit set. Bugl

[PATCH v2 1/6] hw/sd/sdcard: Add trace event for ERASE command (CMD38)

Trace addresses provided to the ERASE command. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 2 +- hw/sd/trace-events | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 0012884..2606b969e34 100644 --- a/hw/sd/sd.c +++ b/hw/sd

[PATCH v2 3/6] hw/sd/sdcard: Do not use legal address '0' for INVALID_ADDRESS

As it is legal to WRITE/ERASE the address/block 0, change the value of this definition to an illegal address: UINT32_MAX. Unfortunately this break the migration stream, so bump the VMState version number. This affects some ARM boards and the SDHCI_PCI device (which is only used for testing). Sign

[PATCH v2 4/6] hw/sd/sdcard: Reset both start/end addresses on error

>From the Spec "4.3.5 Erase": The host should adhere to the following command sequence: ERASE_WR_BLK_START, ERASE_WR_BLK_END and ERASE (CMD38). If an erase (CMD38) or address setting (CMD32, 33) command is received out of sequence, the card shall set the ERASE_SEQ_ERROR bit in the sta

[PATCH v2 0/6] hw/sd/sdcard: Do not attempt to erase out of range addresses

Yet another bug in the sdcard model found by libfuzzer: https://bugs.launchpad.net/bugs/1895310 Since RFC: Settled migration issue Philippe Mathieu-Daudé (6): hw/sd/sdcard: Add trace event for ERASE command (CMD38) hw/sd/sdcard: Introduce the INVALID_ADDRESS definition hw/sd/sdcard: Do not

[PATCH v2 6/6] hw/sd/sdcard: Assert if accessing an illegal group

We can not have more group than 'wpgrps_size'. Assert if we are accessing a group above this limit. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 4454d168e2f..c3febed2434 100644 --- a/hw/sd/sd.c +++ b/hw/s

Re: [PATCH 5/7] dockerfiles: enable Centos 8 PowerTools

On 14/10/20 22:49, Cleber Rosa wrote: > On Wed, Oct 14, 2020 at 09:54:14AM -0400, Paolo Bonzini wrote: >> ninja is included in the CentOS PowerTools repository. >> >> Signed-off-by: Paolo Bonzini >> --- >> tests/docker/dockerfiles/centos8.docker | 3 +++ >> 1 file changed, 3 insertions(+) >> >> d

Re: [PATCH 0/7] build: replace ninjatool with ninja

On 15/10/20 08:15, Howard Spoelstra wrote: > ERROR: meson setup failed > > When I set --ninja=ninja explicitly, this error does not occur: > Found ninja.EXE-1.10.1 at C:\msys64\mingw64\bin/ninja.EXE That is fixed by Meson 0.55.2, I'll add a submodule update. Thanks for the reminder! Paolo

Re: [RFC PATCH v5 2/2] hw/riscv: sifive_u: Add backend drive support

Hi Alistair, On Thu, Oct 15, 2020 at 2:51 AM Alistair Francis wrote: > > On Wed, Oct 14, 2020 at 8:02 AM Bin Meng wrote: > > > > Hi Alistair, > > > > On Wed, Oct 14, 2020 at 10:46 PM Alistair Francis > > wrote: > > > > > > On Wed, Sep 30, 2020 at 12:10 AM Green Wan wrote: > > > > > > > > On W

Re: [RFC PATCH 3/6] hw/sd/sdcard: Do not use legal address '0' for INVALID_ADDRESS

On 9/22/20 4:48 PM, Markus Armbruster wrote: Paolo Bonzini writes: I think we can just bite the bullet and bump the version number. Just like not all boards are created equal in terms of migration compatibility, neither are all devices. Great. I'll add that to the commit description. Unfo

Re: [PATCH 0/7] build: replace ninjatool with ninja

On Wed, Oct 14, 2020 at 3:57 PM Paolo Bonzini wrote: > This pull request is the last build system change for 5.2 from > me, and it is simple: similar to how we are invoking > ROM or tests/tcg "make" from the main Makefile, we now invoke ninja > to build QEMU. Unlike those cases, however, build.n

Re: [PATCH v3 4/4] Jobs based on custom runners: add job definitions for QEMU's machines

On 15/10/2020 01.24, Cleber Rosa wrote: > On Wed, Oct 14, 2020 at 05:14:01PM -0400, Cleber Rosa wrote: >> On Wed, Oct 14, 2020 at 06:46:55PM +0100, Daniel P. Berrangé wrote: >>> >>> This bug links to >>> >>> https://bugs.launchpad.net/ubuntu/+source/libssh/+bug/1847514 >>> >>> which is marked as

[PULL 3/3] linux-user/microblaze: Remove non-rt signal frames

The microblaze kernel does not support these, and uses only rt style signal frames. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- linux-user/microblaze/target_signal.h | 1 - linux-user/microblaze/signal.c| 97 +---

[PULL 1/3] tests/tcg/linux-test: Adjust getsockname for musl

Unlike glibc, musl does not use transparent unions to hide the different structures that overlap struct sockaddr. Add an explicit cast to work around this. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tests/tcg/multiarch/linux-test.c | 2 +- 1 file changed, 1 insert

[PULL 2/3] linux-user/microblaze: Implement rt signal frames

Allows microblaze to pass tests/tcg/multiarch/linux-test.c. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- linux-user/microblaze/signal.c | 91 ++ 1 file changed, 82 insertions(+), 9 deletions(-) diff --git a/li

[PULL 0/3] microblaze patch queue

The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4: Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request' into staging (2020-10-14 13:56:06 +0100) are available in the Git repository at: https://github.com/rth7680/qemu.git ta

Re: [PATCH] meson.build: don't condition iconv detection on library detection

On Thu, Oct 15, 2020 at 6:19 AM Bruce Rogers wrote: > > It isn't necessarily the case that use of iconv requires an additional > library. For that reason we shouldn't conditionalize iconv detection on > libiconv.found. > > Fixes: 5285e593c33 (configure: Fixes ncursesw detection under msys2/mingw b

[RFC PATCH v7 2/2] hw/misc/sifive_u_otp: Add backend drive support

Add '-drive' support to OTP device. Allow users to assign a raw file as OTP image. test commands for 16k otp.img filled with zero: $ dd if=/dev/zero of=./otp.img bs=1k count=16 $ ./qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \ -kernel ../opensbi/build/platform/sifive/fu540/firmw

[RFC PATCH v7 0/2] Add file-backed and write-once features to OTP

patch [1/2] - add write function and wrire-once feature patch [2/2] - add file backend support Test Steps: (should work even only 1/2 is applied) 1) Follow instructions to prepare fw_payload - https://github.com/riscv/opensbi/blob/master/docs/platform/sifive_fu540.md a) build 1-round opensbi

[RFC PATCH v7 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection

- Add write operation to update fuse data bit when PWE bit is on. - Add array, fuse_wo, to store the 'written' status for all bits of OTP to block the write operation. Signed-off-by: Green Wan Reviewed-by: Alistair Francis --- hw/misc/sifive_u_otp.c | 30 +++

Re: Why guest physical addresses are not the same as the corresponding host virtual addresses in QEMU/KVM? Thanks!

Hi Maxim, Thanks for your emphasis. It's much clearer. Best, Harry

Re: Why guest physical addresses are not the same as the corresponding host virtual addresses in QEMU/KVM? Thanks!

Hi Paolo and Sean, It is clear to me now. Thanks much for your reply and help. Best regards, Harry

Re: [PATCH] qemu-palcode: Changes to support booting NetBSD/alpha

On 10/14/20 4:16 PM, Jason Thorpe wrote: > >> On Oct 14, 2020, at 2:52 PM, Richard Henderson >> wrote: >> >> I'm certainly open to these changes. But it'll need to be split up -- one >> patch per bullet, basically. > > That's fine. What's the convention for patches that stack on top of one >

Re: [RFC PATCH v5 2/2] hw/riscv: sifive_u: Add backend drive support

Hi Alistair, That's correct. Once you configure 'CONFIG_SIFIVE_OTP=y', the uboot driver performs some read/write during booting. And I'll also include the test steps by using the 'misc' testing patch shared by Bin. Regards, - Green On Thu, Oct 15, 2020 at 2:51 AM Alistair Francis wrote: > > On

Re: [Qemu-devel][PATCH v6 1/6] x86/cpu: Rename XSAVE related feature words.

On Tue, Oct 13, 2020 at 05:08:54PM -0700, Sean Christopherson wrote: > On Tue, Oct 13, 2020 at 01:19:30PM +0800, Yang Weijiang wrote: > > With more components in XSS being developed on Intel platform, > > it's necessary to clean up existing XSAVE related feature words to > > make the name clearer.

Re: [RFC PATCH v6 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection

On Wed, Oct 14, 2020 at 3:17 PM Bin Meng wrote: > > Hi Green, > > On Wed, Oct 14, 2020 at 3:02 PM Green Wan wrote: > > > > On Wed, Oct 14, 2020 at 1:37 PM Bin Meng wrote: > > > > > > Hi Green, > > > > > > On Mon, Sep 28, 2020 at 6:12 PM Green Wan wrote: > > > > > > > > - Add write operation to

Re: [RFC PATCH 00/12] hw/arm/virt: Introduce cpu and cache topology support

On 10/14/2020 2:08 AM, Andrew Jones wrote: On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote: Cc valentin -Original Message- From: Qemu-devel [mailto:qemu-devel-bounces+prime.zeng=hisilicon@nongnu.org] On Behalf Of Ying Fang Sent: Thursday, September 17, 2020 11:20 AM

RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Thursday, October 15, 2020 3:12 AM > To: Richard Henderson > Cc: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org; Zhanghailiang ; > sag...@eecs.berkeley.edu; kbast...@mail.uni-paderborn.de; Zha

RE: [PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Thursday, October 15, 2020 4:22 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: pal...@dabbelt.com; alistair.fran...@wdc.com; > sag...@eecs.berkeley.edu; kbast...@mail.un

Re: [PATCH v3 4/4] Jobs based on custom runners: add job definitions for QEMU's machines

On Wed, Oct 14, 2020 at 05:14:01PM -0400, Cleber Rosa wrote: > On Wed, Oct 14, 2020 at 06:46:55PM +0100, Daniel P. Berrangé wrote: > > > > This bug links to > > > > https://bugs.launchpad.net/ubuntu/+source/libssh/+bug/1847514 > > > > which is marked as fixed. So I'm thinking we can drop the -

Re: [PATCH] qemu-palcode: Changes to support booting NetBSD/alpha

> On Oct 14, 2020, at 2:52 PM, Richard Henderson > wrote: > > I'm certainly open to these changes. But it'll need to be split up -- one > patch per bullet, basically. That's fine. What's the convention for patches that stack on top of one another? -- thorpej

Re: [PATCH 07/10] tcg: implement bulletproof JIT

There's about 40 instances of *code_ptr or code_ptr[i] changed to TCG_CODE_PTR_RW(s, code_ptr). It's around 2 instances per function, so if I go with a local variable, that would be ~20 extra LOC. Another alternative is two separate functions: tcg_code_ptr_insn_rw() which returns tcg_insn_unit * a

[PATCH] docs: Print warning when running Sphinx 3.x and newer

This won't prevent the docs from being built, but will let people know Sphinx 3.x is not fully supported yet. Signed-off-by: Eduardo Habkost --- docs/conf.py | 5 + 1 file changed, 5 insertions(+) diff --git a/docs/conf.py b/docs/conf.py index 00e1b750e2..1d92e65d12 100644 --- a/docs/conf.p

[PATCH] meson.build: don't condition iconv detection on library detection

It isn't necessarily the case that use of iconv requires an additional library. For that reason we shouldn't conditionalize iconv detection on libiconv.found. Fixes: 5285e593c33 (configure: Fixes ncursesw detection under msys2/mingw by convert them to meson) Signed-off-by: Bruce Rogers --- mes

Re: [PATCH] Changes to support booting NetBSD/alpha

On 10/6/20 8:24 PM, Jason Thorpe wrote: > Along with the previous patch set for qemu-palcode, these changes > allow NetBSD/alpha to run in qemu-system-alpha. > > - Allow a the minimum PCI device number to be passed to typhoon_init(). > Use this to specify a minimum PCI device number of 1 in the

Re: [PATCH] qemu-palcode: Changes to support booting NetBSD/alpha

On 10/6/20 7:52 PM, Jason Thorpe wrote: > There are additional changes in Qemu itself. Those will be sent as > a follow-up. > > - Change the $a2 value at VM start from "cpu count" to "config word". Bits > 0-5 are cpu count, and bit 6 communicates the "-nographic" option from > the VM. > - Pr

CACHE_NAME in .travis.yml (was Re: [Qemu-devel] [PATCH 08/10] .travis.yml: Cache Linux/GCC 'debug profile' jobs together)

I just stumbled upon this when editing .travis.yml, and I'm trying to understand how the $CACHE_NAME trick is supposed to work. If I understood the Travis documentation correctly, all environment variables will affect the cache id (including $CONFIG, in the case below). This would mean the two en

Re: [PATCH 07/10] tcg: implement bulletproof JIT

On 10/14/20 1:58 PM, Joelle van Dyne wrote: > Much of the code that uses the macro is like the following (from > aarch64/tcg-include.inc.c) > > *TCG_CODE_PTR_RW(s, code_ptr) = > deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 0, 26, offset); > > Before the change, it was just *code_p

Re: [PATCH 07/10] tcg: implement bulletproof JIT

On 10/14/20 1:54 PM, BALATON Zoltan wrote: >> static inline void *tcg_code_ptr_rw(TCGContext *s, void *rx) >> { >> #ifdef CONFIG_IOS_JIT >>    return rx + s->code_rw_mirror_diff; > > This looks better but can you add to void *? I think some compilers may > complain about that so may need to cast h

[PATCH] hw/arm/strongarm: Fix 'time to transmit a char' unit comment

The time to transmit a char is expressed in nanoseconds, not in ticks. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/strongarm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index d7133eea6f9..ca7c385f313 100644 --- a/hw/arm/stron

Re: [PATCH v3 4/4] Jobs based on custom runners: add job definitions for QEMU's machines

On Wed, Oct 14, 2020 at 06:46:55PM +0100, Daniel P. Berrangé wrote: > On Wed, Oct 14, 2020 at 01:21:40AM -0400, Cleber Rosa wrote: > > The QEMU project has two machines (aarch64 and s390) that can be used > > for jobs that do build and run tests. This introduces those jobs, > > which are a mapping

Re: [PATCH 07/10] tcg: implement bulletproof JIT

On Wed, 14 Oct 2020, Joelle van Dyne wrote: Much of the code that uses the macro is like the following (from aarch64/tcg-include.inc.c) *TCG_CODE_PTR_RW(s, code_ptr) = deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 0, 26, offset); Before the change, it was just *code_ptr. I'm saying

Re: [PATCH 07/10] tcg: implement bulletproof JIT

Much of the code that uses the macro is like the following (from aarch64/tcg-include.inc.c) *TCG_CODE_PTR_RW(s, code_ptr) = deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 0, 26, offset); Before the change, it was just *code_ptr. I'm saying the alternative was to have to write "tcg_i

Re: [PATCH 07/10] tcg: implement bulletproof JIT

On Wed, 14 Oct 2020, Richard Henderson wrote: On 10/14/20 9:03 AM, Joelle van Dyne wrote: static int encode_search(TranslationBlock *tb, uint8_t *block) { -uint8_t *highwater = tcg_ctx->code_gen_highwater; -uint8_t *p = block; +uint8_t *highwater; +uint8_t *p; int i, j, n; +

Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

On Wed, Oct 14, 2020 at 1:20 PM Victor Kamensky (kamensky) wrote: > > In order just to keep on the same thread, here is piece of information > I found: > > I looked at "MIPS32® 34Kf™ Processor Core Datasheet" [1] > > Page 8 in "Joint TLB (JTLB)" section says: > > "The JTLB is a fully associative T

Re: [PATCH v2 04/15] python: add directory structure README.rst files

On 10/14/20 2:05 PM, Philippe Mathieu-Daudé wrote: On 10/14/20 4:29 PM, John Snow wrote: Add short readmes to python/, python/qemu/, and python/qemu/core that explain the directory hierarchy. These readmes are visible when browsing Maybe readmes -> READMEs If you want it to match the filena

Re: [PATCH v11 09/13] copy-on-read: skip non-guest reads if no copy needed

On 14.10.2020 15:51, Max Reitz wrote: On 12.10.20 19:43, Andrey Shinkevich wrote: If the flag BDRV_REQ_PREFETCH was set, pass it further to the COR-driver to skip unneeded reading. It can be taken into account for the COR-algorithms optimization. That check is being made during the block stream

Re: [PATCH 5/7] dockerfiles: enable Centos 8 PowerTools

On Wed, Oct 14, 2020 at 09:54:14AM -0400, Paolo Bonzini wrote: > ninja is included in the CentOS PowerTools repository. > > Signed-off-by: Paolo Bonzini > --- > tests/docker/dockerfiles/centos8.docker | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/tests/docker/dockerfiles/centos8.d

Re: [PATCH 07/10] tcg: implement bulletproof JIT

On 10/14/20 9:03 AM, Joelle van Dyne wrote: >>> static int encode_search(TranslationBlock *tb, uint8_t *block) >>> { >>> -uint8_t *highwater = tcg_ctx->code_gen_highwater; >>> -uint8_t *p = block; >>> +uint8_t *highwater; >>> +uint8_t *p; >>> int i, j, n; >>> >>> +highwater

Re: [PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address

On 10/14/20 3:17 AM, Yifei Jiang wrote: > +if (fault_pte_addr) { > +*fault_pte_addr = (base + idx * ptesize) >> 2; The shift is wrong. It should be exactly like... > +} > +return TRANSLATE_G_STAGE_FAIL; > } > >

Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

In order just to keep on the same thread, here is piece of information I found: I looked at "MIPS32® 34Kf™ Processor Core Datasheet" [1] Page 8 in "Joint TLB (JTLB)" section says: "The JTLB is a fully associative TLB cache containing 16, 32, or 64-dual-entries mapping up to 128 virtual pages to

Re: [PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address

On Wed, Oct 14, 2020 at 3:18 AM Yifei Jiang wrote: > > VS-stage translation at get_physical_address needs to translate pte > address by G-stage translation. But the G-stage translation error > can not be distinguished from VS-stage translation error in > riscv_cpu_tlb_fill. On migration, destinati

Re: [PATCH 5/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

> The if is redundant, since that will have been done in cpu_get_tb_cpu_state while assigning pm_enabled. I totally agree here, however I tried to do explicit checks, so this functionality is available only if a special option is supplied. But if you think that's too much and I could do just mov(ds

Re: [PATCH v11 06/13] block: modify the comment for BDRV_REQ_PREFETCH flag

On 14.10.2020 15:22, Max Reitz wrote: On 12.10.20 19:43, Andrey Shinkevich wrote: Modify the comment for the flag BDRV_REQ_PREFETCH as we are going to use it alone and pass it to the COR-filter driver for further processing. Signed-off-by: Andrey Shinkevich --- include/block/block.h | 7

Re: [PATCH 4/5] [RISCV_PM] Add address masking functions required for RISC-V Pointer Masking extension

> I suggest adding a stub version of this function to patch 5, and then swap patch 4 and patch 5. Thanks, will do. >This bakes in values from ENV without adding any way to verify that those values are still current. If I correctly get your idea, you're talking about the situation, when DisasContex

Re: [PULL 5/9] configure: Fixes ncursesw detection under msys2/mingw by convert them to meson

I believe we shouldn't be conditionalizing running the iconv c program detection on the iconv library having been found. At least that's my semi-uninformed analysis so far. - Bruce From: 罗勇刚(Yonggang Luo) Sent: Wednesday, October 14, 2020 1:17 PM To: Bru

Re: [PATCH v2 2/3] accel/tcg: split tcg_start_vcpu_thread

On 10/14/20 12:23 PM, Claudio Fontana wrote: > +++ b/accel/tcg/tcg-cpus-mttcg.h > @@ -10,14 +10,4 @@ > #ifndef TCG_CPUS_MTTCG_H > #define TCG_CPUS_MTTCG_H > > -/* > - * Multi-threaded TCG > - * > - * In the multi-threaded case each vCPU has its own thread. The TLS > - * variable current_cpu can

Re: [PULL 00/10] migration queue

On Sun, Oct 11, 2020 at 07:29:25PM +0100, Peter Maydell wrote: > > Migration: > > Dirtyrate measurement API cleanup > > Postcopy recovery fixes > > > > Virtiofsd: > > Missing qemu_init_exec_dir call > > Support for setting the group on socket creation > > Stop a gcc warning > > Avoid te

Re: [RFC PATCH 0/4] generic loader FDT support (for direct Xen boot)

On Tue, Oct 13, 2020 at 3:11 AM Alex Bennée wrote: > > > Edgar E. Iglesias writes: > > > On Mon, Oct 12, 2020 at 05:02:57PM +0100, Alex Bennée wrote: > >> > >> Alistair Francis writes: > >> > >> > On Fri, Oct 9, 2020 at 10:07 AM Alex Bennée > >> > wrote: > >> >> > >> >> Hi, > >> >> > >> >> Thi

Re: [PATCH 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs

First of all thank you so much for reviewing these patches! >RVJ. Thanks, I missed this typo, will fix it. >Probably you only want to dump the set that's current. I don't know for sure how anyone would be using this while debugging PM related code, but I like the idea, so I'll try to do it, thank

Re: [PATCH] hw/usb/hcd-dwc2: fix divide-by-zero in dwc2_handle_packet()

On Tue, Oct 13, 2020 at 10:41 AM Gerd Hoffmann wrote: > > On Tue, Oct 13, 2020 at 12:19:40AM -0700, Paul Zimmerman wrote: > > I sent you a patch to fix up several assert()s, including that one, about a > > month ago. Did you miss it? > > https://lore.kernel.org/qemu-devel/20200920021449.830-1-paul

Re: [PATCH] target/riscv: Fix implementation of HLVX.WU instruction

On Tue, Oct 13, 2020 at 10:23 AM Georg Kotheimer wrote: > > The HLVX.WU instruction is supposed to read a machine word, > but prior to this change it read a byte instead. > > Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis Thanks! Applied to riscv-to-apply.next Alistair > --- >

Re: [PATCH] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt

On Tue, Oct 13, 2020 at 10:31 AM Georg Kotheimer wrote: > > The hstatus.GVA bit was not set if the faulting guest virtual address > was zero. > > Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu_helper.c |

Re: [PATCH v2 1/3] accel/tcg: split CpusAccel into three TCG variants

On 10/14/20 12:23 PM, Claudio Fontana wrote: > split up the CpusAccel tcg_cpus into three TCG variants: > > tcg_cpus_rr (single threaded, round robin cpus) > tcg_cpus_icount (same as rr, but with instruction counting enabled) > tcg_cpus_mttcg (multi-threaded cpus) > > Suggested-by: Richard Hender

Re: [PATCH] target/riscv: Fix update of hstatus.SPVP

On Tue, Oct 13, 2020 at 8:11 AM Georg Kotheimer wrote: > > When trapping from virt into HS mode, hstatus.SPVP was set to > the value of sstatus.SPP, as according to the specification both > flags should be set to the same value. > However, the assignment of SPVP takes place before SPP itself is >

Re: [PATCH v4 08/12] tests/9pfs: change qtest name prefix to synth

On Wed, 14 Oct 2020 17:25:35 +0200 Christian Schoenebeck wrote: > On Donnerstag, 8. Oktober 2020 20:34:56 CEST Christian Schoenebeck wrote: > > All existing 9pfs test cases are using the 'synth' fs driver so far, which > > means they are not accessing real files, but a purely simulated (in RAM >

Re: [PATCH] arm/trace: Fix hex printing

On 10/14/20 9:33 PM, Dr. David Alan Gilbert (git) wrote: From: "Dr. David Alan Gilbert" Use of 0x%d - make up our mind as 0x%x Uh... Reviewed-by: Philippe Mathieu-Daudé (hw/arm/... in subject) Signed-off-by: Dr. David Alan Gilbert --- hw/arm/trace-events | 2 +- 1 file changed, 1 in

Re: [PATCH v2 3/3] accel/tcg: rename tcg-cpus functions to match module name

On 10/14/20 9:23 PM, Claudio Fontana wrote: Signed-off-by: Claudio Fontana --- accel/tcg/tcg-cpus-icount.c | 24 ++-- accel/tcg/tcg-cpus-icount.h | 6 +-- accel/tcg/tcg-cpus-mttcg.c | 10 ++--- accel/tcg/tcg-cpus-rr.c | 74 ++--- accel/tcg/tcg-

Re: [PATCH v2 1/3] accel/tcg: split CpusAccel into three TCG variants

On 10/14/20 9:23 PM, Claudio Fontana wrote: split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson Signed-o

Re: [PATCH v2 7/8] migration: Open brace '{' following function declarations go on the next line

* Bihong Yu (yubih...@huawei.com) wrote: > Signed-off-by: Bihong Yu > Reviewed-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert > --- > migration/rdma.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/migration/rdma.c b/migration/rdma.c > index 0eb42b7..ca4d315

[PATCH] arm/trace: Fix hex printing

From: "Dr. David Alan Gilbert" Use of 0x%d - make up our mind as 0x%x Signed-off-by: Dr. David Alan Gilbert --- hw/arm/trace-events | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c8a4d80f6b..a335ee891d 100644 --- a/hw/arm/tra

Re: [PATCH v2 2/8] migration: Don't use '#' flag of printf format

* Bihong Yu (yubih...@huawei.com) wrote: > Signed-off-by: Bihong Yu > Reviewed-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert > --- > migration/block.c | 2 +- > migration/ram.c | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/migration/block.c b/migration

[PATCH v2 2/3] accel/tcg: split tcg_start_vcpu_thread

after the initial split into 3 tcg variants, we proceed to also split tcg_start_vcpu_thread. We actually split it in 2 this time, since the icount variant just uses the round robin function. Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana --- accel/tcg/tcg-all.c | 5 +++

Re: [PATCH 5/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

On 10/14/20 10:01 AM, Alexey Baturo wrote: > +if (has_ext(ctx, RVJ)) { > +src1 = apply_pointer_masking(ctx, src1); > +} The if is redundant, since that will have been done in cpu_get_tb_cpu_state while assigning pm_enabled. The test for pm_enabled is in gen_pm_adjust_address. The

Re: [PATCH v3 2/4] Jobs based on custom runners: build environment docs and playbook

On Wed, Oct 14, 2020 at 02:59:58PM -0400, Cleber Rosa wrote: > On Wed, Oct 14, 2020 at 06:30:09PM +0100, Daniel P. Berrangé wrote: > > > > This needs updating to add meson, and with Paolo's series today you > > might as well go ahead and add ninja-build immediately too > > I replied too quickly,

Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson wrote: > > On 10/14/20 3:21 AM, Jiangyifei wrote: > >> Would this be a good time to expand mstatus to uint64_t instead of > >> target_ulong so that it can be saved as one unit and reduce some ifdefs in > >> the > >> code base? > >> > >> Similarly

[PATCH v2 1/3] accel/tcg: split CpusAccel into three TCG variants

split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana --- accel/tcg/meson.b

Re: [PULL 5/9] configure: Fixes ncursesw detection under msys2/mingw by convert them to meson

If iconv installed then it's the meson's probme that didn't found the iconv properly On Thu, Oct 15, 2020 at 2:22 AM Bruce Rogers wrote: > > On Wed, 2020-10-14 at 10:21 +0200, Gerd Hoffmann wrote: > > From: Yonggang Luo > > > > The mingw pkg-config are showing following absolute path and contains

Re: [PATCH v2] hw/intc: Move sifive_plic.h to the include directory

On Tue, Oct 13, 2020 at 1:31 AM Bin Meng wrote: > > Since sifive_plic.h is used by hw/intc/sifive_plic.c, > it has to be in the public include directory. Move it. > > Fixes: 84fcf3c15111 ("hw/riscv: Move sifive_plic model to hw/intc") > Signed-off-by: Bin Meng > Reviewed-by: Philippe Mathieu-Daud

[PATCH v2 3/3] accel/tcg: rename tcg-cpus functions to match module name

Signed-off-by: Claudio Fontana --- accel/tcg/tcg-cpus-icount.c | 24 ++-- accel/tcg/tcg-cpus-icount.h | 6 +-- accel/tcg/tcg-cpus-mttcg.c | 10 ++--- accel/tcg/tcg-cpus-rr.c | 74 ++--- accel/tcg/tcg-cpus-rr.h | 2 +- accel/tcg/tcg-cpus.c

[PATCH v2 0/3] tcg-cpus: split into 3 tcg variants

The purpose of this series is to split the tcg-cpus into 3 variants: tcg_cpus_mttcg(multithreaded tcg vcpus) tcg_cpus_rr (single threaded round robin vcpus) tcg_cpus_icount (same as RR, but using icount) Ciao, Claudio v1 -> v2: * fixed file preambles to be clearer (Philippe) * rewo

Re: [PATCH v2 5/8] migration: Add braces {} for if statement

* Bihong Yu (yubih...@huawei.com) wrote: > Signed-off-by: Bihong Yu > Reviewed-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert > --- > migration/ram.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/migration/ram.c b/migration/ram.c > index 0aea78f..09178cc

Re: [PATCH v2 6/8] migration: Do not initialise statics and globals to 0 or NULL

* Bihong Yu (yubih...@huawei.com) wrote: > Signed-off-by: Bihong Yu > Reviewed-by: Chuan Zheng OK, sometimes I find initialisation clearer Reviewed-by: Dr. David Alan Gilbert > --- > migration/ram.c| 2 +- > migration/savevm.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-)

Re: [PATCH 4/5] [RISCV_PM] Add address masking functions required for RISC-V Pointer Masking extension

On 10/14/20 10:01 AM, Alexey Baturo wrote: > +static TCGv_i64 apply_pointer_masking(DisasContext *s, TCGv_i64 addr) > +{ > +gen_pm_adjust_address(s, addr, addr); > +return addr; > +} This function is unused in this patch, which means the series as a whole is non-bisectable. Rather than me

Re: [PULL 5/9] configure: Fixes ncursesw detection under msys2/mingw by convert them to meson

Because you didn't install the iconv. On Thu, Oct 15, 2020 at 2:22 AM Bruce Rogers wrote: > > On Wed, 2020-10-14 at 10:21 +0200, Gerd Hoffmann wrote: > > From: Yonggang Luo > > > > The mingw pkg-config are showing following absolute path and contains > > : as the separator, > > > > -D_XOPEN_SOUR

Re: [PATCH v2 8/8] migration: Delete redundant spaces

* Bihong Yu (yubih...@huawei.com) wrote: > Signed-off-by: Bihong Yu > Reviewed-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert > --- > migration/rdma.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/migration/rdma.c b/migration/rdma.c > index ca4d315..00eac34 10

Re: [PATCH v3 2/4] Jobs based on custom runners: build environment docs and playbook

On Wed, Oct 14, 2020 at 06:30:09PM +0100, Daniel P. Berrangé wrote: > On Wed, Oct 14, 2020 at 01:21:38AM -0400, Cleber Rosa wrote: > > To run basic jobs on custom runners, the environment needs to be > > properly set up. The most common requirement is having the right > > packages installed. > >

Re: [PATCH v11 05/13] copy-on-read: limit COR operations to base in COR driver

On 14.10.2020 15:01, Max Reitz wrote: On 12.10.20 19:43, Andrey Shinkevich wrote: Limit COR operations by the base node in the backing chain when the overlay base node name is given. It will be useful for a block stream job when the COR-filter is applied. The overlay base node is passed as the b

Re: [RFC PATCH v5 2/2] hw/riscv: sifive_u: Add backend drive support

On Wed, Oct 14, 2020 at 8:02 AM Bin Meng wrote: > > Hi Alistair, > > On Wed, Oct 14, 2020 at 10:46 PM Alistair Francis > wrote: > > > > On Wed, Sep 30, 2020 at 12:10 AM Green Wan wrote: > > > > > > On Wed, Sep 30, 2020 at 1:08 AM Alistair Francis > > > wrote: > > > > > > > > On Mon, Sep 28, 2

Re: [PATCH 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs

On 10/14/20 10:01 AM, Alexey Baturo wrote: > +if (riscv_has_ext(env, RVH)) { RVJ. > +qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte", env->mmte); > +qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", env->upmbase); > +qemu_fprintf(f, " %s " TARGET_FMT_lx "\n"

[Bug 1899728] Re: Qemu-5.1.0 build from source man entry not found

Hello together, build with enable-docs and install the required packages now it works with man qemu. Many thanks for you help Problem resolved :-) Best regards Damian ** Changed in: qemu Status: Incomplete => Confirmed ** Changed in: qemu Status: Confirmed => Fix Released --

Re: [PULL 5/9] configure: Fixes ncursesw detection under msys2/mingw by convert them to meson

On Wed, 2020-10-14 at 10:21 +0200, Gerd Hoffmann wrote: > From: Yonggang Luo > > The mingw pkg-config are showing following absolute path and contains > : as the separator, > > -D_XOPEN_SOURCE=600 -D_POSIX_C_SOURCE=199506L -IC:/CI- > Tools/msys64/mingw64/include/ncursesw:-I/usr/include/ncursesw:

Re: [PATCH RESEND] pci: Disallow improper BAR registration for type 1

On 10/14/20 7:56 PM, Ben Widawsky wrote: On 20-10-14 13:52:29, Michael S. Tsirkin wrote: On Wed, Oct 14, 2020 at 10:18:53AM -0700, Ben Widawsky wrote: This patch informs future developers working on root complexes, root ports, or bridges that also wish to implement a BAR for those. PCI type 1 h

Re: [PATCH v2 13/15] python: move .isort.cfg into setup.cfg

On 10/14/20 4:29 PM, John Snow wrote: Signed-off-by: John Snow --- python/.isort.cfg | 7 --- python/setup.cfg | 8 2 files changed, 8 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 01/15] python: create qemu.core package

On 10/14/20 4:29 PM, John Snow wrote: move python/qemu/*.py to python/qemu/core/*.py and update import directives across the tree. This is done to create a PEP420 namespace package, in which we may create subpackages. To do this, the namespace directory ("qemu") should not have any modules in it

[PATCH v3 3/5] tools/virtiofsd: xattr name mappings: Map server xattr names

From: "Dr. David Alan Gilbert" Map xattr names coming from the server, i.e. the host filesystem; currently this is only from listxattr. Signed-off-by: Dr. David Alan Gilbert --- tools/virtiofsd/passthrough_ll.c | 89 1 file changed, 89 insertions(+) diff --git

Re: [PATCH v2 04/15] python: add directory structure README.rst files

On 10/14/20 4:29 PM, John Snow wrote: Add short readmes to python/, python/qemu/, and python/qemu/core that explain the directory hierarchy. These readmes are visible when browsing Maybe readmes -> READMEs Otherwise: Reviewed-by: Philippe Mathieu-Daudé the source on e.g. gitlab/github and a

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