Hi
On Wed, Dec 16, 2020 at 2:41 AM Eduardo Habkost wrote:
> QOM reference counting bugs are often hard to detect, but there's
> one kind of bug that's easier: if we are freeing an object but is
> still attached to a parent, it means the reference count is wrong
> (because the parent always hold
John Snow writes:
> On 11/13/20 11:48 AM, Markus Armbruster wrote:
>> John Snow writes:
>>
>>> The typing of _make_tree and friends is a bit involved, but it can be
>>> done with some stubbed out types and a bit of elbow grease. The
>>> forthcoming patches attempt to make some simplifications,
On Wed, Dec 16, 2020 at 2:41 AM Eduardo Habkost wrote:
> commit 1e419ee68fa5 ("chardev: generate an internal id when none
> given") changed the reference ownership semantics of
> qemu_chardev_new(NULL, ...): now all chardevs created using
> qemu_chardev_new() are added to the /chardevs QOM contai
On Mon, 7 Dec 2020 at 22:48, Steven Price wrote:
>
> On 04/12/2020 08:25, Haibo Xu wrote:
> > On Fri, 20 Nov 2020 at 17:51, Steven Price wrote:
> >>
> >> On 19/11/2020 19:11, Marc Zyngier wrote:
> >>> On 2020-11-19 18:42, Andrew Jones wrote:
> On Thu, Nov 19, 2020 at 03:45:40PM +, Peter
On Tue, Dec 15, 2020 at 12:55:50PM +0100, Andrew Jones wrote:
> On Tue, Dec 15, 2020 at 03:19:48PM +0800, Keqian Zhu wrote:
> > The parameters start and size are transfered from QEMU memory
> > emulation layer. It can promise that they are TARGET_PAGE_SIZE
> > aligned. However, KVM needs they are q
John Snow writes:
> On 11/16/20 5:12 AM, Markus Armbruster wrote:
>> John Snow writes:
>>
>>> This replaces _make_tree with Annotated(). By creating it as a generic
>>> container, we can more accurately describe the exact nature of this
>>> particular value. i.e., each Annotated object is actua
On Tue, Dec 15, 2020 at 06:20:48PM +, David Edmondson wrote:
> On Tuesday, 2020-12-15 at 18:48:15 +01, Andrew Jones wrote:
>
> > virt machine's 'smp_cpus' and machine->smp.cpus must always have the
> > same value. And, anywhere we have virt machine state we have machine
> > state. So let's rem
AVX512 Half-precision floating point (FP16) has better performance
compared to FP32 if the presicion or magnitude requirements are met.
It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23].
Refer to
https://software.intel.com/content/www/us/en/develop/download/\
intel-architecture-instruction-set-exten
John Snow writes:
> On 11/16/20 4:46 AM, Markus Armbruster wrote:
>> John Snow writes:
>>
>>> Returning two different types conditionally can be complicated to
>>> type. Let's always return a tuple for consistency. Prohibit the use of
>>> annotations with dict-values in this circumstance. It ca
user --static builds are apparently resulting in dynamically linked
executables (to the glibc library, not other shared objects )
Concise summary:
$ file ../qemu-aarch64_v*
../qemu-aarch64_v4.2.1: ELF 64-bit LSB executable, x86-64, version 1
(GNU/Linux), statically linked,
BuildID[sha1]=70f5e10a
On Mon, Dec 14, 2020 at 11:05:50AM +0100, Greg Kurz wrote:
65;6201;1c> It is currently impossible to hot-unplug a memory device between
> machine reset and CAS.
>
> (qemu) device_del dimm1
> Error: Memory hot unplug not supported for this guest
>
> This limitation was introduced in order to provi
On Mon, Dec 14, 2020 at 12:19:55PM +0100, Greg Kurz wrote:
> Section 13.5.2 of LoPAPR mandates various DR related indentifiers
> for all hot-pluggable entities to be exposed in the "ibm,drc-indexes",
> "ibm,drc-power-domains", "ibm,drc-names" and "ibm,drc-types" properties
> of their parent node. T
From: Andrey Shinkevich
This patch completes the series with the COR-filter applied to
block-stream operations.
Adding the filter makes it possible in future implement discarding
copied regions in backing files during the block-stream job, to reduce
the disk overuse (we need control on permissio
From: Andrey Shinkevich
Add the new member supported_read_flags to the BlockDriverState
structure. It will control the flags set for copy-on-read operations.
Make the block generic layer evaluate supported read flags before they
go to a block driver.
Suggested-by: Vladimir Sementsov-Ogievskiy
S
15.12.2020 22:01, David Edmondson wrote:
When a call to fcntl(2) for the purpose of manipulating file locks
fails, report the error returned by fcntl.
Signed-off-by: David Edmondson
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vladimir
Add a direct link to target bs for convenience and to simplify
following commit which will insert COR filter above target bs.
This is a part of original commit written by Andrey.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
---
block/stream.c | 23 ++-
From: Andrey Shinkevich
If the flag BDRV_REQ_PREFETCH was set, skip idling read/write
operations in COR-driver. It can be taken into account for the
COR-algorithms optimization. That check is being made during the
block stream job by the moment.
Add the BDRV_REQ_PREFETCH flag to the supported_re
From: Andrey Shinkevich
Provide API for the COR-filter removal. Also, drop the filter child
permissions for an inactive state when the filter node is being
removed.
To insert the filter, the block generic layer function
bdrv_insert_node() can be used.
The new function bdrv_cor_filter_drop() may b
test_stream_parallel run parallel stream jobs, intersecting so that top
of one is base of another. It's OK now, but it would be a problem if
insert the filter, as one job will want to use another job's filter as
above_base node.
Correct thing to do is move to new interface: "bottom" argument inste
From: Andrey Shinkevich
The test case #310 is similar to #216 by Max Reitz. The difference is
that the test #310 involves a bottom node to the COR filter driver.
Signed-off-by: Andrey Shinkevich
Signed-off-by: Vladimir Sementsov-Ogievskiy
[vsementsov: detach backing to test reads from top, l
From: Andrey Shinkevich
Add support for the recently introduced functions
bdrv_co_preadv_part()
and
bdrv_co_pwritev_part()
to the COR-filter driver.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/copy-on-read.c | 28
1 file ch
From: Andrey Shinkevich
Stream in stream_prepare calls bdrv_change_backing_file() to change
backing-file in the metadata of bs.
It may use either backing-file parameter given by user or just take
filename of base on job start.
Backing file format is determined by base on job finish.
There are
From: Andrey Shinkevich
Add an option to limit copy-on-read operations to specified sub-chain
of backing-chain, to make copy-on-read filter useful for block-stream
job.
Suggested-by: Max Reitz
Suggested-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Andrey Shinkevich
Signed-off-by: Vladimir
The code already don't freeze base node and we try to make it prepared
for the situation when base node is changed during the operation. In
other words, block-stream doesn't own base node.
Let's introduce a new interface which should replace the current one,
which will in better relations with the
From: Andrey Shinkevich
Provide API for insertion a node to backing chain.
Suggested-by: Max Reitz
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
---
include/block/block.h | 2 ++
block.c | 25 +
2 fil
Hi all!
Here is a new version of cor-filter in block-stream series. Main change
is freezing the chain in cor-filter itself.
v15:
02: s/ = / = /
add Max's r-b
03: add Max's r-b
04: since: 6.0
indent comment
add Max's r-b
05: changed commit msg
wording
document the default
From: Andrey Shinkevich
Provide the possibility to pass the 'filter-node-name' parameter to the
block-stream job as it is done for the commit block job.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
[vsementsov: comment indentation, s/Since: 5.2/Since: 6.0/]
Revi
- Original Message -
> Jason Wang writes:
>
> [...]
> > One more stupid question, instead of generating the string via hard
> > codes, is there any method (dict?) to iterate all the key/values
> > automatically?
>
> QAPI visitors.
>
> The lazy way: use the QObject output visitor to c
Eduardo Habkost writes:
> On Tue, Dec 15, 2020 at 03:11:06PM +0100, Markus Armbruster wrote:
>> Eduardo Habkost writes:
>>
>> > Class properties make QOM introspection simpler and easier, as
>> > they don't require an object to be instantiated.
>> >
>> > Signed-off-by: Eduardo Habkost
>>
>> T
Hi,
Is there a way to know the support plans for CXL protocol in QEMU?
I see that there is side branch development going on:
https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v2
But when does it get merged and gets released in QEMU formally?
Is there a way to know a rough timeline?
Regards,
Prashan
在 2020/12/16 上午10:50, Jiaxun Yang 写道:
TBH I do think it doesn't sounds like a good idea to make 32-bit
and 64-bit different. In fact ISA_MIPS32R6 is always set for targets
with ISA_MIPS64R6.
We're treating MIPS64R6 as a superset of MIPS32R6, and ISA_MIPS3
is used to tell if a CPU supports 6
在 2020/12/16 上午7:48, Philippe Mathieu-Daudé 写道:
On 12/16/20 12:27 AM, Richard Henderson wrote:
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
+bool isa_rel6_available(const CPUMIPSState *env)
+{
+if (TARGET_LONG_BITS == 64) {
+return cpu_supports_isa(env, ISA_MIPS64R6);
+
It should be 53308.
See clock_set_hz.
Signed-off-by: Jiaxun Yang
---
hw/mips/fuloong2e.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 256c7867e4..af2d259dc4 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -1
highmem started from 0x2000.
Now we can have up to 2G RAM.
Signed-off-by: Jiaxun Yang
---
hw/mips/fuloong2e.c | 49 -
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index af2d259dc4..dec6ac
modetty and busclock is not handled by kernel and the parameter
here seems unreasonable.
Signed-off-by: Jiaxun Yang
---
hw/mips/fuloong2e.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index a5b75b230a..256c7867e4 100644
--- a/hw/mips/fuloong2e.c
The original mapping had wrong base address.
Fix by correct the base adress and merge three alias into
a single.
Signed-off-by: Jiaxun Yang
---
hw/pci-host/bonito.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
Websites are downing, but GitHub may last forever.
Loongson even doesn't recogonize 2E as their products nowadays..
Signed-off-by: Jiaxun Yang
---
hw/mips/fuloong2e.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
inde
Accroading to arch/mips/pci/fixup-fuloong2e.c in kernel,
despites south bridge IRQs needs special care, all other
IRQ pins are mapped by 'LOONGSON_IRQ_BASE + 25 + pin'.
As south bridge IRQs are all handled by ISA bus, we can simply
remove BONITO_IRQ_BASE and direct map IRQs here.
Signed-off-by: J
Seems useless
Signed-off-by: Jiaxun Yang
---
hw/mips/fuloong2e.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 9b0eb8a314..055b99e378 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -48,8 +48,6 @@
#include "sysemu/reset.h"
It can now boot Debian installer[1].
I'm going to add acceptance test for it later.
Thanks.
Jiaxun Yang (7):
hw/mips/fuloong2e: Remove define DEBUG_FULOONG2E_INIT
hw/mips/fuloong2e: Relpace fault links
hw/pci-host/bonito: Fixup IRQ mapping
hw/pci-host/bonito: Fixup pci.lomem mapping
hw/
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/bitmanip_helper.c | 72 +
target/riscv/helper.h | 7 +++
target/riscv/insn32-64.decode | 2 +
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/tran
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 22 ++
target/riscv/translate.c| 6 ++
3 files changed, 31 insertions(+)
diff --git a/
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 61 +
target/riscv/translate.c| 36 +
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/bitmanip_helper.c | 31 ++
target/riscv/helper.h | 2 ++
target/riscv/insn32-64.decode | 2 ++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 8 ++
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvb.c.inc | 90 +
target/riscv/translate.c| 102
From: Kito Cheng
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 4
target/riscv/cpu.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/ri
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 13 +
2 files changed, 15 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvb.c.inc | 24
2 files changed, 28 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.d
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvb.c.inc | 58 +
target/riscv/translate.c| 13 +
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++
target/riscv/translate.c| 32 ++
From: Frank Chang
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 12
target/riscv/translate.c| 6 ++
4 files cha
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18ca..3823b3ea800 100644
--- a/target/riscv/i
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 30 ++
target/riscv/translate.c| 41
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++
target/riscv/translate.c| 21 +
3 files changed, 43 insertions(+)
d
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 7 +++-
target/riscv/insn_trans/trans_rvb.c.inc | 47 +
target/riscv/translate.c| 42 ++
From: Frank Chang
This patchset implements RISC-V B-extension draft version Zbb, Zbs and
Zba subset instructions. Some Zbp instructions are also implemented as
they have similar behavior with their Zbb-, Zbs- and Zba-family
instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
Specific
Currently if the cross compiler passed to 'configure' (--cross-cc-) does
not exist no error happens and only later when the TCG tests are run they fail
because the cross compiler is not set correctly.
This commit changes that behavior and make 'configure' fail if the specified
cross compiler canno
On Tue, Dec 15, 2020 at 06:40:25PM +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Applied to ppc-for-6.0, thanks.
> ---
> include/hw/ppc/spapr_xive.h | 2 --
> hw/intc/spapr_xive.c| 2 +-
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/include/hw/pp
On Tue, Dec 15, 2020 at 06:36:51PM +0100, Greg Kurz wrote:
> All memory DRC objects are created during machine init. It is thus safe
> to assume spapr_drc_by_id() cannot return NULL when hot-plug/unplugging
> memory.
>
> Make this clear with an assertion, like the code already does a few lines
> a
Hi Dmitry,
Looks good to me, thanks for sticking with it.
Reviewed-by: Keith Busch
On 12/16/20 12:27 AM, Richard Henderson wrote:
> On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
>> +bool isa_rel6_available(const CPUMIPSState *env)
>> +{
>> +if (TARGET_LONG_BITS == 64) {
>> +return cpu_supports_isa(env, ISA_MIPS64R6);
>> +}
>> +return cpu_supports_isa(env,
On 12/15/20 6:48 PM, Richard Henderson wrote:
> In f47db80cc07, we handled odd-sized tail clearing for
> the case of hosts that have vector operations, but did
> not handle the case of hosts that do not have vector ops.
>
> This was ok until e2e7168a214b, which changed the encoding
> of simd_desc
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> Add the LSA opcode to the MSA32 decodetree config, add DLSA
> to a new config for the MSA64 ASE, and call decode_msa64()
> in the main decode_opc() loop.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/mod-msa32.decode| 4 ++
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> +bool isa_rel6_available(const CPUMIPSState *env)
> +{
> +if (TARGET_LONG_BITS == 64) {
> +return cpu_supports_isa(env, ISA_MIPS64R6);
> +}
> +return cpu_supports_isa(env, ISA_MIPS32R6);
> +}
So... does qemu-system-mips64 sup
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> Make gen_msa() and gen_msa_branch() public declarations
> so we can keep calling them once extracted from the big
> translate.c in the next commit.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 2 ++
> target/mips
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> As we will slowly move to decodetree generated decoders,
> extract the legacy decoding from decode_opc(), so new
> decoders are added in decode_opc() while old code is
> removed from decode_opc_legacy().
>
> Signed-off-by: Philippe Mathieu-Daudé
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> translate_init.c.inc mostly contains CPU definitions.
> msa_reset() doesn't belong here, move it with the MSA
> helpers.
>
> One comment style is updated to avoid checkpatch.pl warning.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> Simplify gen_check_zero_element() by passing the TCGCond
> argument along.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Maybe this can be named 'msa_translate.c' after all...
> ---
> target/mips/mod-msa_
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> LSA and LDSA opcodes are also available with MIPS release 6.
> Introduce the decodetree config files and call the decode()
> helpers in the main decode_opc() loop.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> Now that we can decode the MSA ASE opcodes with decode_msa32(),
> use it and remove the unreachable code.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 12
> target/mips/mod-msa_translate.c |
On 12/15/20 4:29 PM, Philippe Mathieu-Daudé wrote:
> On 12/15/20 4:09 PM, Peter Maydell wrote:
>> This patchseries makes some changes to the clock API:
>> * Remove clock_get_ns()
>> * Add clock_ticks_to_ns() to return number of nanoseconds
>>it will take the clock to tick N times
>> * clock_
On 12/15/20 11:43 PM, Richard Henderson wrote:
> On 12/14/20 4:09 PM, Philippe Mathieu-Daudé wrote:
>> On 12/14/20 3:02 PM, Richard Henderson wrote:
>>> Create a function to determine if a pointer is within the buffer.
>>>
>>> Signed-off-by: Richard Henderson
>>> ---
>>> include/tcg/tcg.h
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
>
> We decode the branch instructions, and all instructions based
> on the MSA opcode.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 3
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> Extract gen_lsa() from translate.c and explode it as
> gen_LSA() and gen_DLSA().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h| 6
> target/mips/translate.c| 35 +++-
>
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
Maybe this can be named 'msa_translate.c' after all...
---
target/mips/mod-msa_translate.c | 10 --
1 file changed, 4 insertions(+), 6 delet
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 1 +
target/mips/isa-mips32r6.decode | 17 +
Now that we can decode the MSA ASE opcodes with decode_msa32(),
use it and remove the unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 12
target/mips/mod-msa_translate.c | 29 +
target/mips/translate.c
MSA means 'MIPS SIMD Architecture' and is defined as a Module by
MIPS.
To keep the directory sorted, we use the 'mod' prefix for MIPS
modules. Rename msa_helper.c as mod-msa_helper.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201123204448.3260804-4-f4...
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mod-msa32.decode| 4
target/mips/mod-msa64.decode| 17 +
targe
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD]-> BxZ(true)
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Sign
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletion
We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'mod-msa_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201123204448.3260804-5-f4...@amsat.org>
---
target/mips/mod-msa_helper.c | 393 ++
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h| 6
target/mips/translate.c| 35 +++-
target/mips/translate_addr_const.c | 52 +++
The msa_wr_d[] registers are only initialized/used by MSA.
They are declared static. We want to move them to the new
'mod-msa_translate.c' unit in few commits, without having to
declare them global (with extern).
Extract first the logic initialization of the MSA registers
from the generic initial
The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 57 -
1 file changed, 28 insertions(+),
Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
We decode the branch instructions, and all instructions based
on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 3 +++
target/mips/mod-msa32.decode| 24 +
ta
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 2 ++
target/mips/cpu.c| 1 +
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
It is not very clear to have FPU registers displayed with MSA
register names, ev
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 5 +
target/mips/cpu-defs.c.inc | 4
2 files changed, 5 insertions(+
We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h| 1 -
target/mips/cpu-defs.c.inc | 8
2 files cha
Keep all MSA-related code altogether.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201120210844.2625602-4-f4...@amsat.org>
---
target/mips/helper.h | 436 +-
target/mips/mod-msa_helper.h.inc | 443 +++
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 6 ++
target/mips/cpu.c
As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 45 ---
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 2 --
Introduce the isa_rel6_available() helper to check if the
CPU supports the Release 6 ISA.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 1 +
target/mips/cpu.c | 8
2 files changed, 9 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3ac21d0e9c0..c6a
MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mi
Missing review: 1-3 14 17 19-24
Since v1:
- rebased
- addressed Richard review comments
- reworded some commit descriptions
- avoid 64-bit ifdef'ry
Finally, we use decodetree with the MIPS target.
Starting easy with the MSA ASE. 2700+ lines extracted
from helper.h and translate.c, now built as a
Patchew URL:
https://patchew.org/QEMU/20201215162119.27360-1-zhangjiachen.jay...@bytedance.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201215162119.27360-1-zhangjiachen.jay...@bytedance.com
Subject: [RFC PATC
On 12/14/20 8:05 PM, Joelle van Dyne wrote:
> Should qemu-options.hx be updated?
Yep, good catch.
r~
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