Re: QOM address space handling

2020-12-17 Thread Mark Cave-Ayland
On 10/11/2020 11:40, Paolo Bonzini wrote: On 10/11/20 12:14, Mark Cave-Ayland wrote: There are 2 possible solutions here: 1) ensure QOM objects that add address spaces during instance init have a corresponding instance finalize function to remove them or 2) move the creation of address spaces

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

2020-12-17 Thread Bin Meng
Hi Atish, On Fri, Dec 18, 2020 at 3:27 PM Atish Patra wrote: > > On Fri, 2020-12-18 at 15:21 +0800, Bin Meng wrote: > > Hi Atish, > > > > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra > > wrote: > > > > > > Currently, we place the DTB at 2MB from 4GB or end of DRAM which > > > ever is > > > lesser

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

2020-12-17 Thread Atish Patra
On Fri, 2020-12-18 at 15:21 +0800, Bin Meng wrote: > Hi Atish, > > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra > wrote: > > > > Currently, we place the DTB at 2MB from 4GB or end of DRAM which > > ever is > > lesser. However, Linux kernel can address only 1GB of memory for > > RV32. > > Thus, it

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

2020-12-17 Thread Bin Meng
Hi Atish, On Fri, Dec 18, 2020 at 5:48 AM Atish Patra wrote: > > Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is > lesser. However, Linux kernel can address only 1GB of memory for RV32. > Thus, it can not map anything beyond 3GB (assuming 2GB is the starting > address).

Re: [PATCH v2 2/2] s390x/pci: Fix memory_region_access_valid call

2020-12-17 Thread Thomas Huth
On 17/12/2020 23.16, Matthew Rosato wrote: > In pcistb_service_handler, a call is made to validate that the memory > region can be accessed. However, the call is made using the entire length > of the pcistb operation, which can be larger than the allowed memory > access size (8). Since we already

Re: [PATCH v6 3/3] block: qcow2: remove the created file on initialization error

2020-12-17 Thread Vladimir Sementsov-Ogievskiy
17.12.2020 20:09, Maxim Levitsky wrote: If the qcow initialization fails, we should remove the file if it was already created, to avoid leaving stale files around. We already do this for luks raw images. Signed-off-by: Maxim Levitsky Reviewed-by: Alberto Garcia Reviewed-by: Vladimir Sementsov

Re: [PATCH v6 2/3] block: add bdrv_co_delete_file_noerr

2020-12-17 Thread Vladimir Sementsov-Ogievskiy
17.12.2020 20:09, Maxim Levitsky wrote: This function wraps bdrv_co_delete_file for the common case of removing a file, which was just created by format driver, on an error condition. It hides the -ENOTSUPP error, and reports all other errors otherwise. Use it in luks driver Signed-off-by: Max

[PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout

2020-12-17 Thread Alistair Francis
OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.fran...@wdc.com --- include/hw/riscv/opentitan.h |

Re: [PATCH] acpi: Add addr_trans in build_crs

2020-12-17 Thread Jiahui Cen
Hi Michael, On 2020/12/18 2:32, Michael S. Tsirkin wrote: > On Thu, Dec 17, 2020 at 09:27:47PM +0800, Jiahui Cen wrote: >> AML needs Address Translation offset to describe how a bridge translates >> addresses accross the bridge when using an address descriptor, and >> especially on ARM, the transl

[PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: ac75037dd58061486de421a0fcd9ac8a92014607.1608142916.git.alistair.fran...@wdc.com --- hw/riscv/spike.c | 45 - 1 file changed, 24 i

[PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit

2020-12-17 Thread Alistair Francis
Instead of using string compares to determine if a RISC-V machine is using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids us having to maintain a list of CPU names to compare against. This commit also fixes the name of the function to match the riscv_cpu_is_32bit() function. Si

[PULL 21/23] target/riscv: cpu: Set XLEN independently from target

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.fran...@wdc.com --- target/riscv/cpu.c | 25 - 1 file changed, 1

[PULL 10/23] riscv: virt: Remove target macro conditionals

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.fran...@wdc.com --- include/hw/riscv/virt.h | 6 -- hw/riscv/virt.c | 2 +-

[PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.fran...@wdc.com --- include/hw/riscv/boot.h | 8 +++--- hw/riscv/boot.c | 55 ++

[PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 872d2dfcd1c7c3914655d677e911b9432eb8f340.1608142916.git.alistair.fran...@wdc.com --- target/riscv/cpu_helper.c | 12 +

[PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.fran...@wdc.com --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 + 2 files

[PULL 09/23] riscv: spike: Remove target macro conditionals

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.fran...@wdc.com --- include/hw/riscv/spike.h | 6 -- hw/riscv/spike.c | 2 +- 2 files changed, 1

[PULL 20/23] target/riscv: csr: Remove compile time XLEN checks

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Tested-by: Bin Meng Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.fran...@wdc.com --- target/riscv/cpu_bits.h | 4 +- target/riscv/csr.c | 176

[PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros

2020-12-17 Thread Alistair Francis
Update the function definitions generated in helper.h to match the actual function implementations. Also remove all compile time XLEN checks when building. Signed-off-by: Alistair Francis Message-id: 614c369cbd070873a647b8aac7e023cba145.1608142916.git.alistair.fran...@wdc.com --- target/ri

[PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.fran...@wdc.com --- target/riscv/cpu.h | 6 ++ 1 file changed, 6 insertions(+) diff

[PULL 17/23] target/riscv: Specify the XLEN for CPUs

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.fran...@wdc.com --- target/riscv/cpu.c | 33

[PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs

2020-12-17 Thread Alistair Francis
Currently the riscv_is_32_bit() function only supports the generic rv32 CPUs. Extend the function to support the SiFive and LowRISC CPUs as well. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916

[PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.fran...@wdc.com --- hw/riscv/sifive_u.c | 55 ---

[PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process

2020-12-17 Thread Alistair Francis
Previously if an interrupt occured during the claim process (after the interrupt is claimed but before it's completed) it would never be cleared. This patch ensures that we also clear the hidden_pending bits as well. Signed-off-by: Alistair Francis Tested-by: Jackie Ke Message-id: 4e9786084a86f

[PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV

2020-12-17 Thread Alistair Francis
From: Yifei Jiang We found that the hypervisor virtual-machine load and store instructions, included HLVX/HLV/HSV, couldn't access guest userspace memory. In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow: "As usual when V=1, two-stage address translation is applied, and the HS-lev

[PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.fran...@wdc.com --- hw/riscv/virt.c | 32 +--- 1 file change

[PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR

2020-12-17 Thread Alistair Francis
From: Alex Richardson The TW and TSR fields should be bits 21 and 22 and not 30/29. This was found while comparing QEMU behaviour against the sail formal model (https://github.com/rems-project/sail-riscv/). Signed-off-by: Alex Richardson Reviewed-by: Alistair Francis Message-id: 20201130170117

[PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash

2020-12-17 Thread Alistair Francis
From: Vitaly Wool Add QSPI NOR flash definition for Microchip PolarFire SoC. Signed-off-by: Vitaly Wool Acked-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20201112074950.33283-1-vitaly.w...@konsulko.com Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 3 ++

[PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB

2020-12-17 Thread Alistair Francis
From: Anup Patel The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 2020094725.3768755-1-anup.pa...@wdc.com Signed-off-by: Ali

[PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks

2020-12-17 Thread Alistair Francis
Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Tested-by: Bin Meng Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.fran...@wdc.com --- target/riscv/cpu.c | 19 ++--

[PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format

2020-12-17 Thread Alistair Francis
From: Xinhao Zhang Fix code style. Don't use '#' flag of printf format ('%#') in format strings, use '0x' prefix instead Signed-off-by: Xinhao Zhang Signed-off-by: Kai Deng Reviewed-by: Alistair Francis Message-id: 20201116140148.2850128-1-zhangxinh...@huawei.com Signed-off-by: Alistair Franc

Re: [PATCH] acpi/gpex: Inform os to keep firmware resource map

2020-12-17 Thread Jiahui Cen
Hi Michael, On 2020/12/18 2:29, Michael S. Tsirkin wrote: > On Thu, Dec 17, 2020 at 09:29:26PM +0800, Jiahui Cen wrote: >> There may be some differences in pci resource assignment between guest os >> and firmware. >> >> Eg. A Bridge with Bus [d2] >> -+-[:d2]---01.0-[d3]01.0 >> >> w

[PULL 00/23] riscv-to-apply queue

2020-12-17 Thread Alistair Francis
l-riscv-to-apply-20201217-1 for you to fetch changes up to d31e970a01e7399b9cd43ec0dc00c857d968987e: riscv/opentitan: Update the OpenTitan memory layout (2020-12-17 21:56:44 -0800) A collection of RISC-V improvements: - I

[PATCH v14 RESEND 18/21] multi-process: Synchronize remote memory

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Add ProxyMemoryListener object which is used to keep the view of the RAM in sync between QEMU and remote process. A MemoryListener is registered for system-memory AddressSpace. The listener sends SYNC_SYSMEM message to the remote process when memory listener commits the ch

[PATCH v14 RESEND 13/21] multi-process: setup memory manager for remote device

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman SyncSysMemMsg message format is defined. It is used to send file descriptors of the RAM regions to remote device. RAM on the remote device is configured with a set of file descriptors. Old RAM regions are deleted and new regions, each with an fd, is added to the RAM. Sign

Re: [PATCH] acpi/gpex: Inform os to keep firmware resource map

2020-12-17 Thread Jiahui Cen
Hi Michael, On 2020/12/18 4:04, Michael S. Tsirkin wrote: > On Thu, Dec 17, 2020 at 09:29:26PM +0800, Jiahui Cen wrote: >> There may be some differences in pci resource assignment between guest os >> and firmware. >> >> Eg. A Bridge with Bus [d2] >> -+-[:d2]---01.0-[d3]01.0 >> >> w

[PATCH v14 RESEND 14/21] multi-process: introduce proxy object

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Defines a PCI Device proxy object as a child of TYPE_PCI_DEVICE. Signed-off-by: Elena Ufimtseva Signed-off-by: Jagannathan Raman Signed-off-by: John G Johnson Reviewed-by: Stefan Hajnoczi --- include/hw/remote/proxy.h | 36 hw/remote/proxy.c |

[PATCH v14 RESEND 08/21] multi-process: add qio channel write function

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Adds qio_channel_writev_full_all() to transmit both data and FDs. Refactors existing code to use this function. Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman --- include/io/channel.h | 25 + io/chan

[PATCH v14 RESEND 11/21] multi-process: Initialize message handler in remote device

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Initializes the message handler function in the remote process. It is called whenever there's an event pending on QIOChannel that registers this function. Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by: Stefan

[PATCH v14 RESEND 16/21] multi-process: Forward PCI config space acceses to the remote process

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva The Proxy Object sends the PCI config space accesses as messages to the remote process over the communication channel Signed-off-by: Elena Ufimtseva Signed-off-by: Jagannathan Raman Signed-off-by: John G Johnson Reviewed-by: Stefan Hajnoczi --- include/hw/remote/mpqemu

[PATCH v14 RESEND 21/21] multi-process: perform device reset in the remote process

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Perform device reset in the remote process when QEMU performs device reset. This is required to reset the internal state (like registers, etc...) of emulated devices Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by

[PATCH v14 RESEND 12/21] multi-process: Associate fd of a PCIDevice with its object

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Associate the file descriptor for a PCIDevice in remote process with DeviceState object. Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by: Stefan Hajnoczi --- hw/remote/remote-obj.c | 194 ++

[PATCH v14 RESEND 09/21] multi-process: add qio channel read function

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Adds qio_channel_readv_full_all() to read both data and FDs. Refactors existing code to use this function. Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman --- include/io/channel.h | 25 io/channel.c

[PATCH v14 RESEND 20/21] multi-process: Retrieve PCI info from remote process

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Retrieve PCI configuration info about the remote device and configure the Proxy PCI object based on the returned information Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by: Stefan Hajnoczi --- hw/remote/proxy

[PATCH v14 RESEND 17/21] multi-process: PCI BAR read/write handling for proxy & remote endpoints

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Proxy device object implements handler for PCI BAR writes and reads. The handler uses BAR_WRITE/BAR_READ message to communicate to the remote process with the BAR address and value to be written/read. The remote process implements handler for BAR_WRITE/BAR_READ message. S

[PATCH v14 RESEND 05/21] multi-process: Add config option for multi-process QEMU

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Add configuration options to enable or disable multiprocess QEMU code Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Signed-off-by: Elena Ufimtseva --- configure | 10 ++ meson.build | 2 ++ Kconfig.host | 4 hw/Kconfi

[PATCH v14 RESEND 10/21] multi-process: define MPQemuMsg format and transmission functions

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Defines MPQemuMsg, which is the message that is sent to the remote process. This message is sent over QIOChannel and is used to command the remote process to perform various tasks. Define transmission functions used by proxy and by remote. Signed-off-by: Jagannathan Raman

[PATCH v14 RESEND 06/21] multi-process: setup PCI host bridge for remote device

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman PCI host bridge is setup for the remote device process. It is implemented using remote-pcihost object. It is an extension of the PCI host bridge setup by QEMU. Remote-pcihost configures a PCI bus which could be used by the remote PCI device to latch on to. Signed-off-by:

[PATCH v14 RESEND 19/21] multi-process: create IOHUB object to handle irq

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman IOHUB object is added to manage PCI IRQs. It uses KVM_IRQFD ioctl to create irqfd to injecting PCI interrupts to the guest. IOHUB object forwards the irqfd to the remote process. Remote process uses this fd to directly send interrupts to the guest, bypassing QEMU. Signed-

[PATCH v14 RESEND 15/21] multi-process: add proxy communication functions

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Signed-off-by: Elena Ufimtseva Signed-off-by: Jagannathan Raman Signed-off-by: John G Johnson Reviewed-by: Stefan Hajnoczi --- include/hw/remote/mpqemu-link.h | 4 hw/remote/mpqemu-link.c | 34 + 2 files changed, 38 insertio

[PATCH v14 RESEND 07/21] multi-process: setup a machine object for remote device process

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman x-remote-machine object sets up various subsystems of the remote device process. Instantiate PCI host bridge object and initialize RAM, IO & PCI memory regions. Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Signed-off-by: Elena Ufimtseva Reviewed-by: S

Re: [PATCH 11/12] qapi/schema: Name the builtin module "" instead of None

2020-12-17 Thread Markus Armbruster
John Snow writes: > On 12/17/20 6:09 AM, Markus Armbruster wrote: >> John Snow writes: >> >>> On 12/16/20 5:42 AM, Markus Armbruster wrote: John Snow writes: > Instead of using None as the built-in module filename, use an empty > string instead. PATCH 05's changes t

Re: [PATCH 08/12] qapi/schema: make QAPISourceInfo mandatory

2020-12-17 Thread Markus Armbruster
John Snow writes: > On 12/17/20 3:02 AM, Markus Armbruster wrote: >> John Snow writes: >> >>> On 12/16/20 5:18 AM, Markus Armbruster wrote: John Snow writes: > -- > > events.py had an info to route, was it by choice that it wasn't before? See below. I

Re: [PATCH v14 00/21] Initial support for multi-process Qemu

2020-12-17 Thread Elena Ufimtseva
On Thu, Dec 17, 2020 at 07:57:47PM -0800, elena.ufimts...@oracle.com wrote: > From: Elena Ufimtseva > > Hi > For some reason the patchset was not sent fully and only few patches made trough. I am resending the series with prefix in the subject "[PATCH v14 RESEND... " I am sorry for this inconve

Re: [PATCH v2 5/8] linux-user: Update SO_TIMESTAMP to SO_TIMESTAMP_OLD/NEW

2020-12-17 Thread Shu-Chun Weng
Ping again. This specific patch is here: https://patchew.org/QEMU/cover.1597129029.git@google.com/611db81c87911cb38a35e5f761e11b76e1f0d538.1597129029.git@google.com/ If you want to include the first four patches for now and prefer a separate patch set for the pending changes I can split th

Re: [PATCH v2 6/8] linux-user: setsockopt() SO_TIMESTAMPNS and SO_TIMESTAMPING

2020-12-17 Thread Shu-Chun Weng
Ping -- any comments on https://patchew.org/QEMU/cover.1597129029.git@google.com/c1fdce46c35527ea9da34ca26eab4efcdac407db.1597129029.git@google.com/ On Tue, Aug 11, 2020 at 12:10 AM Shu-Chun Weng wrote: > This change supports SO_TIMESTAMPNS_OLD/NEW and SO_TIMESTAMPING_OLD/NEW > for setso

Re: [PATCH v2 7/8] thunk: supports flexible arrays

2020-12-17 Thread Shu-Chun Weng
Ping -- any comments on https://patchew.org/QEMU/cover.1597129029.git@google.com/e0754f52180aee6418eae8b3b8aa5981fcac12fd.1597129029.git@google.com/ On Tue, Aug 11, 2020 at 2:39 PM Shu-Chun Weng wrote: > Forgot to +riku.voi...@iki.fi when generating v2. > > On Tue, Aug 11, 2020 at 12:10

[PATCH v14 01/21] multi-process: add the concept description to docs/devel/qemu-multiprocess

2020-12-17 Thread elena . ufimtseva
From: John G Johnson Signed-off-by: John G Johnson Signed-off-by: Elena Ufimtseva Signed-off-by: Jagannathan Raman Reviewed-by: Stefan Hajnoczi --- docs/devel/index.rst | 1 + docs/devel/multi-process.rst | 966 +++ MAINTAINERS | 7

[PATCH v14 02/21] multi-process: add configure and usage information

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Adds documentation explaining the command-line arguments needed to use multi-process. Signed-off-by: Elena Ufimtseva Signed-off-by: Jagannathan Raman Signed-off-by: John G Johnson Reviewed-by: Stefan Hajnoczi --- docs/multi-process.rst | 64

[PATCH v14 03/21] memory: alloc RAM from file at offset

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Allow RAM MemoryRegion to be created from an offset in a file, instead of allocating at offset of 0 by default. This is needed to synchronize RAM between QEMU & remote process. Signed-off-by: Jagannathan Raman Signed-off-by: John G Johnson Signed-off-by: Elena Ufimtseva

[PATCH v14 00/21] Initial support for multi-process Qemu

2020-12-17 Thread elena . ufimtseva
From: Elena Ufimtseva Hi This is the v14 of the patchset. Thank you very much for reviewing v13 and sharing your feedback. We have addressed all the comments from the v13 review with changelog below: - [PATCH v14 05/21] multi-process: Add config option for multi-process QEMU add config optio

[PATCH v14 04/21] socket: export socket_get_fd() function

2020-12-17 Thread elena . ufimtseva
From: Jagannathan Raman Export socket_get_fd() helper function. The function protorype is changed to be more generic. Use monitor_fd_param() instead of monitor_fd_get() in order to support named fds as well. Signed-off-by: Jagannathan Raman Signed-off-by: John G Johnson Signed-off-by: Elena Uf

Re: [PATCH v2 4/8] linux-user: Add IPv6 options to do_print_sockopt()

2020-12-17 Thread Shu-Chun Weng
Hi Laurent, The first 4 patches in the set (up to this) are self-contained. Is it possible to include them in your dev branch while the others are still waiting for review? (I'll ping the other threads separately). The first three patches are: https://lists.nongnu.org/archive/html/qemu-devel/20

Re: [PATCH qemu v12] spapr: Implement Open Firmware client interface

2020-12-17 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20201218025040.98132-1-...@ozlabs.ru/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201218025040.98132-1-...@ozlabs.ru Subject: [PATCH qemu v12] spapr: Implement Open Firmware cl

[PATCH qemu v12] spapr: Implement Open Firmware client interface

2020-12-17 Thread Alexey Kardashevskiy
The PAPR platform which describes an OS environment that's presented by a combination of a hypervisor and firmware. The features it specifies require collaboration between the firmware and the hypervisor. Since the beginning, the runtime component of the firmware (RTAS) has been implemented as a 2

[Bug 1908626] [NEW] Atomic test-and-set instruction does not work on qemu-user

2020-12-17 Thread taos
Public bug reported: I try to compile and run PostgreSQL/Greenplum database inside docker container/qemu-aarch64-static: ``` host: CentOS7 x86_64 container: centos:centos7.9.2009 --platform linux/arm64/v8 qemu-user-static: https://github.com/multiarch/qemu-user-static/releases/ ``` However, G

[PATCH v2 1/1] target-riscv: support QMP dump-guest-memory

2020-12-17 Thread Yifei Jiang
Add the support needed for creating prstatus elf notes. Now elf notes only contains user_regs. This allows us to use QMP dump-guest-memory. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li --- target/riscv/arch_dump.c | 189 +++ target/riscv/cpu.c

[PATCH v2 0/1] target-riscv: support QMP dump-guest-memory

2020-12-17 Thread Yifei Jiang
Hi, This patch supports QMP dump-guest-memory in RISC-V. We tested this feature by using following command: dump-guest-memory guest.memory. Then we used the gdb tool to debug guest.memory: gdb vmlinux guest.memory. The test result is as follow: 1. info registers ra 0xffe0008cb83c

[PATCH] tests/docker: Use lower case for centos8 powertools

2020-12-17 Thread Jiaxun Yang
Our gitlab amd64-centos8-container pipeline constantly fail at: 15.36 Error: No matching repo to modify: PowerTools. Fix it by convert it to lower case. Signed-off-by: Jiaxun Yang --- tests/docker/dockerfiles/centos8.docker | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/te

Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()

2020-12-17 Thread Eduardo Habkost
On Fri, Dec 18, 2020 at 01:07:33AM +0100, Claudio Fontana wrote: > On 12/18/20 12:47 AM, Eduardo Habkost wrote: > > On Fri, Dec 18, 2020 at 12:34:46AM +0100, Claudio Fontana wrote: > >> On 12/17/20 11:53 PM, Eduardo Habkost wrote: > >>> On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrot

[Bug 1907137] Re: LDTR not properly emulated when MTE tag checks enabled at EL0

2020-12-17 Thread Peter Collingbourne
The workaround patch above is insufficient if I change userspace to set TCF0=1. With that I get a kernel panic: [ 13.336255][C0] Bad mode in Synchronous Abort handler detected on CPU0, code 0x9211 -- DABT (lower EL) [ 13.337437][C0] CPU: 0 PID: 1 Comm: init Not tainted 5.10.0-rc7

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY

2020-12-17 Thread Claudio Fontana
On 12/18/20 12:47 AM, Claudio Fontana wrote: > On 12/17/20 11:49 PM, Peter Maydell wrote: >> On Thu, 17 Dec 2020 at 22:45, Claudio Fontana wrote: >>> >>> On 12/17/20 9:15 PM, Peter Maydell wrote: On Thu, 17 Dec 2020 at 19:46, Claudio Fontana wrote: Yeah, don't try to ifdef out struct fi

Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()

2020-12-17 Thread Claudio Fontana
On 12/18/20 12:47 AM, Eduardo Habkost wrote: > On Fri, Dec 18, 2020 at 12:34:46AM +0100, Claudio Fontana wrote: >> On 12/17/20 11:53 PM, Eduardo Habkost wrote: >>> On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: Hello all, On 12/17/20 7:46 PM, Eduardo Habkost wrote:

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY

2020-12-17 Thread Claudio Fontana
On 12/17/20 11:49 PM, Peter Maydell wrote: > On Thu, 17 Dec 2020 at 22:45, Claudio Fontana wrote: >> >> On 12/17/20 9:15 PM, Peter Maydell wrote: >>> On Thu, 17 Dec 2020 at 19:46, Claudio Fontana wrote: >>> Yeah, don't try to ifdef out struct fields in common-compiled code... >> >> or should I? U

Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()

2020-12-17 Thread Eduardo Habkost
On Fri, Dec 18, 2020 at 12:34:46AM +0100, Claudio Fontana wrote: > On 12/17/20 11:53 PM, Eduardo Habkost wrote: > > On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: > >> Hello all, > >> > >> On 12/17/20 7:46 PM, Eduardo Habkost wrote: > >>> From: Vitaly Kuznetsov > >>> > >>> As a p

Re: [PULL v2 00/11] testing and configure updates

2020-12-17 Thread Alex Bennée
Peter Maydell writes: > On Thu, 17 Dec 2020 at 09:43, Alex Bennée wrote: >> >> The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: >> >> Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' >> into staging (2020-12-15 21:24:31 +) >> >> are ava

Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()

2020-12-17 Thread Claudio Fontana
On 12/17/20 11:53 PM, Eduardo Habkost wrote: > On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: >> Hello all, >> >> On 12/17/20 7:46 PM, Eduardo Habkost wrote: >>> From: Vitaly Kuznetsov >>> >>> As a preparation to expanding Hyper-V CPU features early, move >>> hyperv_vendor_id ini

Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()

2020-12-17 Thread Eduardo Habkost
On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: > Hello all, > > On 12/17/20 7:46 PM, Eduardo Habkost wrote: > > From: Vitaly Kuznetsov > > > > As a preparation to expanding Hyper-V CPU features early, move > > hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce >

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY

2020-12-17 Thread Peter Maydell
On Thu, 17 Dec 2020 at 22:45, Claudio Fontana wrote: > > On 12/17/20 9:15 PM, Peter Maydell wrote: > > On Thu, 17 Dec 2020 at 19:46, Claudio Fontana wrote: > > Yeah, don't try to ifdef out struct fields in common-compiled code... > > or should I? Using > > #ifdef NEED_CPU_H > #ifdef CONFIG_SOFTMM

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY

2020-12-17 Thread Claudio Fontana
On 12/17/20 9:15 PM, Peter Maydell wrote: > On Thu, 17 Dec 2020 at 19:46, Claudio Fontana wrote: >> >> Hi, >> >> I would like to highlight the current dangerous state of NEED_CPU_H / >> CONFIG_SOFTMMU / CONFIG_USER_ONLY. > >> So our struct TcgCpuOperations in include/hw/core/cpu.h, >> which cont

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

2020-12-17 Thread Palmer Dabbelt
On Thu, 17 Dec 2020 14:35:10 PST (-0800), Atish Patra wrote: On Thu, 2020-12-17 at 14:31 -0800, Palmer Dabbelt wrote: On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote: > Currently, we place the DTB at 2MB from 4GB or end of DRAM which > ever is > lesser. However, Linux kernel can addr

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

2020-12-17 Thread Atish Patra
On Thu, 2020-12-17 at 14:31 -0800, Palmer Dabbelt wrote: > On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote: > > Currently, we place the DTB at 2MB from 4GB or end of DRAM which > > ever is > > lesser. However, Linux kernel can address only 1GB of memory for > > RV32. > > Thus, it can no

Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()

2020-12-17 Thread Claudio Fontana
Hello all, On 12/17/20 7:46 PM, Eduardo Habkost wrote: > From: Vitaly Kuznetsov > > As a preparation to expanding Hyper-V CPU features early, move > hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce > x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() > itself. this

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

2020-12-17 Thread Palmer Dabbelt
On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote: Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is lesser. However, Linux kernel can address only 1GB of memory for RV32. Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address). As a result

[PATCH v2 2/2] s390x/pci: Fix memory_region_access_valid call

2020-12-17 Thread Matthew Rosato
In pcistb_service_handler, a call is made to validate that the memory region can be accessed. However, the call is made using the entire length of the pcistb operation, which can be larger than the allowed memory access size (8). Since we already know that the provided buffer is a multiple of 8,

[PATCH v2 0/2] s390x/pci: some pcistb fixes

2020-12-17 Thread Matthew Rosato
Here are a few fixes pulled out of the 'Fixing s390 vfio-pci ISM support' patchset. v2: - Changed loop pattern for patch 2. @Thomas to be on the safe side I didn't include your RB since I changed code, please have a look. If there are further issues/comments I will address them after the holiday

[PATCH v2 1/2] s390x/pci: fix pcistb length

2020-12-17 Thread Matthew Rosato
In pcistb_service_call, we are grabbing 8 bits from a guest register to indicate the length of the store operation -- but per the architecture the length is actually defined by 13 bits of the guest register. Fixes: 863f6f52b7 ("s390: implement pci instructions") Signed-off-by: Matthew Rosato Revi

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY (was: [PATCH v11 7/7] cpu: introduce cpu_accel_instance_init)

2020-12-17 Thread Eduardo Habkost
On Thu, Dec 17, 2020 at 10:13:17PM +0100, Paolo Bonzini wrote: > I will take a look, CONFIG_USER_ONLY is definitely something that should be > poisoned. Thanks! I started looking at it, but I gave up when I realized how much work it would required. :) In any case, feel free to reuse the 2 small

[PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

2020-12-17 Thread Atish Patra
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is lesser. However, Linux kernel can address only 1GB of memory for RV32. Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address). As a result, it can not process DT and panic if opensbi dynamic firmware i

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY

2020-12-17 Thread Claudio Fontana
Hi Peter, thanks for your answer, On 12/17/20 9:15 PM, Peter Maydell wrote: > On Thu, 17 Dec 2020 at 19:46, Claudio Fontana wrote: >> >> Hi, >> >> I would like to highlight the current dangerous state of NEED_CPU_H / >> CONFIG_SOFTMMU / CONFIG_USER_ONLY. > >> So our struct TcgCpuOperations in

Re: [PATCH RFC 0/3] hw/block/nvme: dif-based end-to-end data protection support

2020-12-17 Thread Keith Busch
On Thu, Dec 17, 2020 at 10:02:19PM +0100, Klaus Jensen wrote: > From: Klaus Jensen > > This series adds support for extended LBAs and end-to-end data > protection. Marked RFC, since there are a bunch of issues that could use > some discussion. > > Storing metadata bytes contiguously with the log

[PATCH RFC 2/3] hw/block/nvme: refactor nvme_dma

2020-12-17 Thread Klaus Jensen
From: Klaus Jensen The nvme_dma function doesn't just do DMA (QEMUSGList-based) memory transfers; it also handles QEMUIOVector copies. Introduce the NvmeTxDirection enum and rename to nvme_tx. Remove mapping of PRPs/SGLs from nvme_tx and assert that they have been mapped previously. This allows

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY (was: [PATCH v11 7/7] cpu: introduce cpu_accel_instance_init)

2020-12-17 Thread Paolo Bonzini
I will take a look, CONFIG_USER_ONLY is definitely something that should be poisoned. Paolo Il gio 17 dic 2020, 21:26 Peter Maydell ha scritto: > On Thu, 17 Dec 2020 at 20:15, Peter Maydell > wrote: > > (So in theory we could make CONFIG_USER_ONLY > > a poisoned identifier but that will requir

[PATCH RFC 3/3] hw/block/nvme: end-to-end data protection

2020-12-17 Thread Klaus Jensen
From: Gollu Appalanaidu Add support for namespaces formatted with protection information in the form of the Data Integrity Field (DIF) where the protection information is contiguous with the logical block data (extended logical blocks). The type of end-to-end data protection (i.e. Type 1, Type 2

Re: [PATCH 11/12] qapi/schema: Name the builtin module "" instead of None

2020-12-17 Thread John Snow
On 12/17/20 6:09 AM, Markus Armbruster wrote: John Snow writes: On 12/16/20 5:42 AM, Markus Armbruster wrote: John Snow writes: Instead of using None as the built-in module filename, use an empty string instead. PATCH 05's changes the module name of the special system module for built-in

[PATCH RFC 0/3] hw/block/nvme: dif-based end-to-end data protection support

2020-12-17 Thread Klaus Jensen
From: Klaus Jensen This series adds support for extended LBAs and end-to-end data protection. Marked RFC, since there are a bunch of issues that could use some discussion. Storing metadata bytes contiguously with the logical block data and creating a physically extended logical block basically b

[PATCH RFC 1/3] nvme: add support for extended LBAs

2020-12-17 Thread Klaus Jensen
From: Gollu Appalanaidu This allows logical blocks to be extended with a number of metadata bytes specified by the new namespace parameter 'ms'. The additional bytes are stored immediately after each logical block. The Deallocated or Unwritten Logical Block Error recovery feature is not supporte

Re: [PULL 00/17] x86 queue, 2020-12-17

2020-12-17 Thread Peter Maydell
On Thu, 17 Dec 2020 at 18:46, Eduardo Habkost wrote: > > Note that this is using my new gitlab.com repository URL, which > was updated on commit f953c100693d ("MAINTAINERS: Update my git > repository URLs"). > > The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: > > Mer

Re: Logging, abnormal cases, ...

2020-12-17 Thread Dr. David Alan Gilbert
* Michael Tokarev (m...@tls.msk.ru) wrote: > Hi! > > I want to bring a topic which is mostly neglected in qemu but it is > one of very important, especially for serious usage of qemu. > > This is about logging of various events or even some unexpected events > coming from guest. > > Let's see fo

Re: dangers of current NEED_CPU_H, CONFIG_SOFTMMU, CONFIG_USER_ONLY (was: [PATCH v11 7/7] cpu: introduce cpu_accel_instance_init)

2020-12-17 Thread Eduardo Habkost
On Thu, Dec 17, 2020 at 08:15:38PM +, Peter Maydell wrote: > On Thu, 17 Dec 2020 at 19:46, Claudio Fontana wrote: > > > > Hi, > > > > I would like to highlight the current dangerous state of NEED_CPU_H / > > CONFIG_SOFTMMU / CONFIG_USER_ONLY. > > > So our struct TcgCpuOperations in include/h

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