Hi Ben,
On 1/13/21 4:29 AM, Bin Meng wrote:
> On Wed, Jan 13, 2021 at 2:35 AM Philippe Mathieu-Daudé
> wrote:
>>
>> Hi,
>>
>> As it is sometimes harder for me to express myself in plain
>> English, I found it easier to write the patches I was thinking
>> about. I know this doesn't scale.
>>
>>
This is my qemu binary compiled with --prefix=/nonexistent
bash-5.1# ./qemu-system-x86_64 -L help
/usr/share/qemu
/usr/share/qemu-firmware
/usr/src/sources/qemu-5.2.0/build/pc-bios
bash-5.1# ./qemu-system-x86_64 --help|grep helper
On 21/12/2020 01.53, Jiaxun Yang wrote:
As per POSIX specification of limits.h [1], OS libc may define
PAGE_SIZE in limits.h.
To prevent collosion of definition, we rename PAGE_SIZE here.
[1]: https://pubs.opengroup.org/onlinepubs/7908799/xsh/limits.h.html
Signed-off-by: Jiaxun Yang
---
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 22 ++
target/riscv/translate.c| 6 ++
3 files
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 36 +
- the same size for secure and non secure gpio. Arm doc says that
secure memory is also split on 4k pages. So one page here has to be
ok.
- will add dtb.
- I think then less options is better. So I will remove
vmc->secure_gpio flag and keep only vmc flag.
Regards,
Maxim.
On Tue, 12 Jan 2021 at
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvb.c.inc | 48 +
On 21/12/2020 01.53, Jiaxun Yang wrote:
As per POSIX specification of limits.h [1], OS libc may define
PAGE_SIZE in limits.h.
Self defined PAGE_SIZE is frequently used in tests, to prevent
collosion of definition, we give PAGE_SIZE definitons reasonable
prefixs.
[1]:
On 21/12/2020 01.53, Jiaxun Yang wrote:
As per POSIX specification of limits.h [1], OS libc may define
PAGE_SIZE in limits.h.
To prevent collosion of definition, we rename PAGE_SIZE here.
[1]: https://pubs.opengroup.org/onlinepubs/7908799/xsh/limits.h.html
Signed-off-by: Jiaxun Yang
---
On 21/12/2020 01.53, Jiaxun Yang wrote:
As per POSIX specification of limits.h [1], OS libc may define
PAGE_SIZE in limits.h.
To prevent collosion of definition, we discard PAGE_SIZE from
defined by libc and take QEMU's variable.
[1]:
From: Frank Chang
Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
interfaces for immediate shift instructions.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvi.c.inc | 54 ++---
target/riscv/translate.c| 43
From: Kito Cheng
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 4
target/riscv/cpu.h | 2 ++
2 files
From: Kito Cheng
Signed-off-by: Kito Cheng
Reviewed-by: Richard Henderson
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 12
2 files changed, 14 insertions(+)
diff --git a/target/riscv/insn32.decode
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/bitmanip_helper.c | 31 +
target/riscv/helper.h | 2 ++
target/riscv/insn32-64.decode | 2 ++
target/riscv/insn32.decode |
From: Kito Cheng
Signed-off-by: Kito Cheng
Reviewed-by: Richard Henderson
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvb.c.inc | 24
2 files changed, 28 insertions(+)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/bitmanip_helper.c | 71 +
target/riscv/helper.h | 7 +++
target/riscv/insn32-64.decode | 2 +
target/riscv/insn32.decode |
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++
From: Frank Chang
Signed-off-by: Kito Cheng
Reviewed-by: Richard Henderson
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 12
target/riscv/translate.c
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 8 +++
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvb.c.inc | 90 +
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 30 +++
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 7 +++-
target/riscv/insn_trans/trans_rvb.c.inc | 47 +
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++
2 files changed, 22 insertions(+)
diff --git
From: Frank Chang
This patchset implements RISC-V B-extension 0.93 version Zbb, Zbs and
Zba subset instructions. Some Zbp instructions are also implemented as
they have similar behavior with their Zbb-, Zbs- and Zba-family
instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
Kindly ping. This patch still not on the master branch.
Please take it on your tree.
Thanks.
On 2020/12/7 18:10, Philippe Mathieu-Daudé wrote:
> On 12/7/20 9:37 AM, shiliyang wrote:
>> This patch fixes error style problems found by checkpatch.pl:
>> ERROR: spaces required around that '*'
>>
On 21/12/2020 01.53, Jiaxun Yang wrote:
Musl libc complains about it's wrong usage.
In file included from ../subprojects/libvhost-user/libvhost-user.h:20,
from ../subprojects/libvhost-user/libvhost-user-glib.h:19,
from
On 21/12/2020 01.53, Jiaxun Yang wrote:
signal.h is equlevant of sys/signal.h on Linux, musl would complain
wrong usage of sys/signal.h.
In file included from /builds/FlyGoat/qemu/include/qemu/osdep.h:108,
from ../tests/qemu-iotests/socket_scm_helper.c:13:
In the subject:
s/clk_adjtime/clock_adjtime/
On 21/12/2020 01.53, Jiaxun Yang wrote:
It is not a part of standard time.h. Glibc put it under
time.h however musl treat it as a sys timex extension.
Signed-off-by: Jiaxun Yang
---
configure | 1 +
1 file changed, 1 insertion(+)
diff --git
On 13.01.21 01:57, David Gibson wrote:
> On Tue, Jan 12, 2021 at 12:36:07PM +0100, Cornelia Huck wrote:
> 65;6201;1c> On Tue, 12 Jan 2021 09:15:26 +0100
>> Christian Borntraeger wrote:
>>
>>> On 12.01.21 05:45, David Gibson wrote:
At least some s390 cpu models support "Protected
Hi Peter,
Friendly ping again, It's been more than a month since I submitted the
patch,did I miss any response?
On 2020/12/31 10:26, zhouyang (T) wrote:
> kindly ping
>
> On 2020/12/17 11:44, zhouyang (T) wrote:
>> kindly ping
>>
>>> v1 -> v2:
>>> Changed the "From:" and "Signed-off-by:" lines
On 12/01/2021 23.37, John Snow wrote:
I wanted to know what the minimal setup required was to replicate the
compilation instructions featured on https://www.qemu.org/download/#source
[...]
> pixman-devel \
pixman is only required for the softmmu and tools targets. If you just build
the
Update all users of do_perm_pred2 for the new
predicate descriptor field definitions.
Cc: qemu-sta...@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1908551
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c| 8
target/arm/translate-sve.c | 13 -
2 files
Update all users of do_perm_pred3 for the new
predicate descriptor field definitions.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c| 18 +-
target/arm/translate-sve.c | 12
2 files changed, 13 insertions(+), 17
SVE predicate operations cannot use the "usual" simd_desc
encoding, because the lengths are not a multiple of 8.
But we were abusing the SIMD_* fields to store values anyway.
This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214.
Introduce a new set of field definitions for exclusive
These two were odd, in that do_pfirst_pnext passed the
count of 64-bit words rather than bytes. Change to pass
the standard pred_full_reg_size to avoid confusion.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c| 7 ---
target/arm/translate-sve.c
There was an inconsistency between encoding, which uses
SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS.
This happened to be ok, until e2e7168a214, which reduced
the size of SIMD_OPRSZ_BITS, which lead to truncating all
predicate vector lengths.
Changes in v2:
* Introduce and use
This prevents illegal instruction on cpus do not support xgetbv.
Buglink: https://bugs.launchpad.net/qemu/+bug/1758819
Signed-off-by: Hill Ma
---
v3: addressed feedback.
v2: xgetbv() modified based on feedback.
target/i386/hvf/x86_cpuid.c | 34 ++
1 file
Looks like one reported by OSS-Fuzz:
Here's a reproducer
cat << EOF | ./qemu-system-i386 -qtest stdio -display none \
-machine q35,accel=qtest -m 512M -nodefaults \
-device megasas -device scsi-cd,drive=null0 \
-blockdev driver=null-co,read-zeroes=on,node-name=null0
outl 0xcf8 0x8801
outl
On 12/01/2021 22.02, Joshua Watt wrote:
There are two cases that need to be accounted for when compiling QEMU
for MinGW32:
1) A standalone distribution, where QEMU is self contained and
extracted by the user, such as a user would download from the QEMU
website. In this case, all the
On 12/01/2021 19.50, Wainer dos Santos Moschetta wrote:
Hi,
On 1/12/21 1:40 PM, Thomas Huth wrote:
Let's gather the POWER-related tests in a separate file.
Did you consider having others ppc/ppc64 boot tests together too?
Some candidates:
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1791796
Title:
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1787070
Title:
Guests
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1759337
Title:
'Failed to
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1788701
Title:
"Zoom to
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1787002
Title:
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1788275
Title:
-cpu
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1800401
Title:
efifb on
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1800088
Title:
Assertion
On Tue, Jan 12, 2021 at 09:46:17AM +, Daniel P. Berrangé wrote:
> On Tue, Jan 12, 2021 at 03:44:57PM +1100, David Gibson wrote:
> > Several architectures have mechanisms which are designed to protect guest
> > memory from interference or eavesdropping by a compromised hypervisor. AMD
> > SEV
Pages can't be both write and executable at the same time on Apple
Silicon. macOS provides public API to switch write protection [1] for
JIT applications, like TCG.
1.
https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon
Signed-off-by: Roman
Hi Philippe,
On Wed, Jan 13, 2021 at 2:35 AM Philippe Mathieu-Daudé wrote:
>
> Hi,
>
> As it is sometimes harder for me to express myself in plain
> English, I found it easier to write the patches I was thinking
> about. I know this doesn't scale.
>
> So this is how I understand the ecSPI reset
From: "Rao, Lei"
The data pointer has skipped vnet_hdr_len in the function of
parse_packet_early().So, we can not subtract vnet_hdr_len again
when calculating pkt->header_size in fill_pkt_tcp_info(). Otherwise,
it will cause network packet comparsion errors and greatly increase
the frequency of
From: "Rao, Lei"
When we use continuous dirty memory copy for flushing ram cache on
secondary VM, we can also clean up the bitmap of contiguous dirty
page memory. This also can reduce the VM stop time during checkpoint.
Signed-off-by: Lei Rao
---
migration/ram.c | 29
From: "Rao, Lei"
When flushing memory from ram cache to ram during every checkpoint
on secondary VM, we can copy continuous chunks of memory instead of
4096 bytes per time to reduce the time of VM stop during checkpoint.
Signed-off-by: Lei Rao
---
migration/ram.c | 44
From: "Rao, Lei"
We can detect disk migration in migrate_prepare, if disk migration
is enabled in COLO mode, we can directly report an error.and there
is no need to disable block migration at every checkpoint.
Signed-off-by: Lei Rao
Signed-off-by: Zhang Chen
---
migration/colo.c | 6
From: "Rao, Lei"
The iov_size has been calculated in filter_send(). we can directly
return the size.In this way, this is no need to repeat calculations
in filter_redirector_receive_iov();
Signed-off-by: Lei Rao
---
net/filter-mirror.c | 8
1 file changed, 4 insertions(+), 4
From: "Rao, Lei"
This patch fixes the following:
#0 __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:50
#1 0x7f6ae4559859 in __GI_abort () at abort.c:79
#2 0x559aaa386720 in error_exit (err=16, msg=0x559aaa5973d0
<__func__.16227> "qemu_mutex_destroy") at
From: "Rao, Lei"
if we put the data copy outside the packet_new(), then for the
filter-rewrite module, there will be one less memory copy in the
processing of each network packet.
Signed-off-by: Lei Rao
---
net/colo-compare.c| 7 +--
net/colo.c| 4 ++--
net/colo.h
The series of patches include:
Fixed some bugs of qemu crash.
Optimized some code to reduce the time of checkpoint.
Remove some unnecessary code to improve COLO.
Rao, Lei (10):
Remove some duplicate trace code.
Fix the qemu crash when guest shutdown during checkpoint
From: "Rao, Lei"
If we don't disable the feature of auto-converge for live migration
before entering COLO mode, it will continue to run with COLO running,
and eventually the system will hang due to the CPU throttle reaching
DEFAULT_MIGRATE_MAX_CPU_THROTTLE.
Signed-off-by: Lei Rao
---
From: "Rao, Lei"
This patch fixes the following:
qemu-system-x86_64: invalid runstate transition: 'colo' ->'shutdown'
Aborted (core dumped)
Signed-off-by: Lei Rao
---
softmmu/runstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/softmmu/runstate.c b/softmmu/runstate.c
index
From: "Rao, Lei"
There is the same trace code in the colo_compare_packet_payload.
Signed-off-by: Lei Rao
---
net/colo-compare.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
index 84db497..9e18baa 100644
--- a/net/colo-compare.c
+++
在 2021/1/10 上午4:16, BALATON Zoltan 写道:
This device is part of the multifunction VIA superio/south bridge chip
so not useful in itself.
Signed-off-by: BALATON Zoltan
Reviewed-by: Jiaxun Yang
---
hw/isa/vt82c686.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
在 2021/1/10 上午4:16, BALATON Zoltan 写道:
The superio memory region holds the io space index/data registers used
to access the superio config registers that are implemented in struct
SuperIOConfig. To keep these related things together move the memory
region to SuperIOConfig and rename it
在 2021/1/13 上午6:25, BALATON Zoltan 写道:
On Tue, 12 Jan 2021, Jiaxun Yang wrote:
在 2021/1/10 上午4:16, BALATON Zoltan 写道:
The base address of the SMBus io ports and its enabled status is set
by registers in the PCI config space but this was not correctly
emulated. Instead the SMBus registers were
在 2021/1/13 上午5:54, Philippe Mathieu-Daudé 写道:
Loongson is next step in the "MIPS decodetree conversion" epic.
Start with the simplest extension.
The diffstat addition comes from the TCG functions expanded.
The code is easier to review now.
IMO this is also a good template to show how easy a
在 2021/1/13 上午5:54, Philippe Mathieu-Daudé 写道:
There is no issue having multiple enum declarations with
the same value. As we are going to remove the OPC_MULT_G_2E
definition in few commits, restore the OPC_ADDUH_QB_DSP and
OPC_MUL_PH_DSP definitions and use them where they belong.
This was reported by OSS-Fuzz as Issue 27389
Here is a minimized reproducer:
=== Reproducer ===
cat << EOF | ./qemu-system-i386 -display none\
-machine accel=qtest -m 512M -machine q35 -nodefaults \
-device e1000e,netdev=net0 -netdev user,id=net0 -qtest stdio
outl 0xcf8 0x8811
outl 0xcfc
On Tue, Jan 12, 2021 at 05:40:45PM +0100, Thomas Huth wrote:
> The "And a hippo new year" image from the QEMU advent calendar 2020
> can be used to test the virtex-ml507 ppc machine.
>
> Signed-off-by: Thomas Huth
Acked-by: David Gibson
> ---
> tests/acceptance/machine_ppc.py | 18
On Tue, Jan 12, 2021 at 05:40:43PM +0100, Thomas Huth wrote:
> Let's gather the POWER-related tests in a separate file.
>
> Signed-off-by: Thomas Huth
Acked-by: David Gibson
> ---
> MAINTAINERS| 1 +
> tests/acceptance/boot_linux_console.py | 19 --
>
On Fri, Jan 08, 2021 at 06:31:27PM +0100, Greg Kurz wrote:
> Since commit 1e8b5b1aa16b ("spapr: Allow memory unplug to always succeed")
> trying to unplug memory from a guest that doesn't support it (eg. rhel6)
> no longer generates an error like it used to. Instead, it leaves the
> memory around
On Tue, Jan 12, 2021 at 05:40:44PM +0100, Thomas Huth wrote:
> We can use the "Stupid creek" image to test the mpc8544ds ppc machine.
>
> Signed-off-by: Thomas Huth
Acked-by: David Gibson
> ---
> tests/acceptance/machine_ppc.py | 17 +
> 1 file changed, 17 insertions(+)
>
>
On Tue, 2021-01-12 at 16:02 +, Peter Maydell wrote:
> On Tue, 12 Jan 2021 at 15:23, Qiuhao Li
> wrote:
> > Fix Bug 1910826 [1] / OSS-Fuzz Issue 29224 [2].
> >
> > In rtl8139.c, the function rtl8139_RxBuf_write, which sets the
> > RxBuf
> > (Receive Buffer Start Address), doesn't check if
On Tue, Jan 12, 2021 at 12:36:07PM +0100, Cornelia Huck wrote:
65;6201;1c> On Tue, 12 Jan 2021 09:15:26 +0100
> Christian Borntraeger wrote:
>
> > On 12.01.21 05:45, David Gibson wrote:
> > > At least some s390 cpu models support "Protected Virtualization" (PV),
> > > a mechanism to protect
On Tue, Jan 12, 2021 at 09:56:12AM +, Daniel P. Berrangé wrote:
> On Tue, Jan 12, 2021 at 03:45:05PM +1100, David Gibson wrote:
> > Some upcoming POWER machines have a system called PEF (Protected
> > Execution Facility) which uses a small ultravisor to allow guests to
> > run in a way that
On Tue, Jan 12, 2021 at 11:59:59AM +0100, Greg Kurz wrote:
> On Tue, 12 Jan 2021 15:45:00 +1100
> David Gibson wrote:
>
> > Currently the "memory-encryption" property is only looked at once we
> > get to kvm_init(). Although protection of guest memory from the
> > hypervisor isn't something
On Tue, Jan 12, 2021 at 12:27:50PM +0100, Greg Kurz wrote:
> On Tue, 12 Jan 2021 15:45:05 +1100
> David Gibson wrote:
>
> > Some upcoming POWER machines have a system called PEF (Protected
> > Execution Facility) which uses a small ultravisor to allow guests to
> > run in a way that they can't
** Description changed:
It seems like the qemu tcg code for x86-64 doesn't write the access and
- dirty flags of the page table entries atomically. Instead, they first
+ dirty bits of the page table entries atomically. Instead, they first
read the entry, see if they need to set the page table
On 1/13/21 12:35 AM, John Snow wrote:
> On 1/12/21 4:11 PM, Eduardo Habkost wrote:
>> [CCing John, Wainer]
>>
>> On Fri, Jan 08, 2021 at 05:51:41PM -0500, Daniele Buono wrote:
>>> I had a similar issue in the past with the acceptance tests.
>>> Some VMs send UTF-8 output in their console and the
On 1/12/21 4:11 PM, Eduardo Habkost wrote:
[CCing John, Wainer]
On Fri, Jan 08, 2021 at 05:51:41PM -0500, Daniele Buono wrote:
I had a similar issue in the past with the acceptance tests.
Some VMs send UTF-8 output in their console and the acceptance test
script would bail out if the locale
Yeah, it's a long standing API deficiency inside QEMU that we don't have
a way to do atomic modifications in things like page-table-walk code:
mostly you don't notice unless you go looking for it, but we really
ought to fix this. Thanks for the unit test.
** Changed in: qemu
Status: New
le/pmaydell/qemu-arm.git
> tags/pull-target-arm-20210112-1
>
> for you to fetch changes up to 1ff5a063d60c7737de11465516331b8ca8700865:
>
> ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 21:19:02 +)
>
> ---
Public bug reported:
It seems like the qemu tcg code for x86-64 doesn't write the access and
dirty flags of the page table entries atomically. Instead, they first
read the entry, see if they need to set the page table entry, and then
overwrite the entry. So if you have two threads running at the
On 1/12/21 11:28 PM, Eduardo Habkost wrote:
> On Tue, Jan 12, 2021 at 11:15:38PM +0100, Philippe Mathieu-Daudé wrote:
>> On 1/12/21 9:44 PM, Richard Henderson wrote:
>>> On 1/12/21 8:41 AM, Philippe Mathieu-Daudé wrote:
Some ISA use a dot in their opcodes. Allow the decodetree
script to
On Tue, Jan 12, 2021 at 7:03 AM Peter Maydell wrote:
>
> On Tue, 5 Jan 2021 at 02:25, Joelle van Dyne wrote:
> >
> > This introduces support for building for iOS hosts. When the correct Xcode
> > toolchain is used, iOS host will be detected automatically.
> >
> > * block: disable features not
I wanted to know what the minimal setup required was to replicate the
compilation instructions featured on https://www.qemu.org/download/#source
> wget https://download.qemu.org/qemu-5.2.0.tar.xz
> tar xvJf qemu-5.2.0.tar.xz
> cd qemu-5.2.0
> ./configure
> make
For fedora:latest, I found that
On Tue, Jan 12, 2021 at 11:19:49PM +0100, Philippe Mathieu-Daudé wrote:
> On 1/12/21 10:05 PM, Eduardo Habkost wrote:
[...]
> >> diff --git a/scripts/decodetree.py b/scripts/decodetree.py
> >> index 47aa9caf6d1..b7572589e64 100644
> >> --- a/scripts/decodetree.py
> >> +++ b/scripts/decodetree.py
>
On Tue, Jan 12, 2021 at 11:15:38PM +0100, Philippe Mathieu-Daudé wrote:
> On 1/12/21 9:44 PM, Richard Henderson wrote:
> > On 1/12/21 8:41 AM, Philippe Mathieu-Daudé wrote:
> >> Some ISA use a dot in their opcodes. Allow the decodetree
> >> script to process them. The dot is replaced by an
On Tue, 12 Jan 2021, Jiaxun Yang wrote:
在 2021/1/10 上午4:16, BALATON Zoltan 写道:
The base address of the SMBus io ports and its enabled status is set
by registers in the PCI config space but this was not correctly
emulated. Instead the SMBus registers were mapped on realize to the
base address
I think this was discussed before but the main issue right now is that
there's no packaging system (like homebrew) for iOS cross building on
Mac. Stefan suggested caching built libraries in an external location
to use with the CI. I think this can be done but would require some
thought to it. I am
On 1/12/21 10:05 PM, Eduardo Habkost wrote:
> On Tue, Jan 12, 2021 at 07:41:56PM +0100, Philippe Mathieu-Daudé wrote:
>> Some ISA use a dot in their opcodes. Allow the decodetree
>> script to process them. The dot is replaced by an underscore
>> in the generated code.
>
> Will something break if
On 1/12/21 9:44 PM, Richard Henderson wrote:
> On 1/12/21 8:41 AM, Philippe Mathieu-Daudé wrote:
>> Some ISA use a dot in their opcodes. Allow the decodetree
>> script to process them. The dot is replaced by an underscore
>> in the generated code.
>
> Given that you then have to remember to use
After decoupling the MAP_JIT and APRR patches, this should only be for
iOS support. I didn't change the title because I didn't know if
patchew would be smart enough to group it with the older patches.
-j
On Tue, Jan 12, 2021 at 3:01 AM Peter Maydell wrote:
>
> On Tue, 5 Jan 2021 at 02:23,
Convert the following opcodes to decodetree:
- MOD.G - mod 32-bit signed integers
- MODU.G - mod 32-bit unsigned integers
- DMOD.G - mod 64-bit signed integers
- DMODU.G - mod 64-bit unsigned integers
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/godson2.decode| 5 ++
On Tue, Jan 12, 2021 at 10:55 PM Philippe Mathieu-Daudé wrote:
>
> DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
> 'is_double' argument so it can generate DIV.G (divide 32-bit
> signed integers).
>
> With this commit we explicit the template used to generate
> opcode for 32/64-bit
DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
'is_double' argument so it can generate DIV.G (divide 32-bit
signed integers).
With this commit we explicit the template used to generate
opcode for 32/64-bit word variants. Next commits will be less
verbose by providing both variants
Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
(divide 64-bit unsigned integers) opcodes to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/godson2.decode| 2 ++
target/mips/loong-ext.decode | 2 ++
target/mips/loong_translate.c | 55
Convert the following opcodes to decodetree:
- MULT.G - multiply 32-bit signed integers
- MULTU.G - multiply 32-bit unsigned integers
- DMULT.G - multiply 64-bit signed integers
- DMULTU.G - multiply 64-bit unsigned integers
Now that all opcodes from the extension have been converted, we
can
Introduce decode_loongson() to decode all Loongson vendor
specific opcodes. Start converting a single opcode: DDIV.G
(divide 64-bit signed integers).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 1 +
target/mips/godson2.decode| 16 +++
There is no issue having multiple enum declarations with
the same value. As we are going to remove the OPC_MULT_G_2E
definition in few commits, restore the OPC_ADDUH_QB_DSP and
OPC_MUL_PH_DSP definitions and use them where they belong.
Signed-off-by: Philippe Mathieu-Daudé
---
1 - 100 of 481 matches
Mail list logo
