Am Fri, 15 Jan 2021 20:12:06 +
schrieb Peter Maydell :
> The next-cube.h file is missing the usual copyright-and-license
> header; add it (same as the next-cube.c one).
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/m68k/next-cube.h | 10 ++
> 1 file changed, 10 insertions(+)
Am Fri, 15 Jan 2021 20:11:58 +
schrieb Peter Maydell :
> Move the registers handled by the mmio_ops struct into the NeXTPC
> device. This allows us to also move the scr1 and scr2 data fields.
>
> Signed-off-by: Peter Maydell
> ---
> hw/m68k/next-cube.c | 80
>
Am Fri, 15 Jan 2021 20:11:56 +
schrieb Peter Maydell :
> The next_irq() function is global, but isn't actually used anywhere
> outside next-cube.c. Make it static.
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/m68k/next-cube.h | 2 --
> hw/m68k/next-cube.c | 2 +-
> 2 files
From: Bin Meng
Now that we have switched to generate the RISC-V CSR XML dynamically,
remove the built-in hardcoded XML files.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
.../targets/riscv32-linux-user.mak| 2 +-
From: Bin Meng
At present QEMU RISC-V uses a hardcoded XML to report the feature
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
approach being used currently:
- The XML does not specify the "regnum" field of a CSR entry, hence
consecutive numbers are used by the remote GDB
From: Bin Meng
At present QEMU RISC-V uses a hardcoded XML to report the feature
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
approach being used currently:
- The XML does not specify the "regnum" field of a CSR entry, hence
consecutive numbers are used by the remote GDB
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
x86_64
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
QEMU
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
OS/2 Warp
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
Windows NT
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
OS/2 Warp
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
netdev
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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Title:
qemu for
On Sat, Jan 16, 2021 at 6:08 AM Alistair Francis wrote:
>
> On Fri, Jan 15, 2021 at 1:59 PM Alistair Francis wrote:
> >
> > On Mon, Jan 11, 2021 at 8:55 PM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > At present QEMU RISC-V uses a hardcoded XML to report the feature
> > >
Patchew URL:
https://patchew.org/QEMU/20210115224645.1196742-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210115224645.1196742-1-richard.hender...@linaro.org
Subject: [PATCH v3
Can you add a Tested-by: tag to the patch?
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https://bugs.launchpad.net/bugs/1906193
Title:
riscv32 user mode emulation: fork return values broken
Status in QEMU:
Confirmed
Bug
On Fri, Jan 15, 2021 at 2:17 PM Peter Maydell wrote:
>
> On Fri, 15 Jan 2021 at 21:43, Alistair Francis wrote:
> >
> > On Fri, Jan 15, 2021 at 6:09 AM Bin Meng wrote:
> > >
> > > On Fri, Jan 15, 2021 at 9:55 PM Peter Maydell
> > > wrote
> > > > printf is definitely the wrong thing... you need
On 9/21/20 9:42 PM, Douglas Crosher wrote:
>
> The cpu_exec_step_atomic() function is called with the cpu->running
> clear and proceeds to run target code without setting this flag. If
> this target code generates an exception then handle_cpu_signal() will
> unnecessarily abort.
>
> For example
On Fri, 15 Jan 2021 15:00:27 PST (-0800), Alistair Francis wrote:
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.
Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity
On Wed, Jan 13, 2021 at 6:32 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
This patch results in a QEMU seg fault when starting userspace on RISC-V 32-bit.
This is the full backtrace:
```
#0 0x55a67c4d in ts_are_copies (ts2=0x7fffa8008008,
ts1=0x7fffa8001e40) at
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.
Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis
---
On Sat, Dec 19, 2020 at 10:11 AM Alistair Francis
wrote:
>
> When mapping the host waitid status to the target status we previously
> just used decoding information in the status value. This doesn't follow
> what the waitid documentation describes, which instead suggests using
> the si_code value
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index abc0affd00..5e613a747a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -208,6 +208,22 @@ static void
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_signal.h | 1 +
linux-user/aarch64/cpu_loop.c | 34 +-
target/arm/mte_helper.c| 10 +
3 files changed, 35 insertions(+), 10 deletions(-)
diff --git
Move everything related to syndromes to a new file,
which can be shared with linux-user.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 245 +---
target/arm/syndrome.h | 273 +
2 files changed, 274
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/mte.h | 53 +++
tests/tcg/aarch64/mte-1.c | 25 +++
tests/tcg/aarch64/mte-2.c | 42
tests/tcg/aarch64/mte-3.c | 47 +++
Use the now-saved PAGE_ANON and PAGE_MTE bits,
and the per-page saved data.
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index
These prctl fields are required for the function of MTE.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_syscall.h | 9 ++
linux-user/syscall.c| 44 +
2 files changed, 53 insertions(+)
diff --git
The AArch64 Linux ABI has always enabled TBI, but has historically
required that pointer tags be removed before a syscall. This has
changed in the lead-up to ARMv8.5-MTE, in a way that affects the
ABI generically and not specifically to MTE.
This patch allows the target to indicate that (1)
This is the prctl bit that controls whether syscalls accept tagged
addresses. See Documentation/arm64/tagged-address-abi.rst in the
linux kernel.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_syscall.h | 4
target/arm/cpu-param.h | 3 +++
target/arm/cpu.h
These constants are only ever used with access_ok, and friends.
Rather than translating them to PAGE_* bits, let them equal
the PAGE_* bits to begin.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/qemu.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
A proper syndrome is required to fill in the proper si_code.
Use page_get_flags to determine permission vs translation for user-only.
Signed-off-by: Richard Henderson
---
v3: Use syndrome.h, arm_deliver_fault.
---
linux-user/aarch64/cpu_loop.c | 24 +---
This is the only use of guest_addr_valid that does not begin
with a guest address, but a host address being transformed to
a guest address.
We will shortly adjust guest_addr_valid to handle guest memory
tags, and the host address should not be subjected to that.
Move h2g_valid adjacent to the
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_signal.h | 2 ++
linux-user/aarch64/cpu_loop.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/linux-user/aarch64/target_signal.h
b/linux-user/aarch64/target_signal.h
index ddd73169f0..777fb667fe 100644
---
This is more descriptive than 'unsigned long'.
No functional change, since these match on all linux+bsd hosts.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
These constants are only ever used with access_ok, and friends.
Rather than translating them to PAGE_* bits, let them equal
the PAGE_* bits to begin.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
bsd-user/qemu.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
This is more descriptive than 'unsigned long'.
No functional change, since these match on all linux+bsd hosts.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 2 +-
bsd-user/main.c| 2 +-
linux-user/main.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff
Return bool not int; pass abi_ulong not 'unsigned long'.
All callers use abi_ulong already, so the change in type
has no effect.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/cpu_ldst.h
Remember the PROT_MTE bit as PAGE_MTE/PAGE_TARGET_2.
Otherwise this does not yet have effect.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Do not overlap PAGE_TARGET_2 with PAGE_RESERVED.
---
include/exec/cpu-all.h| 1 +
linux-user/syscall_defs.h | 1 +
Verify that addr + size - 1 does not wrap around.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/qemu.h | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 534753ca12..a0f670832e 100644
Record whether the backing page is anonymous, or if it has file
backing. This will allow us to get close to the Linux AArch64
ABI for MTE, which allows tag memory only on ram-backed VMAs.
The real ABI allows tag memory on files, when those files are
on ram-backed filesystems, such as tmpfs. We
We must always use GUEST_ADDR_MAX, because even 32-bit hosts can
use -R to restrict the memory address of the guest.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/include/exec/cpu_ldst.h
The kernel abi was finally merged into 5.10.
Changes for v3:
* Split out type changes to separate patches.
* Add doc comments; tweak alloc so that the !PAGE_VALID case is clear.
* Do not overlap PAGE_TARGET_2 with PAGE_RESERVED.
* Use syndrome.h, arm_deliver_fault.
r~
v1:
This data can be allocated by page_alloc_target_data() and
released by page_set_flags(start, end, prot | PAGE_RESET).
This data will be used to hold tag memory for AArch64 MTE.
Signed-off-by: Richard Henderson
---
v3: Add doc comments; tweak alloc so that the !PAGE_VALID case is clear.
---
On 210115 1609, Philippe Mathieu-Daudé wrote:
> This test fails when QEMU is built without the megasas device,
> restrict it to its availability.
Should we just make a separate directory for fuzzer tests and have a
separate source file for each reproducer (or for each device)? That way,
we avoid
On 1/15/21 12:13 PM, Alistair Francis wrote:
> On Fri, Jan 15, 2021 at 1:09 PM Richard Henderson
> wrote:
>>
>> Signed-off-by: Richard Henderson
>> ---
>> tcg/riscv/tcg-target-con-str.h | 21 ++
>> tcg/riscv/tcg-target.h | 1 +
>> tcg/riscv/tcg-target.c.inc | 50
On Tue, Jan 12, 2021 at 4:11 AM Vitaly Wool wrote:
>
> Hi Bin,
>
> On Tue, Jan 5, 2021 at 7:27 AM Bin Meng wrote:
> >
> > +Alistair Francis
> >
> > On Sat, Dec 19, 2020 at 8:24 AM Vitaly Wool
> > wrote:
> > >
> > > Add command line parameter to microchip_pfsoc machine to be able
> > > to
On 15/01/2021 16.09, Philippe Mathieu-Daudé wrote:
Tests in fuzz-test's main() already check for the supported
architecture before adding tests, therefore this test is not
specific to the X86 target. Move it to the generic set.
As long as it does not run any test on non-x86, it does not make
On Sun, Jan 10, 2021 at 10:57 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/target/riscv/cpu.c
On Fri, 15 Jan 2021 at 21:43, Alistair Francis wrote:
>
> On Fri, Jan 15, 2021 at 6:09 AM Bin Meng wrote:
> >
> > On Fri, Jan 15, 2021 at 9:55 PM Peter Maydell
> > wrote
> > > printf is definitely the wrong thing... you need to either report
> > > the error back to the guest if the interface
On Fri, Jan 15, 2021 at 1:09 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/riscv/tcg-target-con-str.h | 21 ++
> tcg/riscv/tcg-target.h | 1 +
> tcg/riscv/tcg-target.c.inc | 50 --
> 3 files changed, 33
On Sun, Jan 10, 2021 at 10:51 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>
On Sun, Jan 10, 2021 at 11:00 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 19398977d3..234401c3c6 100644
>
On Fri, Jan 15, 2021 at 1:59 PM Alistair Francis wrote:
>
> On Mon, Jan 11, 2021 at 8:55 PM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > At present QEMU RISC-V uses a hardcoded XML to report the feature
> > "org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
> > approach being
Ok, enter and leave will officially get to be TCG code.
To be honest initially we thought that helper code would be preferable
to TCG one. Apparently we were wrong. :-)
Thanks for your quick feedback.
On 1/15/21 9:53 PM, Richard Henderson wrote:
> On 1/15/21 11:48 AM, Cupertino Miranda wrote:
On Mon, Jan 11, 2021 at 8:55 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Now that we have switched to generate the RISC-V CSR XML dynamically,
> remove the built-in hardcoded XML files.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
>
On Mon, Jan 11, 2021 at 8:55 PM Bin Meng wrote:
>
> From: Bin Meng
>
> At present QEMU RISC-V uses a hardcoded XML to report the feature
> "org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
> approach being used currently:
>
> - The XML does not specify the "regnum" field of a CSR
On Fri, Jan 15, 2021 at 3:50 AM Peter Maydell wrote:
>
> Ping! This patch was trying to fix a Coverity issue (CID 1435959,
> 1435960, 1435961) -- is anybody planning to review it?
>
> (I'm not entirely sure 'guest error' is the right warning category,
> but I don't know the specifics of this
On 1/15/21 11:48 AM, Cupertino Miranda wrote:
>> In the case of enter or leave, this is one load/store plus one addition,
>> followed by a branch. All of which is encoded as fields in the instruction.
>> Extremely simple.
>
> So your recommendation is leave the conditional exception triggering
On Fri, Jan 15, 2021 at 5:35 AM Alexander Richardson
wrote:
>
> On Tue, 12 Jan 2021 at 05:02, Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > In preparation to generate the CSR register list for GDB stub
> > dynamically, let's add the CSR name in the CSR function table.
> >
> > Signed-off-by:
On Mon, Jan 11, 2021 at 9:05 PM Bin Meng wrote:
>
> From: Bin Meng
>
> In preparation to generate the CSR register list for GDB stub
> dynamically, let's add the CSR name in the CSR function table.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
>
On Mon, Jan 11, 2021 at 8:53 PM Bin Meng wrote:
>
> From: Bin Meng
>
> In preparation to generate the CSR register list for GDB stub
> dynamically, change csr_ops[] to non-static so that it can be
> referenced externally.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
On 1/15/21 11:28 AM, Shahab Vahedi wrote:
>>> +cpu_stl_data(env, tmp_sp, CPU_FP(env));
>>> +}
>>
>> And what if these stores raise an exception? I doubt you're going to get an
>> exception at the correct pc.
>
> I've added a few bad-weather test cases [1] and they work as expected.
On 1/15/21 8:31 PM, Richard Henderson wrote:
> On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>>> Similarly. I think that both of these could be implemented entirely in
>>> translate, which is what
>>>
+bool restore_fp= u7 & 0x10; /* u[4] indicates if fp must be saved
*/
On Fri, Jan 15, 2021 at 6:09 AM Bin Meng wrote:
>
> On Fri, Jan 15, 2021 at 9:55 PM Peter Maydell
> wrote:
> >
> > On Fri, 15 Jan 2021 at 13:33, Bin Meng wrote:
> > >
> > > On Fri, Jan 15, 2021 at 7:50 PM Peter Maydell
> > > wrote:
> > > >
> > > > Ping! This patch was trying to fix a
On 1/15/21 2:22 PM, Greg Kurz wrote:
On Thu, 14 Jan 2021 15:06:28 -0300
Daniel Henrique Barboza wrote:
The only restriction we have when unplugging CPUs is to forbid unplug of
the boot cpu core. spapr_core_unplug_possible() does not contemplate the
I can't remember why this restriction
On 1/15/21 2:22 PM, Greg Kurz wrote:
On Thu, 14 Jan 2021 15:06:28 -0300
Daniel Henrique Barboza wrote:
The only restriction we have when unplugging CPUs is to forbid unplug of
the boot cpu core. spapr_core_unplug_possible() does not contemplate the
I can't remember why this restriction
On Wed, Nov 4, 2020 at 1:29 AM Green Wan wrote:
>
> Fix code coverage issues by checking return value and handling fail case
> of blk_pread() and blk_pwrite(). Return default value 0xff if read fails.
>
> Signed-off-by: Green Wan
Reviewed-by: Alistair Francis
Alistair
> ---
>
Hi Richard,
On 12/1/20 10:35 PM, Richard Henderson wrote:
> On 11/11/20 10:17 AM, cupertinomira...@gmail.com wrote:
>> From: Cupertino Miranda
>> +void helper_enter(CPUARCState *env, uint32_t u6)
>> +{
>> +/* nothing to do? then bye-bye! */
>> +if (!u6) {
>> +return;
>> +}
>>
Thanks for your quick reply.
On 1/15/21 8:17 PM, Richard Henderson wrote:
> On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>>> On 11/11/20 10:17 AM, cupertinomira...@gmail.com wrote:
+/*
+ * The macro to add boiler plate code for conditional execution.
+ * It will add tcg_gen codes
Patchew URL:
https://patchew.org/QEMU/20210115210456.1053477-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210115210456.1053477-1-richard.hender...@linaro.org
Subject: [PATCH v2
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-set.h | 30
tcg/riscv/tcg-target.h | 1 +
tcg/riscv/tcg-target.c.inc | 83 ++
3 files changed, 54 insertions(+), 60 deletions(-)
create mode
All backends have now been converted to tcg-target-con-set.h,
so we can remove the fallback code.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/i386/tcg-target.h| 1 -
tcg/mips/tcg-target.h| 1
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-con-set.h | 42 +++
tcg/ppc/tcg-target.h | 1 +
tcg/ppc/tcg-target.c.inc | 136 +++
3 files changed, 99 insertions(+), 80 deletions(-)
create mode 100644 tcg/ppc/tcg-target-con-set.h
This requires finishing the conversion to tcg_target_op_def.
Remove quite a lot of ifdefs, since we can reference opcodes
even if they are not implemented.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target-con-set.h | 25 +++
tcg/tci/tcg-target.h | 2 +
tcg/tci/tcg-target.c.inc
This exports the constraint sets from tcg_target_op_def to
a place we will be able to manipulate more in future.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target-con-set.h | 54 ++
tcg/i386/tcg-target.h | 1 +
tcg/tcg.c | 122 +
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-con-set.h | 36 +
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 96 +++
3 files changed, 66 insertions(+), 67 deletions(-)
create mode 100644
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target-con-set.h | 32 +++
tcg/sparc/tcg-target.h | 1 +
tcg/sparc/tcg-target.c.inc | 75 +++---
3 files changed, 56 insertions(+), 52 deletions(-)
create mode 100644
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-set.h | 36 +
tcg/aarch64/tcg-target.h | 1 +
tcg/aarch64/tcg-target.c.inc | 86 +++-
3 files changed, 65 insertions(+), 58 deletions(-)
create mode 100644
All backends have now been converted to tcg-target-con-str.h,
so we can remove the fallback code.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/i386/tcg-target.h| 1 -
tcg/mips/tcg-target.h| 1
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target-con-set.h | 29
tcg/s390/tcg-target.h | 1 +
tcg/s390/tcg-target.c.inc | 121 ++
3 files changed, 81 insertions(+), 70 deletions(-)
create mode 100644 tcg/s390/tcg-target-con-set.h
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h | 35 ++
tcg/arm/tcg-target.h | 1 +
tcg/arm/tcg-target.c.inc | 94
3 files changed, 68 insertions(+), 62 deletions(-)
create mode 100644 tcg/arm/tcg-target-con-set.h
Rather than check the type when filling in the constraint,
check it when matching the constant. This removes the only
use of the type argument to target_parse_constraint.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 28 +---
1 file changed, 17
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target-con-str.h | 22 +
tcg/sparc/tcg-target.h | 5 +---
tcg/sparc/tcg-target.c.inc | 45 +-
3 files changed, 29 insertions(+), 43 deletions(-)
create mode 100644
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target-con-str.h | 23
tcg/s390/tcg-target.h | 1 +
tcg/s390/tcg-target.c.inc | 40 ---
3 files changed, 24 insertions(+), 40 deletions(-)
create mode 100644
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-con-str.h | 24
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 72 ---
3 files changed, 41 insertions(+), 56 deletions(-)
create mode 100644 tcg/mips/tcg-target-con-str.h
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-str.h | 22
tcg/arm/tcg-target.h | 1 +
tcg/arm/tcg-target.c.inc | 69 +++-
3 files changed, 36 insertions(+), 56 deletions(-)
create mode 100644 tcg/arm/tcg-target-con-str.h
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-str.h | 21 ++
tcg/riscv/tcg-target.h | 1 +
tcg/riscv/tcg-target.c.inc | 50 --
3 files changed, 33 insertions(+), 39 deletions(-)
create mode 100644
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-con-str.h | 30 +++
tcg/ppc/tcg-target.h | 1 +
tcg/ppc/tcg-target.c.inc | 73
3 files changed, 46 insertions(+), 58 deletions(-)
create mode 100644 tcg/ppc/tcg-target-con-str.h
These are identical to the 'r' constraint.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 15981265db..9c45f5f88f 100644
---
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-str.h | 24 +++
tcg/aarch64/tcg-target.h | 1 +
tcg/aarch64/tcg-target.c.inc | 51 +---
3 files changed, 33 insertions(+), 43 deletions(-)
create mode 100644
This eliminates the target-specific function target_parse_constraint
and folds it into the single caller, process_op_defs. Since this is
done directly into the switch statement, duplicates are compilation
errors rather than silently ignored at runtime.
Signed-off-by: Richard Henderson
---
This pulls out constraints to a couple of headers, which
reduces the boilerplate just a little.
I have a longer term goal, which this aids, in which I
move some of the startup-time debug-only validation into
build/compile-time validation. But not yet.
Changes for v2:
* Rename "conset" ->
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target-con-str.h | 11 +++
tcg/tci/tcg-target.h | 2 ++
tcg/tci/tcg-target.c.inc | 14 --
3 files changed, 13 insertions(+), 14 deletions(-)
create mode 100644 tcg/tci/tcg-target-con-str.h
diff --git
Documented under the "Acceptance tests using the Avocado Framework"
section in testing.rst how environment variables are used to skip tests.
Signed-off-by: Wainer dos Santos Moschetta
---
v2:
- Made the changes Thomas pointed out.
docs/devel/testing.rst | 62
This patch fixes the following memory leak detected by asan:
Indirect leak of 560320 byte(s) in 136 object(s) allocated from:
#0 0x556b3b3f9b57 in calloc
(/home/stefanb/tmp/qemu-tip/build/tests/qtest/tpm-crb-swtpm-test+0x23fb57)
#1 0x152b0e96b9b0 in g_malloc0
Hi,
On 1/14/21 10:02 AM, Daniel P. Berrangé wrote:
Signed-off-by: Daniel P. Berrangé
---
tests/docker/dockerfiles/refresh | 53
1 file changed, 53 insertions(+)
create mode 100755 tests/docker/dockerfiles/refresh
diff --git
On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>> Similarly. I think that both of these could be implemented entirely in
>> translate, which is what
>>
>>> +bool restore_fp= u7 & 0x10; /* u[4] indicates if fp must be saved
>>> */
>>> +bool restore_blink = u7 & 0x20; /* u[5] indicates
On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>> On 11/11/20 10:17 AM, cupertinomira...@gmail.com wrote:
>>> +/*
>>> + * The macro to add boiler plate code for conditional execution.
>>> + * It will add tcg_gen codes only if there is a condition to
>>> + * be checked (ctx->insn.cc != 0). This macro
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