[Bug 1921664] Re: Recent update broke qemu-system-riscv64

Also I've rebuilt the most recent master c1e90def01 about ~55 commits newer than 6.0-rc2. As in the experiments of Tommy I was unable to reproduce it there. But with the data from the tests before it is very likely that this is more likely an accident by having a slightly different timing than a f

Live migration using a specified networking adapter

Hello experts, I have a network topology like this diagram. When start live migration moving a VM from Host A to B, the migration process uses either 10GbE (10.0.0.1) or 1 GbE (10.0.0.2), but the user cannot specify the source NIC by current migrate command. To solve the problem, my rough id

Re: [PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions

On 4/13/21 4:34 PM, Alistair Francis wrote: This patch removes the insn16-32.decode and insn16-64.decode decode files and consolidates the instructions into the general RISC-V insn16.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. T

Re: [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions

On 4/13/21 4:34 PM, Alistair Francis wrote: -#ifndef CONFIG_USER_ONLY -# ifdef TARGET_RISCV32 -# define is_32bit(ctx) true -# else +#ifdef TARGET_RISCV32 +# define is_32bit(ctx) true +#else static inline bool is_32bit(DisasContext *ctx) { -return !(ctx->misa & RV64); +return (ctx->

Re: [PATCH v1 3/3] target/ppc: Add POWER10 exception model

Excerpts from Fabiano Rosas's message of April 14, 2021 1:53 am: > Nicholas Piggin writes: > >> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], >> and it removes support for the LPCR[AIL]=0b10 mode. >> >> Signed-off-by: Nicholas Piggin >> --- [snip] Thanks for the suggest

[RFC PATCH 2/2] target/ppc: Add POWER10 exception model

POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=0b10 mode. Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c| 7 +- target/ppc/cpu-qom.h| 2 ++ target/ppc/cpu.h| 5 ++-- target/ppc

Re: [PATCH v1 1/3] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour

Excerpts from Fabiano Rosas's message of April 13, 2021 11:48 pm: > Nicholas Piggin writes: > >> ISA v3.0 radix guest execution has a quirk in AIL behaviour such that >> the LPCR[AIL] value can apply to hypervisor interrupts. >> >> This affects machines that emulate HV=1 mode (i.e., powernv9). >>

[RFC PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery

The AIL logic is becoming unmanageable spread all over powerpc_excp(), and it is slated to get even worse with POWER10 support. Move it all to a new helper function. Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c| 3 +- target/ppc/cpu.h| 8 -- target/ppc

[RFC PATCH 0/2] ppc: rework AIL logic, add POWER10 exception model

This applies on top of patches 1,2 from the previous series (i.e., these two patches replace patch 3). Function should be the same, but this way seems much cleaner. It does include a "cleanup" patch before the POWER10 fix, but arguably this is a better way to go even as a bug fix (backport, etc).

Re: [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro

On 4/13/21 4:34 PM, Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 --- target/riscv/cpu_helper.c | 24 ++-- target/riscv/csr.c| 20 target/riscv/monitor.c| 22 +- 4

Re: [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro

On 4/13/21 4:33 PM, Alistair Francis wrote: +#ifndef CONFIG_USER_ONLY +# ifdef TARGET_RISCV32 +# define is_32bit(ctx) true +# else +static inline bool is_32bit(DisasContext *ctx) +{ +return !(ctx->misa & RV64); +} +# endif +#endif It's going to be soon enough when this is used by user-onl

[Bug 1923693] [NEW] Lack of architecture in gdbstub makes debugging confusing

Public bug reported: I spent some quality time debugging GEF and came to a conclusion here: https://github.com/hugsy/gef/issues/598#issuecomment-819174169 tldr; * gdb_arch_name was undefined on riscv * this bug was fixed recently via https://github.com/qemu/qemu/commit/edf647864bdab84ed4b1a4f47

[Bug 1923692] [NEW] qemu 5.2.0: Add reconnect option support for netdev socket

Public bug reported: Most of qemu socket accepting options (such as chardev) accept among other things a "reconnect" option. netdev socket however returns: Invalid parameter 'reconnect' It would make sense that available options for socket links be at least partially normalized (also see issue h

Re: [PATCH v1 3/3] target/ppc: Add POWER10 exception model

Excerpts from Cédric Le Goater's message of April 14, 2021 3:09 am: > On 4/13/21 5:53 PM, Fabiano Rosas wrote: >> Nicholas Piggin writes: >> >>> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], >>> and it removes support for the LPCR[AIL]=0b10 mode. >>> >>> Signed-off-by: Nic

Re: [RFC v9 15/29] vfio: Set up nested stage mappings

On 2021/4/13 20:57, Auger Eric wrote: Hi Kunkun, On 4/13/21 2:10 PM, Kunkun Jiang wrote: Hi Eric, On 2021/4/11 20:08, Eric Auger wrote: In nested mode, legacy vfio_iommu_map_notify cannot be used as there is no "caching" mode and we do not trap on map. On Intel, vfio_iommu_map_notify was use

[Bug 1923689] [NEW] sig-abort / coredump observed from aio_ctx_finalize

Public bug reported: Observing occasional sig-abort based on v5.2.0 (tag) of QEMU. The VMM is configured for Kata use case, launching with a nvdimm/pmem based rootfs, and a set of workloads which are heavily utilizing virtio-fs. Sample qemu-cmdline: /usr/bin/qemu-kata-system-x86_64 -name sandbox-

Re: [PATCH] decodetree: Allow custom var width load functions

On 4/13/21 11:16 AM, Luis Pires wrote: This is useful in situations where you want decodetree to handle variable width instructions but you want to provide custom code to load the instructions. Suppressing the generation of the load function is necessary to avoid compilation errors due to the loa

Re: [PATCH v2] target/s390x: Fix translation exception on illegal instruction

On 4/13/21 9:52 AM, Ilya Leoshkevich wrote: Hitting an uretprobe in a s390x TCG guest causes a SIGSEGV. What happens is: * uretprobe maps a userspace page containing an invalid instruction. * uretprobe replaces the target function's return address with the address of that page. * When tb_gen_

[PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro

Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 74636b9db7..ba8fb2cda3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate

[PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 10 -- target/riscv/csr.c | 12 ++-- target/riscv/translate.c | 20 ++-- 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8c

[PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions

This patch removes the insn16-32.decode and insn16-64.decode decode files and consolidates the instructions into the general RISC-V insn16.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure w

[PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 --- target/riscv/cpu_helper.c | 24 ++-- target/riscv/csr.c| 20 target/riscv/monitor.c| 22 +- 4 files changed, 51 insertions(+), 26 deletions(-)

[PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions

This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit

[PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro

Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 6 -- target/riscv/cpu.c | 6 +- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..ef838f5fbf 100644 --- a/target/riscv/cpu.h +++

[PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro

Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6a816ce9c2..9f6fbe3dc5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@

[PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro

Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 11 --- target/riscv/cpu_helper.c | 24 +++- 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 969dd05

[PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro

Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 6 -- target/riscv/csr.c | 9 - 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..969dd05eae 100644 --- a

[PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on

This is another step towards running 32-bit CPU code on the 64-bit softmmu builds for RISC-V. I have tested this and am able to run some 32-bit code, but eventually hit some issue. This series doesn't allow users to use 32-bit CPUs with 64-bit softmmu builds as it doesn't work yet. This series in

Issues with modifying pc in a sigaction handler

In a toy project I was doing (https://github.com/easyaspi314/ThumbGolf), I found that qemu will incorrectly handle modifying pc in a handler. Specifically, on platforms with instruction alignment requirements (most notably ARM), if you set the pc to an odd address, QEMU will start reading unaligne

Re: [PATCH 5/5] target/ppc: Implement paddi and replace addi insns

Hi Luis, On 4/13/21 11:11 PM, Luis Pires wrote: > This implements the Power ISA 3.1 prefixed (64-bit) paddi > instruction, while also replacing the legacy addi implementation. > Both using the decode tree. > > Signed-off-by: Luis Pires > Signed-off-by: Matheus Ferst > --- > target/ppc/ppc.deco

[PATCHv2 1/1] Support monitor chardev hotswap with QMP

For some scenarios, it needs to hot-add a monitor device. But QEMU doesn't support hotplug yet. It also works by adding a monitor with null backend by default and then change its backend to socket by QMP command "chardev-change". So this patch is to support monitor chardev hotswap with QMP. Signe

RE: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

Bruno Piazera Larsen writes: >> I'm actually not sure if we'll want translate_init.c for !tcg builds. >> It's *primarily* for TCG, but we still need at least some of the cpu >> state structure for KVM, and some of that is initialized in >> translate_init. >> >> I think it will probably make more

[Bug 1923497] Re: bios_linker_loader_add_checksum: Assertion `start_offset < file->blob->len' failed

Hmmm. Well, I don't know what the command line was. I use Virtual Machine Manager (virt-manager.org) for my interface to the VM and it does the startup. The error shows up when I start the VM. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed

[PATCH] qemu-iotest: Test NBD hole reporting for qcow2

In commit commit 0da9856851dcca09222a1467e16ddd05dc66e460 nbd: server: Report holes for raw images we changed the way holes are reported for raw images, but also how known-zero portions of qcow2 files are reported. This was not covered by iotests, and revealed recently by libnbd tests[1]. Ad

Re: [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document

Il mar 13 apr 2021, 18:25 Daniel P. Berrangé ha scritto: > Since this was derived from the Fedora CoC, you might be interested to > know that Fedora is currently revisiting its CoC: > > > https://communityblog.fedoraproject.org/policy-proposal-new-code-of-conduct/ > > The first comment on that po

[PATCH 3/5] decodetree: Allow custom var width load functions

This is useful in situations where you want decodetree to handle variable width instructions but you want to provide custom code to load the instructions. Suppressing the generation of the load function is necessary to avoid compilation errors due to the load function being unused. This will be us

[PATCH 5/5] target/ppc: Implement paddi and replace addi insns

This implements the Power ISA 3.1 prefixed (64-bit) paddi instruction, while also replacing the legacy addi implementation. Both using the decode tree. Signed-off-by: Luis Pires Signed-off-by: Matheus Ferst --- target/ppc/ppc.decode | 8 +++ target/ppc/translate.c

[PATCH 0/5] Base for adding PowerPC 64-bit instructions

This series provides the basic infrastructure for adding the new 32/64-bit instructions in Power ISA 3.1 to target/ppc. It starts by changing decodetree.py to support 64-bit instructions as well as custom variable-width instruction load functions. Then it changes the target/ppc code to allow 32-

[PATCH 4/5] target/ppc: Base changes to allow 32/64-bit insns

These changes add the basic support for 32- and 64-bit instruction decoding using decodetree. Apart from the instruction decoding itself, it also takes care of some pre-requisite changes, such as removing hard-coded instruction sizes throughout the code and raising an alignment exception should a

[PATCH 2/5] decodetree: Fix empty input files for varinsnwidth

Decodetree would throw an error when the input file was empty and --varinsnwidth was specified. Signed-off-by: Luis Pires --- scripts/decodetree.py | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 4e18f52a65..935b

[PATCH 1/5] decodetree: Add support for 64-bit instructions

Allow '64' to be specified for the instruction width command line params and use the appropriate insn/field data types, mask, extract and deposit functions in that case. This will be used to implement the new 64-bit Power ISA 3.1 instructions. Signed-off-by: Luis Pires --- docs/devel/decodetree

Re: [PULL 0/1] Block patch for 6.0-rc3

On Tue, 13 Apr 2021 at 14:39, Max Reitz wrote: > > The following changes since commit dce628a97fde2594f99d738883a157f05aa0a14f: > > Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210412' > into staging (2021-04-13 13:05:07 +0100) > > are available in the Git repository at: >

Re: [PATCH] linux-user/elfload: fix filling psinfo->pr_psargs

Patchew URL: https://patchew.org/QEMU/20210413205814.22821-1-...@linux.ibm.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210413205814.22821-1-...@linux.ibm.com Subject: [PATCH] linux-user/elfload: fix filling ps

[PATCH] linux-user/elfload: fix filling psinfo->pr_psargs

The current code dumps the memory between arg_start and arg_end, which contains the argv pointers. This results in the Core was generated by `` message when opening the core file in GDB. This is because the code is supposed to dump the actual arg strings. Fix by using arg_strings and env_stri

[PATCH] linux-user/elfload: add s390x core dumping support

Provide the following definitions required by the common code: * ELF_NREG: with the value of sizeof(s390_regs) / sizeof(long). * target_elf_gregset_t: define it like all the other arches do. * elf_core_copy_regs(): similar to kernel's s390_regs_get(). * USE_ELF_CORE_DUMP. * ELF_EXEC_PAGESIZE. Sig

Re: [RFC v12 03/65] arm: tcg: only build under CONFIG_TCG

On 3/26/21 8:35 PM, Claudio Fontana wrote: > Signed-off-by: Claudio Fontana > Reviewed-by: Richard Henderson > Reviewed-by: Alex Bennée > --- > target/arm/tcg/meson.build | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/

Re: [PULL v2 0/3] osdep.h + QOM changes for QEMU 6.0-rc3

On Tue, 13 Apr 2021 at 17:18, Paolo Bonzini wrote: > > The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620: > > Merge remote-tracking branch > 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12 > 12:12:09 +0100) > > are available in the Git reposi

[Bug 1923663] [NEW] Can't(?) disable default floppy drive any more in qemu 6.0

Public bug reported: There's a documented change in qemu 6.0: https://qemu-project.gitlab.io/qemu/system/removed-features.html#floppy- controllers-drive-properties-removed-in-6-0 where you can't configure floppy controller device properties with -global any more. However, there's a thing you cou

Re: [PATCH for-6.0] x86: acpi: use offset instead of pointer when using build_header()

On Tue, Apr 13, 2021 at 05:21:10PM +0200, Igor Mammedov wrote: > On Tue, 13 Apr 2021 09:53:17 -0400 > "Michael S. Tsirkin" wrote: > > > On Tue, Apr 13, 2021 at 03:18:16PM +0200, Igor Mammedov wrote: > > > On Tue, 13 Apr 2021 08:14:56 -0400 > > > "Michael S. Tsirkin" wrote: > > > > > > > On Tu

Re: [PATCH RFC 4/7] message: add QMP Message type

On Tue, Apr 13, 2021 at 11:55:50AM -0400, John Snow wrote: > This is an abstraction that represents a single message either sent to > or received from the server. It is used to subclass the > AsyncProtocol(Generic[T]) type. > > It was written such that it can be populated by either raw data or by

Re: [PULL 0/3] target-arm queue

to staging (2021-04-12 > 12:12:09 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20210413 > > for you to fetch changes up to 2d18b4ca023ca1a3aee18064251d6e6e1084f3eb: > > sphinx: qa

Re: [PATCH RFC 3/7] protocol: generic async message-based protocol loop

On Tue, Apr 13, 2021 at 11:55:49AM -0400, John Snow wrote: > This module provides the protocol-agnostic framework upon which QMP will > be built. I also have (not included in this series) a qtest > implementation that uses this same framework, which is why it is split > into two portions like this.

Re: [RFC PATCH-for-6.1 0/9] hw/clock: Strengthen machine (non-qdev) clock propagation

On Mon, Apr 12, 2021 at 11:44:29AM +0100, Peter Maydell wrote: > On Mon, 12 Apr 2021 at 11:31, Philippe Mathieu-Daudé wrote: > > TIL MachineClass::reset(). > > > > - hw/hppa/machine.c > > - hw/i386/pc.c > > > > Used to reset CPUs manually because CPUs aren't sysbus-reset. > > pc_machine_reset()

RE: [PATCH] decodetree: Allow empty input files for var width

Please ignore this. I'll resend as part of a patch series. Luis Pires Instituto de Pesquisas ELDORADO Departamento de Computação Embarcada Aviso Legal - Disclaimer -Original Message- From: Luis Pires Sent: terça-feira, 13 de abril de 2021 15:10 To: qemu-devel@nongnu.org Cc: richard.hen

RE: [PATCH] decodetree: Allow custom var width load functions

Please ignore this. I'll resend as part of a patch series. -Original Message- From: Luis Pires Sent: terça-feira, 13 de abril de 2021 15:16 To: qemu-devel@nongnu.org Cc: richard.hender...@linaro.org; qemu-...@nongnu.org; Luis Fernando Fujita Pires Subject: [PATCH] decodetree: Allow cus

Re: [PATCH] target/i386: Add CPU model versions supporting 'xsaves'

On Mon, Apr 12, 2021 at 09:39:52AM +0200, Vitaly Kuznetsov wrote: > Hyper-V 2016 refuses to boot on Skylake+ CPU models because they lack > 'xsaves'/'vmx-xsaves' features and this diverges from real hardware. The > same issue emerges with AMD "EPYC" CPU model prior to version 3 which got > 'xsaves'

[PATCH] decodetree: Allow empty input files for var width

This was broken when varinsnwidth was specified. Signed-off-by: Luis Pires --- scripts/decodetree.py | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 3450a2a08d..fef5eeaf42 100644 --- a/scripts/decodetree.py +++ b

[PATCH] decodetree: Allow custom var width load functions

This is useful in situations where you want decodetree to handle variable width instructions but you want to provide custom code to load the instructions. Suppressing the generation of the load function is necessary to avoid compilation errors due to the load function being unused. This will be us

Re: [PATCH v2] vhost-user-blk: Fail gracefully on too large queue size

On Tue, Apr 13, 2021 at 06:56:54PM +0200, Kevin Wolf wrote: > virtio_add_queue() aborts when queue_size > VIRTQUEUE_MAX_SIZE, so > vhost_user_blk_device_realize() should check this before calling it. > > Simple reproducer: > > qemu-system-x86_64 \ > -chardev null,id=foo \ > -device vhost-

[Bug 1923648] [NEW] macOS App Nap feature gradually freezes QEMU process

Public bug reported: macOS version: 10.15.2 QEMU versions: 5.2.0 (from MacPorts) 5.2.92 (v6.0.0-rc2-23-g9692c7b037) If the QEMU window is not visible (hidden, minimized or another application is in full screen mode), the QEMU process gradually freezes: it still runs, but the VM doe

RE: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

> I'm actually not sure if we'll want translate_init.c for !tcg builds. > It's *primarily* for TCG, but we still need at least some of the cpu > state structure for KVM, and some of that is initialized in > translate_init. > > I think it will probably make more sense to leave it in for a first > cu

Re: [RFC v12 62/65] target/arm: refactor arm_cpu_finalize_features into cpu64

On 3/28/21 9:15 PM, Richard Henderson wrote: > On 3/28/21 1:12 PM, Richard Henderson wrote: >> On 3/26/21 1:36 PM, Claudio Fontana wrote: >>> +++ b/target/arm/monitor.c >>> @@ -184,9 +184,11 @@ CpuModelExpansionInfo >>> *qmp_query_cpu_model_expansion(CpuModelExpansionType type, >>>   if (!

Re: [PATCH 13/13] target/arm: Make translate-neon.c.inc its own compilation unit

On 4/13/21 6:07 PM, Peter Maydell wrote: > Switch translate-neon.c.inc from being #included into translate.c > to being its own compilation unit. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-a32.h | 3 +++ > .../arm/{translate-neon.c.inc => translate-n

Re: [PATCH v2] vhost-user-blk: Fail gracefully on too large queue size

On 4/13/21 6:56 PM, Kevin Wolf wrote: > virtio_add_queue() aborts when queue_size > VIRTQUEUE_MAX_SIZE, so > vhost_user_blk_device_realize() should check this before calling it. > > Simple reproducer: > > qemu-system-x86_64 \ > -chardev null,id=foo \ > -device vhost-user-blk-pci,queue-siz

Re: [PATCH v1 3/3] target/ppc: Add POWER10 exception model

On 4/13/21 5:53 PM, Fabiano Rosas wrote: > Nicholas Piggin writes: > >> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], >> and it removes support for the LPCR[AIL]=0b10 mode. >> >> Signed-off-by: Nicholas Piggin >> --- >> hw/ppc/spapr_hcall.c| 5 ++ >> target

Re: [PATCH 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc

On 4/13/21 6:07 PM, Peter Maydell wrote: > The function vfp_reg_ptr() is used only in translate-neon.c.inc; > move it there. > > Signed-off-by: Peter Maydell > --- > target/arm/translate.c | 7 --- > target/arm/translate-neon.c.inc | 7 +++ > 2 files changed, 7 insertions(+), 7

Re: [PULL v2 0/3] osdep.h + QOM changes for QEMU 6.0-rc3

Patchew URL: https://patchew.org/QEMU/20210413160850.240064-1-pbonz...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210413160850.240064-1-pbonz...@redhat.com Subject: [PULL v2 0/3] osdep.h + QOM changes

Re: [PATCH 08/13] target/arm: Make translate-vfp.c.inc its own compilation unit

On 4/13/21 6:07 PM, Peter Maydell wrote: > Switch translate-vfp.c.inc from being #included into translate.c > to being its own compilation unit. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-a32.h | 2 ++ > target/arm/{translate-vfp.c.inc => translate-vf

Re: [PATCH 12/13] target/arm: Make functions used by translate-neon global

On 4/13/21 6:07 PM, Peter Maydell wrote: > Make the remaining functions needed by the translate-neon code > global. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-a32.h | 8 > target/arm/translate.c | 10 ++ > 2 files changed, 10 insertions(+), 8 deletions(-)

Re: [PATCH 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc

On 4/13/21 6:07 PM, Peter Maydell wrote: > The function vfp_reg_ptr() is used only in translate-neon.c.inc; > move it there. > > Signed-off-by: Peter Maydell > --- > target/arm/translate.c | 7 --- > target/arm/translate-neon.c.inc | 7 +++ > 2 files changed, 7 insertions(+), 7

Re: [PATCH 06/13] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc

On 4/13/21 6:07 PM, Peter Maydell wrote: > The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32() > and vfp_store_reg64() are used only in translate-vfp.c.inc. Move > them to that file. > > Signed-off-by: Peter Maydell > --- > target/arm/translate.c | 20

Re: [PATCH 07/13] target/arm: Make functions used by translate-vfp global

On 4/13/21 6:07 PM, Peter Maydell wrote: > Make the remaining functions which are needed by translate-vfp.c.inc > global. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-a32.h | 32 > target/arm/translate.c | 37 ++---

Re: [PATCH] vhost-user-blk: Fail gracefully on too large queue size

Am 13.04.2021 um 18:52 hat Kevin Wolf geschrieben: > virtio_add_queue() aborts when queue_size > VIRTQUEUE_MAX_SIZE, so > vhost_user_blk_device_realize() should check this before calling it. > > Simple reproducer: > > qemu-system-x86_64 \ > -chardev null,id=foo \ > -device vhost-user-blk-

Re: [PATCH 01/13] target/arm: Move constant expanders to translate.h

On 4/13/21 6:07 PM, Peter Maydell wrote: > Some of the constant expanders defined in translate.c are generically > useful and will be used by the separate C files for VFP and Neon once > they are created; move the expander definitions to translate.h. > > Signed-off-by: Peter Maydell > --- > targ

[PATCH v2] vhost-user-blk: Fail gracefully on too large queue size

virtio_add_queue() aborts when queue_size > VIRTQUEUE_MAX_SIZE, so vhost_user_blk_device_realize() should check this before calling it. Simple reproducer: qemu-system-x86_64 \ -chardev null,id=foo \ -device vhost-user-blk-pci,queue-size=4096,chardev=foo Fixes: https://bugzilla.redhat.com

[PATCH v2] target/s390x: Fix translation exception on illegal instruction

Hitting an uretprobe in a s390x TCG guest causes a SIGSEGV. What happens is: * uretprobe maps a userspace page containing an invalid instruction. * uretprobe replaces the target function's return address with the address of that page. * When tb_gen_code() is called on that page, tb->size ends up

[PATCH] vhost-user-blk: Fail gracefully on too large queue size

virtio_add_queue() aborts when queue_size > VIRTQUEUE_MAX_SIZE, so vhost_user_blk_device_realize() should check this before calling it. Simple reproducer: qemu-system-x86_64 \ -chardev null,id=foo \ -device vhost-user-blk-pci,queue-size=4096,chardev=foo Fixes: https://bugzilla.redhat.com

Re: [PATCH 3/3] hw/arm/mps2-tz: Implement AN524 memory remapping via machine property

On 4/12/21 3:43 PM, Peter Maydell wrote: > The AN524 FPGA image supports two memory maps, which differ > in where the QSPI and BRAM are. In the default map, the BRAM > is at 0x_, and the QSPI at 0x2800_. In the second > map, they are the other way around. > > In hardware, the initial m

Re: [PATCH] tests/acceptance: Add a 'virt_kvm' test using the GICv3

Hi Alex, On 4/12/21 7:55 PM, Philippe Mathieu-Daudé wrote: > On 4/6/21 7:12 PM, Alex Bennée wrote: >> >> Philippe Mathieu-Daudé writes: >> >>> On 3/31/21 5:45 PM, Alex Bennée wrote: Philippe Mathieu-Daudé writes: > The current 'virt_kvm' test is restricted to GICv2, but can al

Re: [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document

On Wed, Mar 31, 2021 at 05:05:27PM +0200, Paolo Bonzini wrote: > In an ideal world, we would all get along together very well, always be > polite and never end up in huge conflicts. And even if there are conflicts, > we would always handle each other fair and respectfully. Unfortunately, > this is

RE: [PATCH v2] target/ppc: code motion from translate_init.c.inc to gdbstub.c

> > +/* gdbstub.c */ > > +void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *ppc); > > +gchar *ppc_gdb_arch_name(CPUState *cs); > > These should probably go into internal.h and not cpu.h. > These do not need to be exposed outside of target/ppc/. Makes sense, I can do that. Is such a small change wor

Re: [PATCH 0/3] mps3-an524: support memory remapping

On 4/13/21 6:29 PM, Philippe Mathieu-Daudé wrote:> On 4/12/21 4:48 PM, Peter Maydell wrote: >> On Mon, 12 Apr 2021 at 15:37, Philippe Mathieu-Daudé wrote: >>> On 4/12/21 3:43 PM, Peter Maydell wrote: The AN524 FPGA image supports two memory maps, which differ in where the QSPI and BRAM a

[PULL v2 3/3] qapi/qom.json: Do not use CONFIG_VIRTIO_CRYPTO in common code

From: Thomas Huth The ObjectType enum and ObjectOptions are included from qapi-types-qom.h into common code. We should not use target-specific config switches like CONFIG_VIRTIO_CRYPTO here, since this is not defined in common code and thus the enum will look differently between common and target

Re: [PATCH 2/3] hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping

On 4/12/21 3:43 PM, Peter Maydell wrote: > On some boards, SCC config register CFG0 bit 0 controls whether > parts of the board memory map are remapped. Support this with: > * a device property scc-cfg0 so the board can specify the >initial value of the CFG0 register > * an outbound GPIO line

Re: [PATCH 0/3] mps3-an524: support memory remapping

Hi Peter, On 4/12/21 4:48 PM, Peter Maydell wrote: > On Mon, 12 Apr 2021 at 15:37, Philippe Mathieu-Daudé wrote: >> On 4/12/21 3:43 PM, Peter Maydell wrote: >>> The AN524 FPGA image supports two memory maps, which differ >>> in where the QSPI and BRAM are. In the default map, the BRAM >>> is at 0

[PULL v2 2/3] osdep: protect qemu/osdep.h with extern "C"

System headers may include templates if compiled with a C++ compiler, which cause the compiler to complain if qemu/osdep.h is included within a C++ source file's 'extern "C"' block. Add an 'extern "C"' block directly to qemu/osdep.h, so that system headers can be kept out of it. There is a stray

[PATCH 13/13] target/arm: Make translate-neon.c.inc its own compilation unit

Switch translate-neon.c.inc from being #included into translate.c to being its own compilation unit. Signed-off-by: Peter Maydell --- target/arm/translate-a32.h | 3 +++ .../arm/{translate-neon.c.inc => translate-neon.c} | 12 +++- target/arm/translate.c

[PATCH 07/13] target/arm: Make functions used by translate-vfp global

Make the remaining functions which are needed by translate-vfp.c.inc global. Signed-off-by: Peter Maydell --- target/arm/translate-a32.h | 32 target/arm/translate.c | 37 ++--- 2 files changed, 38 insertions(+), 31 deletions(-

[PATCH 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc

The function vfp_reg_ptr() is used only in translate-neon.c.inc; move it there. Signed-off-by: Peter Maydell --- target/arm/translate.c | 7 --- target/arm/translate-neon.c.inc | 7 +++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/targe

[PATCH 11/13] target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h

Move the NeonGenThreeOpEnvFn typedef to translate.h together with the other similar typedefs. Signed-off-by: Peter Maydell --- target/arm/translate.h | 2 ++ target/arm/translate.c | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.h b/target/arm/transla

[PATCH 08/13] target/arm: Make translate-vfp.c.inc its own compilation unit

Switch translate-vfp.c.inc from being #included into translate.c to being its own compilation unit. Signed-off-by: Peter Maydell --- target/arm/translate-a32.h | 2 ++ target/arm/{translate-vfp.c.inc => translate-vfp.c} | 12 +++- target/arm/translate.c

[PATCH 06/13] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc

The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32() and vfp_store_reg64() are used only in translate-vfp.c.inc. Move them to that file. Signed-off-by: Peter Maydell --- target/arm/translate.c | 20 target/arm/translate-vfp.c.inc | 20 +

[PATCH 04/13] target/arm: Split m-nocp trans functions into their own file

Currently the trans functions for m-nocp.decode all live in translate-vfp.inc.c; move them out into their own translation unit, translate-m-nocp.c. The trans_* functions here are pure code motion with no changes. Signed-off-by: Peter Maydell --- target/arm/translate-a32.h | 3 + target/ar

[PATCH 03/13] target/arm: Make functions used by m-nocp global

We want to split out the .c.inc files which are currently included into translate.c so they are separate compilation units. To do this we need to make some functions which are currently file-local to translate.c have global scope; create a translate-a32.h paralleling the existing translate-a64.h a

[PATCH 01/13] target/arm: Move constant expanders to translate.h

Some of the constant expanders defined in translate.c are generically useful and will be used by the separate C files for VFP and Neon once they are created; move the expander definitions to translate.h. Signed-off-by: Peter Maydell --- target/arm/translate.h | 24 targe

[PATCH 02/13] target/arm: Share unallocated_encoding() and gen_exception_insn()

The unallocated_encoding() function is the same in both translate-a64.c and translate.c; make the translate.c function global and drop the translate-a64.c version. To do this we need to also share gen_exception_insn(), which currently exists in two slightly different versions for A32 and A64: merg

[PULL v2 1/3] osdep: include glib-compat.h before other QEMU headers

glib-compat.h is sort of like a system header, and it needs to include system headers (glib.h) that may dislike being included under 'extern "C"'. Move it right after all system headers and before all other QEMU headers. Signed-off-by: Paolo Bonzini --- include/qemu/osdep.h | 3 ++- 1 file chan

[PATCH 00/13] target/arm: Split translate-*.c.inc into separate compilation units

When we first converted the A32/T32 frontends to use decodetree, we put the trans* functions for VFP and Neon into their own separate files, but used the preprocessor to just #include those files into translate.c. This was a pragmatic arrangement to avoid having to also rearrange translate.c which

[PULL v2 0/3] osdep.h + QOM changes for QEMU 6.0-rc3

The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12 12:12:09 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream

[PATCH 12/13] target/arm: Make functions used by translate-neon global

Make the remaining functions needed by the translate-neon code global. Signed-off-by: Peter Maydell --- target/arm/translate-a32.h | 8 target/arm/translate.c | 10 ++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/tr

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