Re: [PATCH 2/2] hw/block/nvme: align reserved fields declarations

On Mar 17 15:00, Gollu Appalanaidu wrote: Align the Reserved fields declaration in NvmeBar Signed-off-by: Gollu Appalanaidu --- include/block/nvme.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/block/nvme.h b/include/block/nvme.h index fc65cfcb01..e5bd00bb85 100644

Re: [PATCH 1/2] hw/block/nvme: align with existing style

On Mar 17 15:00, Gollu Appalanaidu wrote: Make uniform hexadecimal numbers format. Signed-off-by: Gollu Appalanaidu --- hw/block/nvme.c | 30 +++--- include/block/nvme.h | 10 +- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/block/nvme.c

Re: Mac OS - Standalone Installer

On Thu, 15 Apr 2021 at 01:16, Richard Hill wrote: > > ... a standalone installer for QEMU for Mac OS? > The xPack QEMU Arm is distributed as standalone archives, for all platforms, including macOS: https://github.com/xpack-dev-tools/qemu-arm-xpack/releases They do not even require install, s

Re: [EXTERNAL] [RFC PATCH 2/2] target/ppc: Add POWER10 exception model

On 4/15/21 7:28 AM, Nicholas Piggin wrote: > Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am: >> On 4/14/21 5:23 AM, Nicholas Piggin wrote: >>> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], >>> and it removes support for the LPCR[AIL]=0b10 mode. >> >> This

Re: [PATCH v2 2/8] qapi/error: Use Python3-style super()

John Snow writes: > Signed-off-by: John Snow > --- > scripts/qapi/error.py | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/scripts/qapi/error.py b/scripts/qapi/error.py > index 126dda7c9b..38bd7c4dd6 100644 > --- a/scripts/qapi/error.py > +++ b/scripts/qapi/error.py > @

Re: [PATCH v2 1/8] qapi/error: Repurpose QAPIError as a generic exception base class

John Snow writes: > Rename QAPIError to QAPISourceError, and then create a new QAPIError > class that serves as the basis for all of our other custom exceptions. Isn't the existing QAPIError such a base class already? Peeking ahead... aha, your new base class is abstract. Can you explain why

Re: [PATCH for-6.1 3/4] qapi/qom.json: Do not use CONFIG_VIRTIO_CRYPTO in common code

On 14/04/2021 15.55, Markus Armbruster wrote: Thomas Huth writes: The ObjectType enum and ObjectOptions are included from qapi-types-qom.h into common code. We should not use target-specific config switches like CONFIG_VIRTIO_CRYPTO here, since this is not defined in common code and thus the e

Re: [Bug 1923197] Re: RISC-V priviledged instruction error

Hello Francis, I'll configure PMP than do the test again. Sorry I hadn't understood what changed between version 5.2 and 6.0-rc2, since my code worked before. Best regards, Teodori Serge On Thu, 15 Apr 2021, 06:15 Alistair Francis, <1923...@bugs.launchpad.net> wrote: > I'm guessing that this is

Re: [PATCH] hw/block/nvme: remove redundant invalid_lba_range trace

On Apr 14 12:34, Gollu Appalanaidu wrote: Currently pci_nvme_err_invalid_lba_range tace being called indvidually at each function, add this in nvme_check_bounds and remove redundant usage of it. Signed-off-by: Gollu Appalanaidu --- hw/block/nvme.c | 9 + 1 file changed, 1 insertion(+), 8

Re: [PULL v2 0/3] osdep.h + QOM changes for QEMU 6.0-rc3

Peter Maydell writes: > On Tue, 13 Apr 2021 at 17:18, Paolo Bonzini wrote: >> >> The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620: >> >> Merge remote-tracking branch >> 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12 >> 12:12:09 +0100) >>

Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2

On 2021/4/15 下午12:46, Alistair Francis wrote: On Tue, Apr 13, 2021 at 1:28 PM LIU Zhiwei wrote: ping +1. On 2021/2/12 下午11:02, LIU Zhiwei wrote: This patchset implements the packed extension for RISC-V on QEMU. This patchset have passed all my direct Linux user mode cases(RV64) and bare me

[PATCH v2 3/4] target/ppc: Rework AIL logic in interrupt delivery

The AIL logic is becoming unmanageable spread all over powerpc_excp(), and it is slated to get even worse with POWER10 support. Move it all to a new helper function. Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c|

[PATCH v2 4/4] target/ppc: Add POWER10 exception model

POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=0b10 mode. Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c| 7 - target/ppc/cpu-qom.h|

[PATCH v2 0/4] ppc: rework AIL logic, add POWER10 exception model

Here's a rollup of where this ended up, hopefully it suits everyone's preference. Thanks for the review and catching several issues. Patches 1-3 are unchanged except for minor comment and changelog tweaks, patch 4 contains fixes for the issues Cedric noticed. Thanks, Nick Nicholas Piggin (4):

[PATCH v2 2/4] target/ppc: POWER10 supports scv

This must have slipped through the cracks between adding POWER10 support and scv support. Signed-off-by: Nicholas Piggin --- target/ppc/translate_init.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index

[PATCH v2 1/4] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour

ISA v3.0 radix guest execution has a quirk in AIL behaviour such that the LPCR[AIL] value can apply to hypervisor interrupts. This affects machines that emulate HV=1 mode (i.e., powernv9). Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 17 + 1 file changed, 13 ins

Re: [EXTERNAL] [RFC PATCH 2/2] target/ppc: Add POWER10 exception model

Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am: > On 4/14/21 5:23 AM, Nicholas Piggin wrote: >> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], >> and it removes support for the LPCR[AIL]=0b10 mode. > > This looks good but it's missing the MSR_LE setting.

Re: [EXTERNAL] [RFC PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery

Excerpts from Cédric Le Goater's message of April 15, 2021 1:24 am: > On 4/14/21 5:23 AM, Nicholas Piggin wrote: >> The AIL logic is becoming unmanageable spread all over powerpc_excp(), >> and it is slated to get even worse with POWER10 support. >> >> Move it all to a new helper function. > > Re

[Bug 1923629] Re: RISC-V Vector Instruction vssub.vv not saturating

Thanks for raising this bug case. A fix should be available soon. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1923629 Title: RISC-V Vector Instruction vssub.vv not saturating Status in QEMU: N

Re: [PATCH] docs: Add documentation for shakti_c machine

On Tue, Apr 13, 2021 at 3:44 AM Vijai Kumar K wrote: > > Add documentation for Shakti C reference platform. > > Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Alistair > --- > docs/system/riscv/shakti-c.rst | 82 ++ > 1 file changed, 82 insertions(

Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2

On Tue, Apr 13, 2021 at 1:28 PM LIU Zhiwei wrote: > > ping +1. > > On 2021/2/12 下午11:02, LIU Zhiwei wrote: > > This patchset implements the packed extension for RISC-V on QEMU. > > > > This patchset have passed all my direct Linux user mode cases(RV64) and > > bare metal cases(RV32) on X86-64 Ubun

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

On Thu, Apr 15, 2021 at 2:18 PM LIU Zhiwei wrote: > > Hi Alistair, > > I think that this bug has been resolved in my packed-extension patch set[1]. > > Would you mind to have a test and merge it before the whole patch set? Great! Thanks I have applied patch 3 for the next PR. Alistair > > Than

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

Hi Alistair, I think that this bug has been resolved in my packed-extension patch set[1]. Would you mind to have a test and merge it before the whole patch set? Thanks. Best Regards, Zhiwei [1]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg782125.html On 2021/4/15 上午11:57, Alist

Re: [PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP)

On Wed, Apr 14, 2021 at 5:35 PM Bin Meng wrote: > > Hi Alistair, > > On Tue, Apr 13, 2021 at 10:42 AM Alistair Francis > wrote: > > > > From: Hou Weiying > > > > This commit adds support for ePMP v0.9.1. > > > > The ePMP spec can be found in: > > https://docs.google.com/document/d/1Mh_aiHYxemL0u

[Bug 1923197] Re: RISC-V priviledged instruction error

I'm guessing that this is a bug in your guest as it hasn't configured PMP regions. >From the RISC-V spec: " If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails. " Confusin

[Bug 1923197] Re: RISC-V priviledged instruction error

You can check this by reverting this QEMU commit: commit d102f19a2085ac931cb998e6153b73248cca49f1 Author: Atish Patra Date: Wed Dec 23 11:25:53 2020 -0800 target/riscv/pmp: Raise exception if no PMP entry is configured As per the privilege specification, any access from S/U mode s

Issue Report: When VM memory is extremely large, downtime for RDMA migration is high. (64G mem --> extra 400ms)

Hi: When I tested RDMA live migration, I found that the downtime increased as the VM's memory increased. My Mellanox network card is [ConnectX-4 LX] and the driver is MLNX-5.2, My VM memory size is 64GB, downtime is 430ms when I migrate using the following parameters: virsh migrate --live --p2p

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

Add Frank, he is the SiFive's qemu maintainer. On Thu, Apr 15, 2021 at 11:57 AM Alistair Francis wrote: > > + LIU Zhiwei and Kito Cheng > > Alistair > > On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote: > > > > Public bug reported: > > > > I noticed doing a negate ( 0

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

+ LIU Zhiwei and Kito Cheng Alistair On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote: > > Public bug reported: > > I noticed doing a negate ( 0 – 0x8000 ) using vssub.vv produces an > incorrect result of 0x8000 (should saturate to 0x7FFF). > > Here is the

[PATCH v6 4/4] net: Extend host forwarding to support IPv6

Net option "-hostfwd" now supports IPv6 addresses. Commands hostfwd_add, hostfwd_remove now support IPv6 addresses. Tested: avocado run tests/acceptance/hostfwd.py Signed-off-by: Doug Evans --- Changes from v5: Recognize ipv4=,ipv6= options. hmp-commands.hx | 18 ++- net/slir

[PATCH v6 3/4] net/slirp.c: Refactor address parsing

... in preparation for adding ipv6 host forwarding support. Tested: avocado run tests/acceptance/hostfwd.py Signed-off-by: Doug Evans --- Changes from v5: Use InetSocketAddress and getaddrinfo(). Use new libslirp calls: slirp_remove_hostxfwd, slirp_add_hostxfwd. include/qemu/sockets.h |

[PATCH v6 2/4] util/qemu-sockets.c: Split host:port parsing out of inet_parse

The parsing is moved into new function inet_parse_host_port. Also split out is ipv4=flag, ipv6=flag processing into inet_parse_ipv46. This is done in preparation for using these functions in net/slirp.c. Signed-off-by: Doug Evans --- Changes from v5: Also split out parsing of ipv4=on|off, ipv6=

[PATCH v6 0/4] Add support for ipv6 host forwarding

This patchset takes the original patch from Maxim, https://www.mail-archive.com/qemu-devel@nongnu.org/msg569573.html and updates it. Option hostfwd is extended to support ipv6 addresses. Commands hostfwd_add, hostfwd_remove are extended as well. The libslirp part of the patch has been committed u

[PATCH v6 1/4] slirp: Advance libslirp submodule to add ipv6 host-forward support

5eraph (2): disable_dns option limit vnameserver_addr to port 53 Akihiro Suda (1): libslirp.h: fix SlirpConfig v3 documentation Doug Evans (11): Add ipv6 host forward support tcpx_listen: Pass sizeof(addr) to memset Reject host forwarding to ipv6 "addr-any"

Re: [RFC v9 15/29] vfio: Set up nested stage mappings

Hi Eric, On 2021/4/14 16:05, Auger Eric wrote: Hi Kunkun, On 4/14/21 3:45 AM, Kunkun Jiang wrote: On 2021/4/13 20:57, Auger Eric wrote: Hi Kunkun, On 4/13/21 2:10 PM, Kunkun Jiang wrote: Hi Eric, On 2021/4/11 20:08, Eric Auger wrote: In nested mode, legacy vfio_iommu_map_notify cannot be

[ANNOUNCE] QEMU 6.0.0-rc3 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the fourth release candidate for the QEMU 6.0 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu-project.org/qemu-6.0.0-rc3.tar.xz http://down

Re: [PATCH v3 3/3] accel/tcg: Assert that tb->size != 0 after translation

On Wed, Apr 14, 2021 at 12:43 PM Richard Henderson wrote: > > On 4/14/21 11:03 AM, Max Filippov wrote: > > On Wed, Apr 14, 2021 at 9:51 AM Ilya Leoshkevich wrote: > >> On Wed, 2021-04-14 at 16:48 +0200, David Hildenbrand wrote: > >>> Did you double-check the xtensa issue? > >> > >> Oh, I'm sorry,

[Bug 1922611] Re: Acceptance Tests: migration fails on sparc target

I can confirm this bug has been fixed. Relevant test output: VM launch command: './qemu-system-sparc -display none -vga none -chardev socket,id=mon,path=/tmp/avo_qemu_sock_g0w15g26/qemu-1672256-monitor.sock -mon chardev=mon,mode=control -incoming tcp:localhost:53800 -nodefaults' >>> {'execute':

Re: [PATCH 5/5] target/ppc: Implement paddi and replace addi insns

On 4/14/21 12:11 PM, Richard Henderson wrote: static bool allow_prefix_MLS(DisasContext *ctx, arg_D *a) {     int64_t imm;     /* Require MLS prefix or no prefix. */     if (ctx->prefix_type != PREFIX_MLS) {     if (ctx->prefix_type == PREFIX_NONE) {     return true;     }

Re: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

On Mon, Apr 12, 2021 at 4:57 PM Yifei Jiang wrote: > > Only support supervisor external interrupt currently. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis Alistair > --- > hw/intc/sifive_plic.c| 29 - > target/riscv/

Re: [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM

On Mon, Apr 12, 2021 at 4:56 PM Yifei Jiang wrote: > > Get kernel and fdt start address in virt.c, and pass them to KVM > when cpu reset. In addition, add kvm_riscv.h to place riscv specific > interface. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis

Re: [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers

On Mon, Apr 12, 2021 at 4:56 PM Yifei Jiang wrote: > > Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > target/riscv/kvm.c | 142 - > 1 file changed, 141 insertions(+), 1 d

Re: [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers

On Mon, Apr 12, 2021 at 4:58 PM Yifei Jiang wrote: > > Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis Alistair > --- > target/riscv/kvm.c | 150 +

Re: [PATCH RFC v5 09/12] target/riscv: Add host cpu type

On Mon, Apr 12, 2021 at 4:54 PM Yifei Jiang wrote: > > 'host' type cpu is set isa to RVXLEN simply, more isa info > will obtain from KVM in kvm_arch_init_vcpu() > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 9 +

Re: [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu

On Mon, Apr 12, 2021 at 4:53 PM Yifei Jiang wrote: > > Get isa info from kvm while kvm init. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > target/riscv/kvm.c | 27 ++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kv

[Bug 1923693] Re: Lack of architecture in gdbstub makes debugging confusing

Thanks for raising this. I have marked it as fixes as like you say it's fixed in mainline. ** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/192369

[PATCH 1/3] Acceptance Tests: rename attribute holding the distro image checksum

This renames the attribute that holds the checksum for the image Linux distribution image used. The current name of the attribute is not very descriptive. Also, in preparation for making the distribution used configurable, which will add distro related parameters, attributes and tags, let's make

[PATCH 0/3] Acceptance Tests: support choosing specific distro and version

Because Fedora 31 will not suit all tests that depend on a Linux guest, this allows for the configuration of the guest distribution. It came out of a suggestion from Eric Auger, and it was actually a feature I planned to submit for a while. This is based on the following series: [PATCH v3 00/11]

[PATCH 2/3] Acceptance Tests: move definition of distro checksums to the framework

Instead of having, by default, the checksum in the tests, and the definition of tests in the framework, let's keep them together. A central definition for distributions is available, and it should allow other known distros to be added more easily. No behavior change is expected here, and tests ca

[PATCH 3/3] Acceptance Tests: support choosing specific distro and version

The tests based on the LinuxTest class give the test writer a ready to use guest operating system, currently pinned to Fedora 31. With this change, it's now possible to choose different distros and versions, similar to how other tags and parameter can be set for the target arch, accelerator, etc.

Mac OS - Standalone Installer

Hello Everyone! I would like to ask if anyone on this list is aware of a standalone installer for QEMU for Mac OS? I am aware of the excellent work carried out by Stefan Weil for the Windows Platform and I wondered if something similar existed for the Mac? The approach of using Homebrew will

Re: [PATCH 0/2] virtiofsd: Enable xattr if xattrmap is used

On Wed Apr 14, 2021 at 3:12 PM CDT, Carlos Venegas wrote: > > Using xattrmap for Kata Containers we found that xattr is should be used > or xattrmap wont work. These patches enable xattr when -o xattrmap is > used. Also, they add help for the xattrmap option on `virtiofsd --help` > output. > > Carl

Re: [Virtio-fs] [PATCH 2/2] virtiofsd: Add help for -o xattr-mapping

On Wed Apr 14, 2021 at 3:12 PM CDT, Carlos Venegas wrote: > The option is not documented in help. > > Add small help about the option. > > Signed-off-by: Carlos Venegas > --- > tools/virtiofsd/helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/tools/virtiofsd/helper.c b/tools/virt

RE: [PATCH 00/11] Add support for Blob resources feature

Hi Gerd, > > > Any other ideas as to how to eliminate that Blit cleanly? > > Well, "cleanly" pretty much implies "supported by toolkit". [Kasireddy, Vivek] I was kind of hoping you'd not draw that implication :) > > gtk glarea for example sets up a framebuffer and expects the application > ren

[PATCH v7 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index

Re: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

On 4/14/21 1:07 PM, Bruno Piazera Larsen wrote: I think it would be worth moving all of the SPR code out to a separate file, apart from cpu_init.c.  There's a lot of it.  And, yes, I would move everything that you can that is related out of translate.c. Yeah, now that I look at the SPR code, I

[PATCH v7 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses

Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds TLB invalidation instructions to invalidate ranges of addresses. Signed-off-by: Rebecca Cran --- accel/tcg/cputlb.c | 130 +++- include/exec/exec-all.h | 46 +++ 2 files changed, 173 insertions(+), 3

[PATCH v7 2/4] target/arm: Add support for FEAT_TLBIRANGE

ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran --- target/arm/cpu.h| 5 + target/arm/helper.c | 296 2 files changed, 301 insertions(+) diff --git a/target/arm/

[PATCH v7 3/4] target/arm: Add support for FEAT_TLBIOS

ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran --- target/arm/cpu.h| 5 ++ target/arm/helper.c | 75 2 files changed, 80 insertions(+) diff --git a/target/arm/cpu.

[PATCH v7 0/4] Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE. They provides TLBI maintenance instructions that extend to the Outer Shareable domain and that apply to a range of input addresses. Changes from v6 to v7: o Fixed the tlbi_aa64_rvae1_write the tlbi_aa64_rvae1is_write functions to pass

[PATCH 1/2] virtiofsd: Allow use "-o xattrmap" without "-o xattr"

When -o xattrmap is used, it will not work unless xattr is enabled. This patch enables xattr when -o xattrmap is used. Signed-off-by: Carlos Venegas --- tools/virtiofsd/passthrough_ll.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/virtiofsd/passthrough_ll.c b/tools/virtiofsd/passth

[PATCH 2/2] virtiofsd: Add help for -o xattr-mapping

The option is not documented in help. Add small help about the option. Signed-off-by: Carlos Venegas --- tools/virtiofsd/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/virtiofsd/helper.c b/tools/virtiofsd/helper.c index 28243b51b2..5e98ed702b 100644 --- a/tools/virtiofsd/

[PATCH 0/2] virtiofsd: Enable xattr if xattrmap is used

Using xattrmap for Kata Containers we found that xattr is should be used or xattrmap wont work. These patches enable xattr when -o xattrmap is used. Also, they add help for the xattrmap option on `virtiofsd --help` output. Carlos Venegas (2): virtiofsd: Allow use "-o xattrmap" without "-o xa

Re: [PATCH v3] target/ppc: code motion from translate_init.c.inc to gdbstub.c

On 4/14/21 7:59 AM, Bruno Larsen (billionai) wrote: All the code related to gdb has been moved from translate_init.c.inc file to the gdbstub.c file, where it makes more sense. This new version puts the prototypes in internal.h, to not expose them unnecessarily. Signed-off-by: Bruno Larsen (bill

RE: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

> > The trivial path is to: > > * rename translate_init.c.inc to cpu_init.c (since it has to do with > > initial definitions for CPUs, and it's not related to translating > > anymore); > > Anymore? You mean after you've moved out everything related to > create_ppc_opcodes? Sure. yeah, that. Als

RE: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

Bruno Piazera Larsen writes: >> > * move gen_write_xer and gen_read_xer into cpu_init.c, as they're >> > used for some sprs, and whatever needs to be moved with it >> >> I'd leave them where they are currently. Instead what I think we should >> do is to find a way to not need the uea/oea/hea|read

[PATCH 2/2] util/async: print leaked BH name when AioContext finalizes

BHs must be deleted before the AioContext is finalized. If not, it's a bug and probably indicates that some part of the program still expects the BH to run in the future. That can lead to memory leaks, inconsistent state, or just hangs. Unfortunately the assert(flags & BH_DELETED) call in aio_ctx_

[PATCH 1/2] util/async: add a human-readable name to BHs for debugging

It can be difficult to debug issues with BHs in production environments. Although BHs can usually be identified by looking up their ->cb() function pointer, this requires debug information for the program. It is also not possible to print human-readable diagnostics about BHs because they have no id

[PATCH 0/2] util/async: print leaked BH name when AioContext finalizes

Eric Ernst and I debugged a BH leak and it was more involved than it should be. The problem is that BHs don't have a human-readable identifier, so low-level debugging techniques and inferences about the code are required to figure out which BH was leaked in production environments without easy debu

Converting QEMU .raw to VMDK VMware

Hi, I have a question, how do I go about converting a .raw snapshot to VMware VMDK? We're looking to move the .raw snapshot to our new VMware environment for DevOps. Thanks, BlackSalt Technology Group Terrance Battle | CEO tbat...@thebstgroup.com 202.579.7334 (

Re: [PATCH 2/5] decodetree: Fix empty input files for varinsnwidth

On 4/13/21 2:11 PM, Luis Pires wrote: Decodetree would throw an error when the input file was empty and --varinsnwidth was specified. Signed-off-by: Luis Pires --- scripts/decodetree.py | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson +

[Bug 1923497] Re: bios_linker_loader_add_checksum: Assertion `start_offset < file->blob->len' failed

The patch may be a bit beyond me at the moment as I use a package to install this and would have to figure out how to download source, get it configure, patched and compiled. Whew! Maybe ... But here is my XML config file. ** Attachment added: "domain xml file" https://bugs.launchpad.net/qe

Re: [PATCH v3 3/3] accel/tcg: Assert that tb->size != 0 after translation

On 4/14/21 11:03 AM, Max Filippov wrote: On Wed, Apr 14, 2021 at 9:51 AM Ilya Leoshkevich wrote: On Wed, 2021-04-14 at 16:48 +0200, David Hildenbrand wrote: Did you double-check the xtensa issue? Oh, I'm sorry, I completely forgot about that one. I just ran the test locally, and apparently i

Re: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

On 4/13/21 10:43 AM, Bruno Piazera Larsen wrote: The trivial path is to: * rename translate_init.c.inc to cpu_init.c (since it has to do with initial definitions for CPUs, and it's not related to translating anymore); Anymore? You mean after you've moved out everything related to create_ppc_o

Re: [PATCH RFC 0/7] RFC: Asynchronous QMP Draft

First and foremost, thank you for reviewing this! It is very helpful to me to see what others think of this pet project I've been growing in the privacy of my own mind. On 4/14/21 2:38 AM, Stefan Hajnoczi wrote: Below are the API docs that I found helpful for understanding the big picture. Th

tidying up osdep.h

(cc'ing people related to the recent 'extern "C"' patches and also randomly Markus as somebody who's had opinions on header cleanups in the past...) osdep.h as it stands today is a mix of two things: (1) it has the "must be included by everybody" items: (a) config-host.h, poison.h, compiler.h

Re: [PATCH 5/5] target/ppc: Implement paddi and replace addi insns

On 4/13/21 2:11 PM, Luis Pires wrote: +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -0,0 +1,26 @@ Missing copyright+license header. +static bool trans_paddi(DisasContext *ctx, arg_paddi *a) +{ +if (a->r == 0) { +if (a->ra == 0) { +/* li case */ +tcg_g

Re: [PATCH v5 12/14] hmp: Print "share" property of memory backends with "info memdev"

* David Hildenbrand (da...@redhat.com) wrote: > Let's print the property. > > Cc: Markus Armbruster > Cc: Eric Blake > Cc: Igor Mammedov > Signed-off-by: David Hildenbrand Reviewed-by: Dr. David Alan Gilbert > --- > hw/core/machine-hmp-cmds.c | 2 ++ > 1 file changed, 2 insertions(+) > >

Re: [PULL v2 2/3] osdep: protect qemu/osdep.h with extern "C"

On Wed, 14 Apr 2021 at 18:26, Daniel P. Berrangé wrote: > > On Tue, Apr 13, 2021 at 06:08:49PM +0200, Paolo Bonzini wrote: > > #ifdef _WIN32 > > #include "sysemu/os-win32.h" > > This and os-posix.h both include other system headers. We don't currently > have problem, so this is ok as the minimal

Re: [RFC PATCH 0/5] mptcp support

* Daniel P. Berrangé (berra...@redhat.com) wrote: > On Mon, Apr 12, 2021 at 03:51:10PM +0100, Dr. David Alan Gilbert wrote: > > * Daniel P. Berrangé (berra...@redhat.com) wrote: > > > On Thu, Apr 08, 2021 at 08:11:54PM +0100, Dr. David Alan Gilbert (git) > > > wrote: > > > > From: "Dr. David Alan

[PATCH] include/qemu/osdep.h: Move system includes to top

Mostly osdep.h puts the system includes at the top of the file; but there are a couple of exceptions where we include a system header halfway through the file. Move these up to the top with the rest so that all the system headers we include are included before we include os-win32.h or os-posix.h.

Re: [PULL v2 2/3] osdep: protect qemu/osdep.h with extern "C"

On Wed, 14 Apr 2021 at 18:26, Daniel P. Berrangé wrote: > > On Tue, Apr 13, 2021 at 06:08:49PM +0200, Paolo Bonzini wrote: > > System headers may include templates if compiled with a C++ compiler, > > which cause the compiler to complain if qemu/osdep.h is included > > within a C++ source file's '

target/ppc: sPAPR invalid function calls when compiling without TCG

Hi, I have been working on billionai's patch to enable the --disable-tcg option on PowerPC and one of the problems is that 5 files in hw/ppc use functions implemented in mmu-hash64.c which is not compiled with --disable-tcg, I'd like to know how to correct the spapr function call, should I *

Re: [PULL v2 0/3] osdep.h + QOM changes for QEMU 6.0-rc3

On Tue, 13 Apr 2021 at 17:18, Paolo Bonzini wrote: > > The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620: > > Merge remote-tracking branch > 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12 > 12:12:09 +0100) > > are available in the Git reposi

Re: [PATCH v3 3/3] accel/tcg: Assert that tb->size != 0 after translation

On Wed, Apr 14, 2021 at 9:51 AM Ilya Leoshkevich wrote: > On Wed, 2021-04-14 at 16:48 +0200, David Hildenbrand wrote: > > Did you double-check the xtensa issue? > > Oh, I'm sorry, I completely forgot about that one. I just ran the > test locally, and apparently it fails because of this new assert,

Re: [PATCH RFC 6/7] qmp_protocol: add QMP client implementation

On 4/14/21 1:44 AM, Stefan Hajnoczi wrote: On Tue, Apr 13, 2021 at 11:55:52AM -0400, John Snow wrote: +async def _execute(self, msg: Message) -> object: +""" +The same as `execute_msg()`, but without safety mechanisms. + +Does not assign an execution ID and does not c

Re: [PATCH RFC 4/7] message: add QMP Message type

On 4/13/21 4:07 PM, Stefan Hajnoczi wrote: On Tue, Apr 13, 2021 at 11:55:50AM -0400, John Snow wrote: This is an abstraction that represents a single message either sent to or received from the server. It is used to subclass the AsyncProtocol(Generic[T]) type. It was written such that it can be

Re: [PATCH] tests/acceptance: Add a 'virt_kvm' test using the GICv3

Philippe Mathieu-Daudé writes: > Hi Alex, > > On 4/12/21 7:55 PM, Philippe Mathieu-Daudé wrote: >> On 4/6/21 7:12 PM, Alex Bennée wrote: >>> >>> Philippe Mathieu-Daudé writes: >>> On 3/31/21 5:45 PM, Alex Bennée wrote: > > Philippe Mathieu-Daudé writes: > >> The current '

[PATCH] migration/dirtyrate: make sample page count configurable

From: Hyman Huang(黄勇) introduce optional sample-pages argument in calc-dirty-rate, making sample page count per GB configurable so that more accurate dirtyrate can be calculated. Signed-off-by: Hyman Huang(黄勇) --- migration/dirtyrate.c | 32 migration/dirtyrate

[PATCH v3 14/15] qemu_iotests: add option to show qemu binary logs on stdout

Using the flag -p, allow the qemu binary to print to stdout. This helps especially when doing print-debugging. Signed-off-by: Emanuele Giuseppe Esposito --- tests/qemu-iotests/check | 3 ++- tests/qemu-iotests/iotests.py | 9 + tests/qemu-iotests/testenv.py | 9 +++-- 3 files ch

Re: [PATCH RFC 3/7] protocol: generic async message-based protocol loop

On 4/13/21 4:00 PM, Stefan Hajnoczi wrote: On Tue, Apr 13, 2021 at 11:55:49AM -0400, John Snow wrote: This module provides the protocol-agnostic framework upon which QMP will be built. I also have (not included in this series) a qtest implementation that uses this same framework, which is why it

[PATCH v1] migration/dirtyrate: make sample page count configurable

From: Hyman Huang(黄勇) introduce optional sample-pages argument in calc-dirty-rate, making sample page count per GB configurable so that more accurate dirtyrate can be calculated. Signed-off-by: Hyman Huang(黄勇) --- migration/dirtyrate.c | 32 migration/dirtyrate

[PATCH v3 10/15] qemu_iotests: extent QMP socket timeout when using valgrind

As with gdbserver, valgrind delays the test execution, so the default QMP socket timeout timeout too soon. Signed-off-by: Emanuele Giuseppe Esposito --- python/qemu/machine.py| 2 +- tests/qemu-iotests/iotests.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/py

[PATCH v3 07/15] qemu-iotests: add gdbserver option to script tests too

The only limitation here is that running a script with gdbserver will make the test output mismatch with the expected results, making the test fail. Signed-off-by: Emanuele Giuseppe Esposito --- tests/qemu-iotests/common.rc | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git

Re: [PULL v2 2/3] osdep: protect qemu/osdep.h with extern "C"

On Tue, Apr 13, 2021 at 06:08:49PM +0200, Paolo Bonzini wrote: > System headers may include templates if compiled with a C++ compiler, > which cause the compiler to complain if qemu/osdep.h is included > within a C++ source file's 'extern "C"' block. Add > an 'extern "C"' block directly to qemu/os

[PATCH v3 06/15] qemu_iotests: insert gdbserver command line as wrapper for qemu binary

Signed-off-by: Emanuele Giuseppe Esposito --- tests/qemu-iotests/iotests.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 380527245e..4f3fb13915 100644 --- a/tests/qemu-iotests/iotests.py +++ b/tests/qemu-

[PATCH v3 15/15] docs/devel/testing: add -p option to the debug section of QEMU iotests

Signed-off-by: Emanuele Giuseppe Esposito --- docs/devel/testing.rst | 4 1 file changed, 4 insertions(+) diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst index 62902cfd2d..0c18fc4571 100644 --- a/docs/devel/testing.rst +++ b/docs/devel/testing.rst @@ -246,6 +246,10 @@ given as

[PATCH v3 11/15] qemu_iotests: allow valgrind to read/delete the generated log file

When using -valgrind on the script tests, it generates a log file in $TEST_DIR that is either read (if valgrind finds problems) or otherwise deleted. Provide the same exact behavior when using -valgrind on the python tests. Signed-off-by: Emanuele Giuseppe Esposito --- tests/qemu-iotests/iotests

[PATCH v3 04/15] qemu-iotests: add option to attach gdbserver

Add -gdb flag and GDB_QEMU environmental variable to python tests to attach a gdbserver to each qemu instance. if -gdb is not provided but $GDB_QEMU is set, ignore the environmental variable. Signed-off-by: Emanuele Giuseppe Esposito --- tests/qemu-iotests/check | 6 +- tests/qemu-iot

[PATCH v3 12/15] qemu_iotests: insert valgrind command line as wrapper for qemu binary

The priority will be given to gdb command line, meaning if the -gdb parameter and -valgrind are given, gdb will be wrapped around the qemu binary. Signed-off-by: Emanuele Giuseppe Esposito --- tests/qemu-iotests/iotests.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tes

  1   2   3   4   >