On 3/17/21 7:46 PM, Cédric Le Goater wrote:
> On 3/13/21 1:05 PM, Philippe Mathieu-Daudé wrote:
>> Incorrect subject prefix, should be "hw/ssi/aspeed_smc"
>
> Is this just good practice or something that was agreed upon ?
Not sure, maybe "good practice"? Anyway here I only meant to
correct my
On Apr 16 09:22, Gollu Appalanaidu wrote:
Use lower case hexadecimal format for the constants and in
comments use the same format as used in Spec. ("h")
Signed-off-by: Gollu Appalanaidu
---
-v3: Add Suggestions (Philippe)
Describe the NVMe subsystem style in nvme.c header
-v2: Address
On 4/15/21 11:51 PM, Cleber Rosa wrote:
> These tests' setUp do not do anything beyong what their base class do.
> And while they do decorate the setUp() we can decorate the classes
> instead, so no functionality is lost here.
This is what I did first when adding this test, but it was not
A customer reported that running
qemu-img convert -t none -O qcow2 -f qcow2 input.qcow2 output.qcow2
fails for them with the following error message when the images are
stored on a GPFS file system:
qemu-img: error while writing sector 0: Invalid argument
After analyzing the strace output,
Hi Cleber,
On 4/15/21 11:51 PM, Cleber Rosa wrote:
> Different users (or even companies) have different interests, and
> may want to run a reduced set of tests during development, or a
> larger set of tests during QE.
>
> To cover these use cases, some example (but functional) jobs are
>
On 4/15/21 11:51 PM, Cleber Rosa wrote:
> The test contains methods for the proper log of test related
"The Test class ..."?
> information. Let's use that and remove the print and the unused
> logging import.
>
> Reference:
>
On 4/15/21 11:51 PM, Cleber Rosa wrote:
> FIXME: check if there's a way to query migration support before
> actually requesting migration.
>
> Some targets/machines contain devices that do not support migration.
> Let's acknowledge that and cancel the test as early as possible.
>
>
On Thu, 15 Apr 2021 10:27:42 PDT (-0700), tetra2...@gmail.com wrote:
Hi all,
This patch makes locally used symbols static to enable more compiler
optimizations on them. Some of the symbols turned out to not be used
at all so I marked them with ATTRIBUTE_UNUSED (as I wasn't sure if
they were ok
On 4/15/21 11:51 PM, Cleber Rosa wrote:
> The premise behind the original behavior is that it would save people
> from downloading Avocado (and other dependencies) if already installed
> on the system. To be honest, I think it's extremely rare that the
> same versions described as dependencies
Hi Yuri,
On 4/15/21 7:27 PM, Yuri Gribov wrote:
> Hi all,
>
> This patch makes locally used symbols static to enable more compiler
> optimizations on them. Some of the symbols turned out to not be used
> at all so I marked them with ATTRIBUTE_UNUSED (as I wasn't sure if
> they were ok to
On Sun, Apr 11, 2021 at 5:41 AM Jose Martins wrote:
>
> The wfi exception trigger behavior was not taking into account the fact
> that user mode is not allowed to execute wfi instructions or the effect
> of the hstatus.vtw bit. It was also always generating virtual instruction
> exceptions when
On Tue, Apr 13, 2021 at 04:07:40PM +0800, Yanan Wang wrote:
> From: Andrew Jones
>
> qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
> it also adds any missing subnodes in the path. We also tweak
> an error message of qemu_fdt_add_subnode().
>
> We'll make use of this new function
On Thu, Apr 15, 2021 at 06:33:01PM +0200, Philippe Mathieu-Daudé wrote:
> We might have a s390x/ppc64 QEMU binary built without the KVM
> accelerator (configured with --disable-kvm).
> Checking for /dev/kvm accessibility isn't enough, also check for the
> accelerator in the binary.
>
>
On Thu, Apr 15, 2021 at 09:43:23AM +0200, Cédric Le Goater wrote:
> On 4/15/21 7:42 AM, Nicholas Piggin wrote:
> > This must have slipped through the cracks between adding POWER10 support
> > and scv support.
> >
> > Signed-off-by: Nicholas Piggin
>
> Reviewed-by: Cédric Le Goater
Applied to
On Thu, Apr 15, 2021 at 03:42:27PM +1000, Nicholas Piggin wrote:
> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
> and it removes support for the LPCR[AIL]=0b10 mode.
>
> Reviewed-by: Cédric Le Goater
> Tested-by: Cédric Le Goater
> Signed-off-by: Nicholas Piggin
> ---
On Thu, Apr 15, 2021 at 03:42:26PM +1000, Nicholas Piggin wrote:
> The AIL logic is becoming unmanageable spread all over powerpc_excp(),
> and it is slated to get even worse with POWER10 support.
>
> Move it all to a new helper function.
>
> Reviewed-by: Cédric Le Goater
> Tested-by: Cédric Le
On Thu, Apr 15, 2021 at 09:12:21AM -0300, Fabiano Rosas wrote:
> Nicholas Piggin writes:
>
> > ISA v3.0 radix guest execution has a quirk in AIL behaviour such that
> > the LPCR[AIL] value can apply to hypervisor interrupts.
> >
> > This affects machines that emulate HV=1 mode (i.e., powernv9).
Use lower case hexadecimal format for the constants and in
comments use the same format as used in Spec. ("h")
Signed-off-by: Gollu Appalanaidu
---
-v3: Add Suggestions (Philippe)
Describe the NVMe subsystem style in nvme.c header
-v2: Address review comments (Klaus)
use lower case
On Thu, Apr 15, 2021 at 06:41:36PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> A newer compiler is needed to build tests for Power10 instructions. As
> done for arm64 on c729a99d2701, new '-test-cross' images are created for
> ppc64 and ppc64le. As done on 936fda4d771f,
On Wed, Apr 14, 2021 at 01:09:19PM -0700, Richard Henderson wrote:
> On 4/14/21 7:59 AM, Bruno Larsen (billionai) wrote:
> > All the code related to gdb has been moved from translate_init.c.inc
> > file to the gdbstub.c file, where it makes more sense.
> >
> > This new version puts the prototypes
On Thu, Apr 15, 2021 at 06:41:35PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> Based-on: <20210413211129.457272-1-luis.pi...@eldorado.org.br>
First things first: it's unclear to me if this is testing stuff that's
already merged, or it's speculative tests for the
On 15/04/2021 23.51, Cleber Rosa wrote:
The acceptance jobs (via `make check-venv`) will setup a virtual
environment, and after that install packages defined in
tests/requirements.txt via pip.
Let's enable pip's default cache directory, so that we can save
a bit on time/bandwidth.
Public bug reported:
If FPU is enabled by writing to CPACR, and the code is in the same
translation block as the following VFP code, qemu generates "v7M NOCP
UsageFault".
This can be reproduced with git HEAD (commit
8fe9f1f891eff4e37f82622b7480ee748bf4af74).
The target binary is attached. The
Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
CPUX86State.xmm_regs[] has already been extended to 512bit to support
AVX512.
Also, other qemu level supports for AVX512 registers are there for
years.
But in x86_cpu_dump_state(), still only dump XMM registers no matter
On Thu, Apr 15, 2021 at 07:18:50PM +0200, Klaus Jensen wrote:
On Apr 15 15:13, Philippe Mathieu-Daudé wrote:
On 4/15/21 2:00 PM, Gollu Appalanaidu wrote:
Make uniform hexadecimal numbers format.
Signed-off-by: Gollu Appalanaidu
---
-v2: Address review comments (Klaus)
use lower case hexa
> -Original Message-
> From: Dr. David Alan Gilbert
> Sent: Wednesday, March 24, 2021 6:40 PM
> To: Zhang, Chen
> Cc: Jason Wang ; qemu-dev de...@nongnu.org>; Eric Blake ; Markus Armbruster
> ; Li Zhijian ; Zhang Chen
> ; Lukas Straub
> Subject: Re: [PATCH V4 4/7] hmp-commands: Add
On Wed, Mar 17, 2021 at 07:32:13PM +0300, Andrey Gruzdev wrote:
> This series is a kind of PoC for asynchronous snapshot reverting. This is
> about external snapshots only and doesn't involve block devices. Thus, it's
> mainly intended to be used with the new 'background-snapshot' migration
>
On 4/15/21 3:04 AM, Philippe Mathieu-Daudé wrote:
dma_memory_set() does a DMA barrier, set the address space with
a constant value. The constant value filling code is not specific
to DMA and can be used for AddressSpace. Extract it as a new
helper: address_space_set().
Signed-off-by: Philippe
On Tue, Apr 13, 2021 at 3:44 AM Vijai Kumar K wrote:
>
> Add documentation for Shakti C reference platform.
>
> Signed-off-by: Vijai Kumar K
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> docs/system/riscv/shakti-c.rst | 82 ++
> 1 file changed, 82
On 4/15/21 1:55 PM, Max Filippov wrote:
target/xtensa used to generate an extra EXCP_DEBUG exception before the
first instruction executed after an interrupt or an exception is taken
to allow single-stepping that instruction in the debugger.
This is no longer needed after the following commits:
On 4/15/21 3:04 AM, Philippe Mathieu-Daudé wrote:
From: Laurent Vivier
When the mem_size of the segment is bigger than the file_size,
and if this space doesn't overlap another segment, it needs
to be cleared.
This bug is very similar to the one we had for linux-user,
22d113b52f41 ("linux-user:
From: Matheus Ferst
A newer compiler is needed to build tests for Power10 instructions. As
done for arm64 on c729a99d2701, new '-test-cross' images are created for
ppc64 and ppc64le. As done on 936fda4d771f, a test for compiler support
is added to verify that the toolchain in use has
From: Matheus Ferst
Based-on: <20210413211129.457272-1-luis.pi...@eldorado.org.br>
This series adds gcc-10 based images to enable the build of tests with Power10
instructions. Then two tests for paddi are added:
- The first one checks a weird behavior observed on POWER10 Functional Simulator
From: Matheus Ferst
This test checks that we can correctly load a 33-bit constant and its
two's complement. At least until version 1.1-0, POWER10 Functional
Simulation fails this test, processing the immediate as if it were
32-bits instead of 34, so it's probably something to keep an eye on.
From: Matheus Ferst
This test exercise the R=1 path of paddi implementation using the
extended mnemonic "pla".
Signed-off-by: Matheus Ferst
---
tests/tcg/ppc64/Makefile.target | 3 ++-
tests/tcg/ppc64le/Makefile.target | 3 ++-
tests/tcg/ppc64le/pla.c | 26
On 4/15/21 11:23 AM, Peter Maydell wrote:
SSE-300 currently shares the SSE-200 Property array. This is
bad principally because the default values of the CPU0_FPU
and CPU0_DSP properties disable the FPU and DSP on the CPU.
That is correct for the SSE-300 but not the SSE-200.
Give the SSE-300 its
Different users (or even companies) have different interests, and
may want to run a reduced set of tests during development, or a
larger set of tests during QE.
To cover these use cases, some example (but functional) jobs are
introduced here:
1) acceptance-all-targets.py: runs all arch agnostic
When running tests that are not target specific with various target
binaries, some specific behavior appears. For s390x, when there's no
guest code running, it will produce GUEST_PANICKED events as the
firmware will shutdown the machine.
With this change, no GUEST_PANICKED *event* will be
Because s390x targets it can not currently migrate without a guest
running.
Future work may provide a proper guest, but for now, it's safer to
cancel the test.
Signed-off-by: Cleber Rosa
---
tests/acceptance/migration.py | 6 ++
1 file changed, 6 insertions(+)
diff --git
FIXME: check if there's a way to query migration support before
actually requesting migration.
Some targets/machines contain devices that do not support migration.
Let's acknowledge that and cancel the test as early as possible.
Signed-off-by: Cleber Rosa
---
tests/acceptance/migration.py | 6
The test contains methods for the proper log of test related
information. Let's use that and remove the print and the unused
logging import.
Reference:
https://avocado-framework.readthedocs.io/en/87.0/api/test/avocado.html#avocado.Test.log
Signed-off-by: Cleber Rosa
---
The acceptance jobs (via `make check-venv`) will setup a virtual
environment, and after that install packages defined in
tests/requirements.txt via pip.
Let's enable pip's default cache directory, so that we can save
a bit on time/bandwidth.
Signed-off-by: Cleber Rosa
---
.gitlab-ci.yml | 1 +
Different users (or even companies) have different interests, and
may want to run a reduced set of tests during development, or a
larger set of tests during QE.
To cover these use cases, this introduces some example (but
functional) jobs.
It's expected that some common jobs will come up from
These tests' setUp do not do anything beyong what their base class do.
And while they do decorate the setUp() we can decorate the classes
instead, so no functionality is lost here.
Signed-off-by: Cleber Rosa
---
tests/acceptance/linux_ssh_mips_malta.py | 7 ++-
1 file changed, 2
The premise behind the original behavior is that it would save people
from downloading Avocado (and other dependencies) if already installed
on the system. To be honest, I think it's extremely rare that the
same versions described as dependencies will be available on most
systems. But, the
target/xtensa used to generate an extra EXCP_DEBUG exception before the
first instruction executed after an interrupt or an exception is taken
to allow single-stepping that instruction in the debugger.
This is no longer needed after the following commits:
a7ba744f4082 ("tcg/cpu-exec: precise
On Thu, Apr 15, 2021 at 8:03 AM Peter Maydell wrote:
>
> On Thu, 15 Apr 2021 at 02:24, Max Filippov wrote:
> > I see a few places where target/xtensa may do that. E.g. it does that on
> > entry
> > to an exception handler to allow for debugging its first instruction.
>
> That should now be
On Thu, Apr 15, 2021 at 6:03 AM Ilya Leoshkevich wrote:
>
> tb_gen_code() assumes that tb->size must never be zero, otherwise it
> may produce spurious exceptions. For xtensa this may happen when
> decoding an unknown instruction, when handling a write into the
> CCOUNT or CCOMPARE special
On 4/15/21 8:23 PM, Peter Maydell wrote:
> SSE-300 currently shares the SSE-200 Property array. This is
> bad principally because the default values of the CPU0_FPU
> and CPU0_DSP properties disable the FPU and DSP on the CPU.
> That is correct for the SSE-300 but not the SSE-200.
> Give the
On 4/15/21 8:58 AM, Daniel P. Berrangé wrote:
I spent a while debugging a tricky migration failure today which was
ultimately caused by fdatasync() getting EACCESS. The existing probes
were not sufficient to diagnose this, so I had to resort to GDB. This
improves probes and block error reporting
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> On 06/04/21 13:42, Vitaly Kuznetsov wrote:
> > older machine types are still available (I disable it for <= 5.1 but we
> > can consider disabling it for 5.2 too). The feature is upstream since
> > Linux 5.8, I know that QEMU supports much older
On 4/15/21 6:56 PM, Greg Kurz wrote:
> On Thu, 15 Apr 2021 18:45:45 +0200
> Philippe Mathieu-Daudé wrote:
>
>> On 4/15/21 3:30 PM, Greg Kurz wrote:
>>> On Thu, 15 Apr 2021 14:39:55 +0200
>>> Philippe Mathieu-Daudé wrote:
>>>
On 4/9/21 6:03 PM, Greg Kurz wrote:
> Despite its simple name
Hi all!
Recently I've implemented fast-cancelling of mirror job: do
bdrv_cancel_in_flight() in mirror_cancel().
Now I'm in doubt: is it a correct thing? I heard, that mirror-cancel is a kind
of valid mirror completion..
Looking at documentation:
# Note that if you issue 'block-job-cancel'
The bug fix for the QEMU part of this is
https://patchew.org/QEMU/20210415182353.8173-1-peter.mayd...@linaro.org/
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when
On Thu, 15 Apr 2021 at 19:23, Peter Maydell wrote:
>
> SSE-300 currently shares the SSE-200 Property array. This is
> bad principally because the default values of the CPU0_FPU
> and CPU0_DSP properties disable the FPU and DSP on the CPU.
> That is correct for the SSE-300 but not the SSE-200.
Thanks. This is a bug in the AN547 model -- we were accidentally turning
off the FPU. I'll write a patch.
NB that with that bug fixed your code then hits an UNDEF trying to do:
0x0996: eef7 1a10 vmrs r1, mvfr0
Only A-profile CPUs have MVFR0 accessible via the vmrs instruction. For
QEMU version: 5.1.0
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1924603
Title:
Incorrect feature negotiation for vhost-vdpa netdevice
Status in QEMU:
New
Bug description:
QEMU cmdline:
On Thu, 15 Apr 2021 at 19:13, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Thu, 15 Apr 2021 at 17:25, Alex Bennée wrote:
> >>
> >> By definition a single instruction is capable of being an IO
> >> instruction. This avoids a problem of triggering a cpu_io_recompile on
> >> a
Public bug reported:
QEMU cmdline:
=
./x86_64-softmmu/qemu-system-x86_64 -machine accel=kvm -m 2G -hda
/gautam/centos75_1.qcow2 -name gautam,process=gautam -enable-kvm -netdev
vhost-vdpa,id=mynet0,vhostdev=/dev/vhost-vdpa-0 -device
SSE-300 currently shares the SSE-200 Property array. This is
bad principally because the default values of the CPU0_FPU
and CPU0_DSP properties disable the FPU and DSP on the CPU.
That is correct for the SSE-300 but not the SSE-200.
Give the SSE-300 its own Property array with the correct
SSE-300
Peter Maydell writes:
> On Thu, 15 Apr 2021 at 17:25, Alex Bennée wrote:
>>
>> By definition a single instruction is capable of being an IO
>> instruction. This avoids a problem of triggering a cpu_io_recompile on
>> a non-recorded translation which then fails because it expects
>>
On 4/15/21 9:24 AM, Alex Bennée wrote:
By definition a single instruction is capable of being an IO
instruction. This avoids a problem of triggering a cpu_io_recompile on
a non-recorded translation which then fails because it expects
tcg_tb_lookup() to succeed unconditionally. The normal use
On Thu, 15 Apr 2021 at 17:25, Alex Bennée wrote:
>
> By definition a single instruction is capable of being an IO
> instruction. This avoids a problem of triggering a cpu_io_recompile on
> a non-recorded translation which then fails because it expects
> tcg_tb_lookup() to succeed unconditionally.
Hi all,
This patch makes locally used symbols static to enable more compiler
optimizations on them. Some of the symbols turned out to not be used
at all so I marked them with ATTRIBUTE_UNUSED (as I wasn't sure if
they were ok to delete).
The symbols have been identified with a pet project of
On 4/15/21 5:55 PM, Philippe Mathieu-Daudé wrote:
> On 4/15/21 4:54 PM, Peter Maydell wrote:
>> On Thu, 15 Apr 2021 at 15:32, Alex Bennée wrote:
>>> --8<---cut here---start->8---
>>> accel/tcg: avoid re-translating one-shot instructions
>>>
>>> By definition a
On Thu, Apr 15, 2021 at 5:13 AM Corey Minyard wrote:
>
> On Mon, Apr 12, 2021 at 12:45:18PM -0700, Patrick Venture wrote:
> > The i2c mux device pca954x implements two devices:
> > - the pca9546 and pca9548.
>
> This looks good, I have pulled it into my queue. 6.0 is about to be
> released,
On Thu, Apr 15, 2021 at 05:40:40PM +0100, Daniel P. Berrangé wrote:
> On Thu, Apr 15, 2021 at 12:30:11PM -0400, Eduardo Habkost wrote:
> > On Thu, Apr 15, 2021 at 12:04 PM Daniel P. Berrangé
> > wrote:
> > >
> > > Is it possible to query the migration blockers via QMP ?
> >
> > I don't think it
On Thu, 15 Apr 2021 at 18:18, Cédric Le Goater wrote:
>
> On 4/15/21 5:55 PM, Philippe Mathieu-Daudé wrote:
> > On 4/15/21 4:54 PM, Peter Maydell wrote:
> >> On Thu, 15 Apr 2021 at 15:32, Alex Bennée wrote:
> >>> --8<---cut here---start->8---
> >>> accel/tcg:
On Thu, Apr 15, 2021 at 06:32:59PM +0200, Philippe Mathieu-Daudé wrote:
> Now than we can probe if the TCG accelerator is available
> at runtime with a QMP command, only run these tests if TCG
> is built into the QEMU binary.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Philippe Mathieu-Daudé
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> On Thu, Apr 15, 2021 at 05:44:02PM +0200, Vitaly Kuznetsov wrote:
> > When a migration blocker is added nothing is reported to the user,
> > inability to migrate such guest may come as a late surprise. As a bare
> > minimum, we can print a
Hi Paolo,
Can you specify how to reproduce the issue ? We need more details about
environment.
In my case, everything seems to work fine for the newest version of glib (2.68).
Thank you,
Aleksandar
> qemu/osdep.h is quite special in that, despite being part of QEMU sources,
> it is included
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/translate.c | 3 ++-
target/hexagon/translate.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index
On Apr 15 15:13, Philippe Mathieu-Daudé wrote:
On 4/15/21 2:00 PM, Gollu Appalanaidu wrote:
Make uniform hexadecimal numbers format.
Signed-off-by: Gollu Appalanaidu
---
-v2: Address review comments (Klaus)
use lower case hexa format for the code and in comments
use the same format as used in
On 4/14/21 12:11 PM, Richard Henderson wrote:
This approach seems like it will work fine for MLS and MMIR prefixes. For 8LS,
8RR, and MRR prefixes, we'll need some extra help within ppc_tr_translate_insn.
E.g.
insn = translator_ldl_swap(env, ctx->base.pc_next,
From: Alessandro Di Federico
This commit moves into a separate file routines used to manipulate
TCGCond. These will be employed by the idef-parser.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
include/tcg/tcg-cond.h | 101 +
Command line is
qemu-system-arm -machine mps3-an547 -nographic -kernel test.elf -semihosting
-semihosting-config enable=on,target=native
Binary is attached. It does
int main(int argc, char* argv[])
{
SCB->NSACR |= (3U << 10U);/* enable Non-secure access to
CP10 and CP11
On Thu, Apr 15, 2021 at 06:32:58PM +0200, Philippe Mathieu-Daudé wrote:
> sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm()
> tests are now only being run if KVM is available. Drop the TCG
> fallback.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/genptr.c | 6 --
target/hexagon/macros.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index
On Thu, 15 Apr 2021 18:45:45 +0200
Philippe Mathieu-Daudé wrote:
> On 4/15/21 3:30 PM, Greg Kurz wrote:
> > On Thu, 15 Apr 2021 14:39:55 +0200
> > Philippe Mathieu-Daudé wrote:
> >
> >> On 4/9/21 6:03 PM, Greg Kurz wrote:
> >>> Despite its simple name and common usage of "getting a pointer to
On 4/15/21 3:30 PM, Greg Kurz wrote:
> On Thu, 15 Apr 2021 14:39:55 +0200
> Philippe Mathieu-Daudé wrote:
>
>> On 4/9/21 6:03 PM, Greg Kurz wrote:
>>> Despite its simple name and common usage of "getting a pointer to
>>> the machine" in system-mode emulation, qdev_get_machine() has some
>>>
From: Alessandro Di Federico
Signed-off-by: Alessandro Di Federico
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 36055f14c5..158badbd18 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -193,11 +193,19 @@ Hexagon TCG CPUs
M: Taylor
On Thu, Apr 15, 2021 at 06:32:56PM +0200, Philippe Mathieu-Daudé wrote:
> Use the recently added generic qtest_has_accel() method to
> check if KVM is available.
>
> Suggested-by: Claudio Fontana
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/qtest/arm-cpu-features.c | 25
On Thu, Apr 15, 2021 at 06:32:57PM +0200, Philippe Mathieu-Daudé wrote:
> The sve_tests_sve_off_kvm() test is KVM specific.
> Only run it if KVM is available.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/qtest/arm-cpu-features.c | 4 ++--
> 1 file
From: Alessandro Di Federico
Extend gen_tcg_funcs.py in order to emit calls to the functions emitted
by the idef-parser, if available.
Signed-off-by: Alessandro Di Federico
---
target/hexagon/gen_tcg_funcs.py | 28 ++--
target/hexagon/hex_common.py| 10 ++
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Dr. David Alan Gilbert
> ---
> block/file-posix.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 6aafeda44f..2538e43299 100644
> ---
Since commit 82bf7ae84ce ("target/arm: Remove KVM support for
32-bit Arm hosts") we can remove the comment / check added in
commit ab6b6a4 and directly run the bios-tables-test.
Reviewed-by: Eric Blake
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/meson.build | 3 +--
1 file
On Thu, Apr 15, 2021 at 12:30:11PM -0400, Eduardo Habkost wrote:
> On Thu, Apr 15, 2021 at 12:04 PM Daniel P. Berrangé
> wrote:
> >
> > On Thu, Apr 15, 2021 at 05:44:02PM +0200, Vitaly Kuznetsov wrote:
> > > When a migration blocker is added nothing is reported to the user,
> > > inability to
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/idef-parser/idef-parser.y | 947 +++
target/hexagon/idef-parser/parser-helpers.c | 2374 +
target/hexagon/idef-parser/parser-helpers.h | 347 +++
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/idef-parser/idef-parser.h | 254
target/hexagon/idef-parser/idef-parser.lex| 611 ++
target/hexagon/meson.build| 4 +
We might have a s390x/ppc64 QEMU binary built without the KVM
accelerator (configured with --disable-kvm).
Checking for /dev/kvm accessibility isn't enough, also check for the
accelerator in the binary.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: David Gibson
Cc: Greg Kurz
Cc: Halil Pasic
From: Niccolò Izzo
Signed-off-by: Alessandro Di Federico
Signed-off-by: Niccolò Izzo
---
tests/tcg/hexagon/Makefile.target | 36 -
tests/tcg/hexagon/crt.S| 28 +
tests/tcg/hexagon/test_abs.S | 20 ++
tests/tcg/hexagon/test_add.S |
From: Niccolò Izzo
These helpers will be employed by the idef-parser generated code.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Niccolò Izzo
---
target/hexagon/genptr.c | 188
target/hexagon/genptr.h | 22 +
target/hexagon/macros.h |
From: Alessandro Di Federico
Introduce infrastructure necessary to produce a file suitable for being
parsed by the idef-parser.
Signed-off-by: Alessandro Di Federico
---
target/hexagon/gen_idef_parser_funcs.py | 114 ++
target/hexagon/idef-parser/macros.inc | 150
The sve_tests_sve_off_kvm() test is KVM specific.
Only run it if KVM is available.
Suggested-by: Andrew Jones
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c
From: Paolo Montesel
Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/genptr.c | 7 ---
From: Alessandro Di Federico
This patchset introduces the idef-parser for target/hexagon.
It's the fourth iteration of the patchset and includes fixes suggested
in previous iterations.
`idef-parser` is a build-time tool built using flex and bison. Its aim
is to generate a large part of the
From: Alessandro Di Federico
Signed-off-by: Alessandro Di Federico
---
target/hexagon/README | 5 +
target/hexagon/idef-parser/README.rst | 447 ++
2 files changed, 452 insertions(+)
create mode 100644 target/hexagon/idef-parser/README.rst
diff --git
Use the recently added generic qtest_has_accel() method to
check if KVM is available.
Suggested-by: Claudio Fontana
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git
From: Philippe Mathieu-Daudé
The previous attempt (commit f77147cd4de) doesn't work as
expected, as we still have CONFIG_TCG=1 when using:
configure --disable-system --disable-user
Now than we have removed the use of CONFIG_TCG from target-dependent
files in tests/qtest/, we can remove the
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> A flush failure is a critical failure scenario for some operations.
> For example, it will prevent migration from completing, as it will
> make vm_stop() report an error. Thus it is important to have a
> trace point present for debugging.
>
>
1 - 100 of 251 matches
Mail list logo
