Re: [PATCH v2 4/4] target/ppc: Add POWER10 exception model

Excerpts from David Gibson's message of April 16, 2021 2:28 pm: > On Thu, Apr 15, 2021 at 03:42:27PM +1000, Nicholas Piggin wrote: >> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], >> and it removes support for the LPCR[AIL]=0b10 mode. >> >> Reviewed-by: Cédric Le Goater

Re: [PATCH v2 3/4] target/ppc: Rework AIL logic in interrupt delivery

Excerpts from David Gibson's message of April 16, 2021 2:24 pm: > On Thu, Apr 15, 2021 at 03:42:26PM +1000, Nicholas Piggin wrote: >> The AIL logic is becoming unmanageable spread all over powerpc_excp(), >> and it is slated to get even worse with POWER10 support. >> >> Move it all to a new

Re: [RFC PATCH v2 1/6] device_tree: Add qemu_fdt_add_path

Hi David, On 2021/4/16 12:52, David Gibson wrote: On Tue, Apr 13, 2021 at 04:07:40PM +0800, Yanan Wang wrote: From: Andrew Jones qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it also adds any missing subnodes in the path. We also tweak an error message of

Re: [PATCH v4 16/19] qapi/expr.py: Add docstrings

On 4/14/21 11:04 AM, Markus Armbruster wrote: John Snow writes: Thanks for taking this on. I realize it's a slog. (Update: much later: AUUUGH WHY DID I DECIDE TO WRITE DOCS. MY HUBRIS) Signed-off-by: John Snow --- scripts/qapi/expr.py | 213

[PATCH v1 07/11] target/arm: Implement bfloat16 dot product (indexed)

This is BFDOT for both AArch64 AdvSIMD and SVE, and VDOT.BF16 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 ++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 3 +++ target/arm/translate-a64.c | 41

[PATCH v1 09/11] target/arm: Implement bfloat widening fma (vector)

This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE, and VFMA{B,T}.BF16 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper.h | 3 +++ target/arm/neon-shared.decode | 3 +++ target/arm/sve.decode | 3 +++ target/arm/translate-a64.c | 13

[PATCH v1 04/11] target/arm: Implement vector float32 to bfloat16 conversion

This is BFCVT{N,T} for both AArch64 AdvSIMD and SVE, and VCVT.BF16.F32 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 4 +++ target/arm/helper.h | 1 + target/arm/neon-dp.decode | 1 + target/arm/sve.decode | 2 ++

[PATCH v1 06/11] target/arm: Implement bfloat16 dot product (vector)

This is BFDOT for both AArch64 AdvSIMD and SVE, and VDOT.BF16 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper.h | 3 +++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 3 +++ target/arm/translate-a64.c | 20

[PATCH v1 11/11] target/arm: Enable BFloat16 extensions

Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 3 +++ target/arm/cpu_tcg.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 379f90fab8..db4f48edcf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -660,6 +660,7 @@ static

[PATCH v1 05/11] fpu: Add float_round_to_odd_inf

For Arm BFDOT and BFMMLA, we need a version of round-to-odd that overflows to infinity, instead of the max normal number. Signed-off-by: Richard Henderson --- include/fpu/softfloat-types.h | 4 +++- fpu/softfloat.c | 8 ++-- 2 files changed, 9 insertions(+), 3 deletions(-)

[PATCH v1 08/11] target/arm: Implement bfloat16 matrix multiply accumulate

This is BFMMLA for both AArch64 AdvSIMD and SVE, and VMMLA.BF16 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper.h | 3 +++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 6 +++-- target/arm/translate-a64.c | 10 +

[PATCH v1 03/11] target/arm: Implement scalar float32 to bfloat16 conversion

This is the 64-bit BFCVT and the 32-bit VCVT{B,T}.BF16.F32. Signed-off-by: Richard Henderson --- target/arm/helper.h| 1 + target/arm/vfp.decode | 2 ++ target/arm/translate-a64.c | 19 +++ target/arm/vfp_helper.c| 5 +

[PATCH v1 02/11] target/arm: Unify unallocated path in disas_fp_1src

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 668edf3a00..d8ec219bb2 100644 --- a/target/arm/translate-a64.c +++

[PATCH v1 10/11] target/arm: Implement bfloat widening fma (indexed)

This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE, and VFMA{B,T}.BF16 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 ++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 2 ++ target/arm/translate-a64.c | 15

[PATCH v1 for-6.1 00/11] target/arm: Implement BFloat16

Based-on: 20210416210240.1591291-1-richard.hender...@linaro.org ("[PATCH v5 for-6.1 00/81] target/arm: Implement SVE2") https://gitlab.com/rth7680/qemu/-/tree/tgt-arm-bf16 https://gitlab.com/rth7680/qemu/-/commit/2ecc372b672d11fdc4e2573d789bfb3f5e6cba48 Bfloat16 is a set of 2 tightly-coupled

[PATCH v1 01/11] target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16

Note that the SVE BFLOAT16 support does not require SVE2, it is an independent extension. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 134dc65e34..38db20c721 100644 ---

Re: [PATCH v5 for-6.1 00/81] target/arm: Implement SVE2

Patchew URL: https://patchew.org/QEMU/20210416210240.1591291-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210416210240.1591291-1-richard.hender...@linaro.org Subject: [PATCH v5

[PATCH v5 81/81] target/arm: Enable SVE2 and some extensions

Signed-off-by: Richard Henderson --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 13 + 2 files changed, 14 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0dd623e590..30fd5d5ff7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1464,6 +1464,7 @@

[PATCH v5 76/81] target/arm: Remove unused fpst from VDOT_scalar

Cut and paste error from another pattern. Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 6385d13a7e..c1fbe21ae6 100644 ---

[PATCH v5 72/81] target/arm: Implement SVE2 bitwise shift immediate

From: Stephen Long Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Signed-off-by: Stephen Long Message-Id: <20200430194159.24064-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 33 + target/arm/sve.decode | 5

[PATCH v5 67/81] target/arm: Implement SVE2 FCVTXNT, FCVTX

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-4-stepl...@quicinc.com> [rth: Use do_frint_mode, which avoids a specific runtime helper.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 2 ++ target/arm/translate-sve.c | 49

[PATCH v5 68/81] target/arm: Implement SVE2 FLOGB

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200430191405.21641-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fixed esz index and c++ comments v3: Fixed denormal arithmetic and raise invalid. --- target/arm/helper-sve.h| 4 +++ target/arm/sve.decode

[PATCH v5 59/81] target/arm: Implement SVE mixed sign dot product (indexed)

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.h| 4 +++ target/arm/sve.decode | 4 +++ target/arm/translate-sve.c | 16 + target/arm/vec_helper.c| 68 ++ 5 files changed, 97 insertions(+)

[PATCH v5 78/81] target/arm: Split decode of VSDOT and VUDOT

Now that we have a common helper, sharing decode does not save much. Also, this will solve an upcoming naming problem. Signed-off-by: Richard Henderson --- target/arm/neon-shared.decode | 9 ++--- target/arm/translate-neon.c.inc | 30 ++ 2 files changed, 28

[PATCH v5 66/81] target/arm: Implement SVE2 FCVTLT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 23 +++

[PATCH v5 55/81] target/arm: Implement SVE2 saturating multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 32 4 files changed, 81 insertions(+),

[PATCH v5 80/81] target/arm: Implement integer matrix multiply accumulate

This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE, and V{S,U,US}MMLA.S8 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 +++ target/arm/neon-shared.decode | 7 +++ target/arm/sve.decode | 6 +++ target/arm/translate-a64.c | 18

[PATCH 1/1] spapr_drc.c: handle hotunplug errors in drc_unisolate_logical()

The Linux kernel will call set-indicator to move a DRC to 'unisolate' in the case a device removal fails. Setting a DRC that is already unisolated or configured to 'unisolate' is a no-op for the current hypervisors that supports pSeries guests, namely QEMU and phyp, and is being used to signal

[PATCH v5 70/81] target/arm: Implement SVE2 LD1RO

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 97 ++ 2 files changed, 101 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 17adb393ff..df870ce23b 100644 ---

[PATCH v5 49/81] target/arm: Pass separate addend to FCMLA helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 ++--- target/arm/translate-a64.c | 28 ++

[PATCH 0/1] pSeries: handle hotunplug errors in drc_unisolate_logical()

Hi, This is the QEMU side of a kernel change being proposed in [1], where an attempt to implement a CPU hotunplug error report mechanism was proposed. The idea was discussed first in this mailing list [2], where the RTAS set-indicator call would be used to signal QEMU when a kernel side error

[PATCH v5 63/81] target/arm: Implement SVE2 crypto constructive binary operations

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 3 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 904f5da290..b43fd066ba 100644 ---

[PATCH v5 79/81] target/arm: Implement aarch32 VSUDOT, VUSDOT

Signed-off-by: Richard Henderson --- target/arm/cpu.h| 5 + target/arm/neon-shared.decode | 6 ++ target/arm/translate-neon.c.inc | 27 +++ 3 files changed, 38 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index

[PATCH v5 51/81] target/arm: Split out formats for 3 vectors + 1 index

Used by FMLA and DOT, but will shortly be used more. Split FMLA from FMLS to avoid an extra sub field; similarly for SDOT from UDOT. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 29 +++-- target/arm/translate-sve.c | 38

[PATCH v5 69/81] target/arm: Share table of sve load functions

The table used by do_ldrq is a subset of the table used by do_ld_zpa; we can share them by passing dtype instead of msz to do_ldrq. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 254 ++--- 1 file changed, 126 insertions(+), 128 deletions(-)

[PATCH v5 77/81] target/arm: Fix decode for VDOT (indexed)

We were extracting the M register twice, once incorrectly as M:vm and once correctly as rm. Remove the incorrect name and remove the incorrect decode. Signed-off-by: Richard Henderson --- target/arm/neon-shared.decode | 4 +- target/arm/translate-neon.c.inc | 90

[PATCH v5 46/81] target/arm: Implement SVE2 FMMLA

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200422165503.13511-1-stepl...@quicinc.com> [rth: Fix indexing in helpers, expand macro to straight functions.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ target/arm/helper-sve.h| 3 ++

[PATCH v5 73/81] target/arm: Implement SVE2 fp multiply-add long

From: Stephen Long Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT Signed-off-by: Stephen Long Message-Id: <20200504171240.11220-1-stepl...@quicinc.com> [rth: Rearrange to use float16_to_float32_by_bits.] Signed-off-by: Richard Henderson --- target/arm/helper.h|

[PATCH v5 56/81] target/arm: Implement SVE2 saturating multiply (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 12 target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 19 +++ 4 files changed, 52 insertions(+), 4 deletions(-) diff --git

[PATCH v5 75/81] target/arm: Split out do_neon_ddda_fpst

Split out a helper that can handle the 4-register format for helpers shared with SVE. Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 98 +++-- 1 file changed, 43 insertions(+), 55 deletions(-) diff --git a/target/arm/translate-neon.c.inc

[PATCH v5 43/81] target/arm: Implement SVE2 XAR

In addition, use the same vector generator interface for AdvSIMD. This fixes a bug in which the AdvSIMD insn failed to clear the high bits of the SVE register. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 ++ target/arm/helper.h| 2 +

[PATCH v5 71/81] target/arm: Implement 128-bit ZIP, UZP, TRN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 3 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 29 +-- target/arm/translate-sve.c | 58 ++ 4 files changed, 90 insertions(+), 8 deletions(-) diff

[PATCH v5 62/81] target/arm: Implement SVE2 crypto destructive binary operations

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 38 ++ 3 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index

[PATCH v5 74/81] target/arm: Implement aarch64 SUDOT, USDOT

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/translate-a64.c | 25 + 2 files changed, 30 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b43fd066ba..a0865e224c 100644 --- a/target/arm/cpu.h +++

[PATCH v5 65/81] target/arm: Implement SVE2 FCVTNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-2-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 4 target/arm/sve_helper.c| 20

[PATCH v5 37/81] target/arm: Implement SVE2 complex integer multiply-add

Signed-off-by: Richard Henderson --- v2: Fix do_sqrdmlah_d (laurent desnogues) --- target/arm/helper-sve.h| 18 target/arm/vec_internal.h | 5 + target/arm/sve.decode | 5 + target/arm/sve_helper.c| 42 ++

[PATCH v5 54/81] target/arm: Implement SVE2 saturating multiply-add high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 + target/arm/sve.decode | 8 target/arm/sve_helper.c| 40 ++ target/arm/translate-sve.c | 8 4 files changed, 70 insertions(+) diff --git

[PATCH v5 60/81] target/arm: Implement SVE mixed sign dot product

Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 ++ target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 target/arm/vec_helper.c| 18 ++ 4 files changed, 40 insertions(+) diff --git a/target/arm/helper.h

[PATCH v5 64/81] target/arm: Implement SVE2 TBL, TBX

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428144352.9275-1-stepl...@quicinc.com> [rth: rearrange the macros a little and rebase] Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 5 +++ target/arm/sve_helper.c|

[PATCH v5 53/81] target/arm: Implement SVE2 integer multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 23 +++ 2 files changed, 31 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 65cb0a2206..9bfaf737b7 100644 --- a/target/arm/sve.decode

[PATCH v5 36/81] target/arm: Implement SVE2 integer multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 28 ++ target/arm/sve.decode | 11 ++ target/arm/sve_helper.c| 18 + target/arm/translate-sve.c | 76 ++ 4 files changed, 133 insertions(+) diff --git

[PATCH v5 57/81] target/arm: Implement SVE2 signed saturating doubling multiply high

Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 + target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 18 target/arm/vec_helper.c| 84 ++ 4 files changed, 116 insertions(+) diff --git a/target/arm/helper.h

[PATCH v5 58/81] target/arm: Implement SVE2 saturating multiply high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/sve.decode | 8 target/arm/translate-sve.c | 8 target/arm/vec_helper.c| 88 ++ 4 files changed, 118 insertions(+) diff --git a/target/arm/helper.h

[PATCH v5 48/81] target/arm: Pass separate addend to {U, S}DOT helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- v4: Fix double addition (zhiwei). --- target/arm/helper.h | 20 +++--- target/arm/sve.decode

[PATCH v5 34/81] target/arm: Implement SVE2 saturating multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 14 ++ target/arm/sve_helper.c| 30 + target/arm/translate-sve.c | 54 ++ 4 files changed, 112 insertions(+) diff

[PATCH v5 61/81] target/arm: Implement SVE2 crypto unary operations

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 11 +++ 2 files changed, 17 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 73f1348313..6ab13b2f78 100644 --- a/target/arm/sve.decode +++

[PATCH v5 50/81] target/arm: Split out formats for 2 vectors + 1 index

Currently only used by FMUL, but will shortly be used more. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 04ef38f148..a504b55dad 100644 ---

[PATCH v5 33/81] target/arm: Implement SVE2 MATCH, NMATCH

From: Stephen Long Reviewed-by: Richard Henderson Signed-off-by: Stephen Long Message-Id: <20200415145915.2859-1-stepl...@quicinc.com> [rth: Expanded comment for do_match2] Signed-off-by: Richard Henderson --- v2: Apply esz_mask to input pg to fix output flags. --- target/arm/helper-sve.h

[PATCH v5 41/81] target/arm: Implement SVE2 RSUBHNB, RSUBHNT

From: Stephen Long This completes the section 'SVE2 integer add/subtract narrow high part' Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-5-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix round bit type (laurent desnogues) --- target/arm/helper-sve.h| 8

[PATCH v5 52/81] target/arm: Implement SVE2 integer multiply (indexed)

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 30 ++ 2 files changed, 37 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 74ac72bdbd..65cb0a2206 100644 ---

[PATCH v5 32/81] target/arm: Implement SVE2 bitwise ternary operations

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 6 ++ target/arm/sve.decode | 12 +++ target/arm/sve_helper.c| 50 + target/arm/translate-sve.c | 213 + 4 files changed, 281 insertions(+) diff --git

[PATCH v5 40/81] target/arm: Implement SVE2 SUBHNB, SUBHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-4-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c |

[PATCH v5 44/81] target/arm: Implement SVE2 scatter store insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal store insns. 64-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT1W (vector plus scalar) * STNT1D (vector plus scalar) 32-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) *

[PATCH v5 47/81] target/arm: Implement SVE2 SPLICE, EXT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200423180347.9403-1-stepl...@quicinc.com> [rth: Rename the trans_* functions to *_sve2.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 11 +-- target/arm/translate-sve.c | 35

[PATCH v5 42/81] target/arm: Implement SVE2 HISTCNT, HISTSEG

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200416173109.8856-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix overlap between output and input vectors. v4: Fix histseg counting (zhiwei). --- target/arm/helper-sve.h| 7 ++ target/arm/sve.decode

[PATCH v5 35/81] target/arm: Implement SVE2 saturating multiply-add high

SVE2 has two additional sizes of the operation and unlike NEON, there is no saturation flag. Create new entry points for SVE2 that do not set QC. Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 18

[PATCH v5 27/81] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 +++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 35 ++ target/arm/translate-sve.c | 98 ++ 4 files changed, 153 insertions(+) diff --git

[PATCH v5 31/81] target/arm: Implement SVE2 WHILERW, WHILEWR

Signed-off-by: Richard Henderson --- v2: Fix decodetree typo v3: Fix iteration counts (zhiwei). v4: Update for PREDDESC. --- target/arm/sve.decode | 3 ++ target/arm/translate-sve.c | 67 ++ 2 files changed, 70 insertions(+) diff --git

[PATCH v5 45/81] target/arm: Implement SVE2 gather load insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus

[PATCH v5 38/81] target/arm: Implement SVE2 ADDHNB, ADDHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-2-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 5 + target/arm/sve_helper.c| 36

[PATCH v5 28/81] target/arm: Implement SVE2 UQSHRN, UQRSHRN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 +++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 24 ++ target/arm/translate-sve.c | 93 ++ 4 files changed, 137 insertions(+) diff --git

[PATCH v5 22/81] target/arm: Implement SVE2 bitwise shift and insert

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 5 + target/arm/translate-sve.c | 10 ++ 2 files changed, 15 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index d3c4ec6dd1..695a16551e 100644 --- a/target/arm/sve.decode +++

[PATCH v5 39/81] target/arm: Implement SVE2 RADDHNB, RADDHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix round bit type (laurent desnogues) --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c

[PATCH v5 25/81] target/arm: Implement SVE2 floating-point pairwise

From: Stephen Long Signed-off-by: Stephen Long Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- v2: Load all inputs before writing any output (laurent desnogues) --- target/arm/helper-sve.h| 35 + target/arm/sve.decode | 8 +++

[PATCH v5 26/81] target/arm: Implement SVE2 SHRN, RSHRN

Signed-off-by: Richard Henderson --- v2: Fix typo in gen_shrnb_vec (laurent desnogues) v3: Replace DO_RSHR with an inline function --- target/arm/helper-sve.h| 16 target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 54 - target/arm/translate-sve.c | 160

[PATCH v5 18/81] target/arm: Implement SVE2 complex integer add

Signed-off-by: Richard Henderson --- v2: Fix subtraction ordering (laurent desnogues). --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 9 target/arm/sve_helper.c| 42 ++ target/arm/translate-sve.c | 31

[PATCH v5 30/81] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS

Rename the existing sve_while (less-than) helper to sve_whilel to make room for a new sve_whileg helper for greater-than. Signed-off-by: Richard Henderson --- v2: Use a new helper function to implement this. v4: Update for PREDDESC. --- target/arm/helper-sve.h| 3 +- target/arm/sve.decode

[PATCH v5 23/81] target/arm: Implement SVE2 integer absolute difference and accumulate

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 21 + 2 files changed, 27 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 695a16551e..32b15e4192 100644 --- a/target/arm/sve.decode +++

[PATCH v5 19/81] target/arm: Implement SVE2 integer absolute difference and accumulate long

Signed-off-by: Richard Henderson --- v2: Fix select offsetting and argument order (laurent desnogues). --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 12 + target/arm/sve_helper.c| 23 target/arm/translate-sve.c | 55

[PATCH v5 14/81] target/arm: Implement PMULLB and PMULLT

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ target/arm/helper-sve.h| 1 + target/arm/sve.decode | 2 ++ target/arm/translate-sve.c | 22 ++ target/arm/vec_helper.c| 24 5 files changed, 59

[PATCH v5 29/81] target/arm: Implement SVE2 SQSHRN, SQRSHRN

This completes the section "SVE2 bitwise shift right narrow". Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 ++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 24 + target/arm/translate-sve.c | 105 + 4

[PATCH v5 20/81] target/arm: Implement SVE2 integer add/subtract long with carry

Signed-off-by: Richard Henderson --- v2: Fix sel indexing and argument order (laurent desnogues). --- target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 6 ++ target/arm/sve_helper.c| 34 ++ target/arm/translate-sve.c | 23

[PATCH v5 16/81] target/arm: Implement SVE2 bitwise exclusive-or interleaved

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 5 + target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 19 +++ 4 files changed, 49 insertions(+) diff --git a/target/arm/helper-sve.h

[PATCH v5 17/81] target/arm: Implement SVE2 bitwise permute

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper-sve.h| 15 target/arm/sve.decode | 6 target/arm/sve_helper.c| 73 ++ target/arm/translate-sve.c | 36 +++ 5 files changed,

[PATCH v5 24/81] target/arm: Implement SVE2 saturating extract narrow

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 24 target/arm/sve.decode | 12 ++ target/arm/sve_helper.c| 56 + target/arm/translate-sve.c | 238 + 4 files changed, 330 insertions(+) diff --git

[PATCH v5 09/81] target/arm: Implement SVE2 saturating add/subtract (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 54 +++ target/arm/sve.decode | 11 +++ target/arm/sve_helper.c| 194 ++--- target/arm/translate-sve.c | 7 ++ 4 files changed, 210 insertions(+), 56 deletions(-) diff --git

[PATCH v5 11/81] target/arm: Implement SVE2 integer add/subtract interleaved long

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 4 2 files changed, 10 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index fbfd57b23a..12be0584a8 100644 --- a/target/arm/sve.decode +++

[PATCH v5 10/81] target/arm: Implement SVE2 integer add/subtract long

Signed-off-by: Richard Henderson --- v2: Fix select offsets (laurent desnogues). --- target/arm/helper-sve.h| 24 target/arm/sve.decode | 19 target/arm/sve_helper.c| 43 +++ target/arm/translate-sve.c | 46

[PATCH v5 21/81] target/arm: Implement SVE2 bitwise shift right and accumulate

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 34 ++ 2 files changed, 42 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 79046d81e3..d3c4ec6dd1 100644 ---

[PATCH v5 15/81] target/arm: Implement SVE2 bitwise shift left long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 26 ++ target/arm/translate-sve.c | 159 + 4 files changed, 201 insertions(+) diff --git a/target/arm/helper-sve.h

[PATCH v5 08/81] target/arm: Implement SVE2 integer pairwise arithmetic

Signed-off-by: Richard Henderson --- v2: Load all inputs before writing any output (laurent desnogues) --- target/arm/helper-sve.h| 45 ++ target/arm/sve.decode | 8 target/arm/sve_helper.c| 76 ++

[PATCH v5 06/81] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated)

Signed-off-by: Richard Henderson --- v2: Shift values are always signed (laurent desnogues). --- target/arm/helper-sve.h| 54 ++ target/arm/sve.decode | 17 + target/arm/sve_helper.c| 78 ++

[PATCH v5 13/81] target/arm: Implement SVE2 integer multiply long

Exclude PMULL from this category for the moment. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 15 +++ target/arm/sve.decode | 9 + target/arm/sve_helper.c| 31 +++ target/arm/translate-sve.c | 9 + 4 files

[PATCH v5 12/81] target/arm: Implement SVE2 integer add/subtract wide

Signed-off-by: Richard Henderson --- v2: Fix select offsets (laurent desnogues). --- target/arm/helper-sve.h| 16 target/arm/sve.decode | 12 target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 20

[PATCH v5 05/81] target/arm: Split out saturating/rounding shifts from neon

Split these operations out into a header that can be shared between neon and sve. The "sat" pointer acts both as a boolean for control of saturating behavior and controls the difference in behavior between neon and sve -- QC bit or no QC bit. Widen the shift operand in the new helpers, as the

[PATCH v5 04/81] target/arm: Implement SVE2 integer unary operations (predicated)

Signed-off-by: Richard Henderson --- v2: Fix sqabs, sqneg (laurent desnogues) --- target/arm/helper-sve.h| 13 +++ target/arm/sve.decode | 7 ++ target/arm/sve_helper.c| 29 +++ target/arm/translate-sve.c | 47 ++

[PATCH v5 03/81] target/arm: Implement SVE2 integer pairwise add and accumulate long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 target/arm/sve.decode | 5 + target/arm/sve_helper.c| 44 ++ target/arm/translate-sve.c | 39 + 4 files changed, 102 insertions(+)

[PATCH v5 07/81] target/arm: Implement SVE2 integer halving add/subtract (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 54 ++ target/arm/sve.decode | 11 target/arm/sve_helper.c| 39 +++ target/arm/translate-sve.c | 8 ++ 4 files changed, 112 insertions(+) diff

[PATCH v5 02/81] target/arm: Implement SVE2 Integer Multiply - Unpredicated

For MUL, we can rely on generic support. For SMULH and UMULH, create some trivial helpers. For PMUL, back in a21bb78e5817, we organized helper_gvec_pmul_b in preparation for this use. Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 target/arm/sve.decode | 10

[PATCH v5 for-6.1 00/81] target/arm: Implement SVE2

Based-on: 20210416185959.1520974-1-richard.hender...@linaro.org ("[PATCH v4 for-6.1 00/39] target/arm: enforce alignment") And of course, since I messed up the alignment subject, our tooling isn't going to thread this properly. So: https://gitlab.com/rth7680/qemu/-/tree/tgt-arm-sve2

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