Re: [PATCH qemu v20] spapr: Implement Open Firmware client interface

On 6/7/21 13:05, David Gibson wrote: On Fri, Jun 04, 2021 at 03:50:28PM +0200, BALATON Zoltan wrote: On Fri, 4 Jun 2021, David Gibson wrote: On Sun, May 30, 2021 at 07:33:01PM +0200, BALATON Zoltan wrote: [snip] MorphOS checks the name property of the root node ("/") to decide what platfor

Re: [PATCH qemu v20] spapr: Implement Open Firmware client interface

On 6/8/21 08:54, BALATON Zoltan wrote: On Mon, 7 Jun 2021, David Gibson wrote: On Fri, Jun 04, 2021 at 03:59:22PM +0200, BALATON Zoltan wrote: On Fri, 4 Jun 2021, David Gibson wrote: On Wed, Jun 02, 2021 at 02:29:29PM +0200, BALATON Zoltan wrote: On Wed, 2 Jun 2021, David Gibson wrote: On

Re: [RESEND] Multiple SMMUv3 instances on PCI Bus and PCI Host Bridge

Hi Eric, Thanks for the reply! On Mon, Jun 07, 2021 at 11:19:39AM +0200, Eric Auger wrote: > > So I started to have questions in my mind: > > (1) Can PCI host bridge (PCIE.128) add to a different vSMMU without > > following PCIE.0's SMMU setup? > changes need to be made in hw/arm/virt.c > cr

Re: [PATCH 4/4] aspeed: sonorapass: enable pca954x muxes

On 6/9/21 3:58 AM, Joel Stanley wrote: > On Tue, 8 Jun 2021 at 19:56, Patrick Venture wrote: >> >> On Wed, May 19, 2021 at 10:18 AM Patrick Venture wrote: >>> >>> On Tue, May 18, 2021 at 4:27 PM Joel Stanley wrote: On Tue, 18 May 2021 at 19:41, Patrick Venture wrote: > > Enabl

Re: [PATCH v2 3/3] hw/arm: quanta-q71l add pca954x muxes

On 6/8/21 10:25 PM, Patrick Venture wrote: > Adds the pca954x muxes expected. > > Tested: Booted quanta-q71l image to userspace. > Signed-off-by: Patrick Venture > Reviewed-by: Hao Wu > Reviewed-by: Joel Stanley Reviewed-by: Cédric Le Goater I guess this patchset can go through the arm tree

Re: [PATCH v1 2/5] ui: Add a helper to wait on a dmabuf sync

Hi Gerd, Our goal is to block virtio-gpu driver running on the guest from writing on the buffer that hasn't been completely blitted yet. If we do graphic_hw_gl_block, it will block the next commands from being processed but won't stop the guest fill the scanout buffers and send commands, I think.

Re: [PATCH 4/4] aspeed: sonorapass: enable pca954x muxes

On Tue, 8 Jun 2021 at 19:56, Patrick Venture wrote: > > On Wed, May 19, 2021 at 10:18 AM Patrick Venture wrote: > > > > On Tue, May 18, 2021 at 4:27 PM Joel Stanley wrote: > > > > > > On Tue, 18 May 2021 at 19:41, Patrick Venture wrote: > > > > > > > > Enables the pca954x muxes in the bmc board

Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer

On Wed, Jun 9, 2021 at 7:49 AM Alistair Francis wrote: > > Add support for the Ibex timer. This is used with the RISC-V > mtime/mtimecmp similar to the SiFive CLINT. > > We currently don't support changing the prescale or the timervalue. > > Signed-off-by: Alistair Francis > --- > include/hw/tim

Re: [PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer

On Wed, Jun 9, 2021 at 7:49 AM Alistair Francis wrote: > > Connect the Ibex timer to the OpenTitan machine. The timer can trigger > the RISC-V MIE interrupt as well as a custom device interrupt. > > Signed-off-by: Alistair Francis > --- > include/hw/riscv/opentitan.h | 5 - > hw/riscv/opent

[PATCH] KVM: Fix dirty ring mmap incorrect size due to renaming accident

Found this when I wanted to try the per-vcpu dirty rate series out, then I found that it's not really working and it can quickly hang death a guest. I found strange errors (e.g. guest crash after migration) happens even without the per-vcpu dirty rate series. When merging dirty ring, probably no

Re: [PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH

On 6/7/21 9:57 AM, Peter Maydell wrote: +#define DO_LDAVH(OP, ESIZE, TYPE, H, XCHG, EVENACC, ODDACC, TO128) \ +uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ +void *vm, uint64_t a) \ +{

Re: [PATCH 31/55] include/qemu/int128.h: Add function to create Int128 from int64_t

On 6/7/21 9:57 AM, Peter Maydell wrote: int128_make64() creates an Int128 from an unsigned 64 bit value; add a function int128_makes64() creating an Int128 from a signed 64 bit value. Signed-off-by: Peter Maydell --- include/qemu/int128.h | 10 ++ 1 file changed, 10 insertions(+) Re

Re: [PATCH 30/55] target/arm: Implement MVE VMLSLDAV

On 6/7/21 9:57 AM, Peter Maydell wrote: +static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) +{ +MVEGenDualAccOpFn *fns[4][2] = { static const, otherwise, Reviewed-by: Richard Henderson r~

Re: [PATCH 29/55] target/arm: Implement MVE VMLALDAV

On 6/7/21 9:57 AM, Peter Maydell wrote: +static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) +{ +MVEGenDualAccOpFn *fns[4][2] = { static const, otherwise, Reviewed-by: Richard Henderson r~

Re: [PATCH 29/55] target/arm: Implement MVE VMLALDAV

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VMLALDAV insn, which multiplies pairs of integer elements, accumulating them into a 64-bit result in a pair of general-purpose registers. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 8 +++ target/arm/translate.h

Re: A bug of Monitor Chardev ?

在 2021/6/8 23:37, Daniel P. Berrangé 写道: > On Tue, Jun 08, 2021 at 04:07:30PM +0200, Markus Armbruster wrote: >> "Longpeng (Mike, Cloud Infrastructure Service Product Dept.)" >> writes: >> >>> We find a race during QEMU starting, which would case the QEMU process >>> coredump. >>> >>>

Re: [PATCH 2/4] Python QEMU utils: introduce a generic feature list

On Tue, Jun 8, 2021 at 5:42 PM Wainer dos Santos Moschetta < waine...@redhat.com> wrote: > Hi, > > On 6/8/21 11:09 AM, Cleber Rosa wrote: > > Which can be used to check for any "feature" that is available as a > > QEMU command line option, and that will return its list of available > > options. >

Re: [PATCH 28/55] target/arm: Implement MVE VMULL

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VMULL insn, which multiplies two single width integer elements to produce a double width result. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 14 ++ target/arm/mve.decode | 5 + target/arm/mve_he

[PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer

Add support for the Ibex timer. This is used with the RISC-V mtime/mtimecmp similar to the SiFive CLINT. We currently don't support changing the prescale or the timervalue. Signed-off-by: Alistair Francis --- include/hw/timer/ibex_timer.h | 52 ++ hw/timer/ibex_timer.c | 305 ++

[PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer

Connect the Ibex timer to the OpenTitan machine. The timer can trigger the RISC-V MIE interrupt as well as a custom device interrupt. Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 5 - hw/riscv/opentitan.c | 14 +++--- 2 files changed, 15 insertions(+),

[PATCH v2 1/3] hw/char/ibex_uart: Make the register layout private

We don't need to expose the register layout in the public header, so don't. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- include/hw/char/ibex_uart.h | 37 - hw/char/ibex_uart.c | 37 + 2 files changed,

[PATCH v2 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer

v2: - Address review comments Alistair Francis (3): hw/char/ibex_uart: Make the register layout private hw/timer: Initial commit of Ibex Timer hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer include/hw/char/ibex_uart.h | 37 - include/hw/riscv/opentitan.h | 5 +- incl

Re: [PATCH 27/55] target/arm: Implement MVE VHADD, VHSUB

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement MVE VHADD and VHSUB insns, which perform an addition or subtraction and then halve the result. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 14 ++ target/arm/mve.decode | 5 + target/arm/mve_helper.c

Re: [PATCH 26/55] target/arm: Implement MVE VABD

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VABD insn. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 7 +++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c| 5 + target/arm/translate-mve.c | 2 ++ 4 files changed, 17 insertions(+) Rev

Re: [PATCH 25/55] target/arm: Implement MVE VMAX, VMIN

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VMAX and VMIN insns. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 14 ++ target/arm/mve.decode | 5 + target/arm/mve_helper.c| 14 ++ target/arm/translate-mve.c | 4 4 fil

Re: [PATCH 24/55] target/arm: Implement MVE VRMULH

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VRMULH insn, which performs a rounding multiply and then returns the high half. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 7 +++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c| 22 +++

Re: [PATCH 23/55] target/arm: Implement MVE VMULH

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VMULH insn, which performs a vector multiply and returns the high half of the result. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 7 +++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c| 26 +

Re: [PATCH 22/55] target/arm: Implement MVE VADD, VSUB, VMUL

On 6/7/21 9:57 AM, Peter Maydell wrote: +#define DO_2OP(INSN, FN) \ +static bool trans_##INSN(DisasContext *s, arg_2op *a) \ +{ \ +MVEGenTwoOpFn *fns[] = {\ static const, otherwise, R

Re: [PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR

On 6/7/21 9:57 AM, Peter Maydell wrote: +DO_2OP(vand, 1, uint8_t, H1, DO_AND) +DO_2OP(vbic, 1, uint8_t, H1, DO_BIC) +DO_2OP(vorr, 1, uint8_t, H1, DO_ORR) +DO_2OP(vorn, 1, uint8_t, H1, DO_ORN) +DO_2OP(veor, 1, uint8_t, H1, DO_EOR) Again, logicals should use uint64_t. Otherwise, Reviewed-by: Ric

Re: [PATCH 20/55] target/arm: Implement MVE VDUP

On 6/7/21 9:57 AM, Peter Maydell wrote: +#define DO_VDUP(OP, ESIZE, TYPE, H) \ +void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t val) \ +{ \ +TYPE *d = vd;

[Bug 1323758] Re: Mouse stops working when connected usb-storage-device

I have used rel 7.x 8.x ubuntu 18.04 and see this happening in all of them the original user had it only in ubuntu. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1323758 Title: Mouse stops working

Re: [PATCH 19/55] target/arm: Implement MVE VNEG

On 6/7/21 9:57 AM, Peter Maydell wrote: +#define DO_NEG(N)(-(N)) +#define DO_FNEG(N)((N) ^ ~((__typeof(N))-1 >> 1)) + +DO_1OP(vnegb, 1, int8_t, H1, DO_NEG) +DO_1OP(vnegh, 2, int16_t, H2, DO_NEG) +DO_1OP(vnegw, 4, int32_t, H4, DO_NEG) + +DO_1OP(vfnegh, 2, uint16_t, H2, DO_FNEG) +DO_1OP(vfn

Re: [PATCH 18/55] target/arm: Implement MVE VABS

On 6/7/21 9:57 AM, Peter Maydell wrote: +DO_1OP(vfabsh, 2, uint16_t, H2, DO_FABS) +DO_1OP(vfabss, 4, uint32_t, H4, DO_FABS) Could just as plausibly be done on uint64_t. #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fff)) +MVEGen

Re: [PATCH 17/55] target/arm: Implement MVE VMVN (register)

On 6/7/21 9:57 AM, Peter Maydell wrote: +DO_1OP(vmvn, 1, uint8_t, H1, DO_NOT) This is a logical operation; you might as well perform in uint64_t. Otherwise, Reviewed-by: Richard Henderson r~

Re: [PATCH 16/55] target/arm: Implement MVE VREV16, VREV32, VREV64

On 6/7/21 9:57 AM, Peter Maydell wrote: +static uint64_t mask_to_bytemask8(uint16_t mask) +{ +return mask_to_bytemask4(mask) | +((uint64_t)mask_to_bytemask4(mask >> 4) << 32); +} Again, suggest to share the array from expand_pred_b. +DO_1OP(vrev16b, 2, uint16_t, H2, bswap16) +DO_1

Re: [PATCH 15/55] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations

On 6/7/21 9:57 AM, Peter Maydell wrote: Currently the ARM SVE helper code defines locally some utility functions for swapping 16-bit halfwords within 32-bit or 64-bit values and for swapping 32-bit words within 64-bit values, parallel to the byte-swapping bswap16/32/64 functions. We want these a

Re: [PATCH 14/55] target/arm: Implement MVE VCLS

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VCLS insn. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h| 4 target/arm/mve.decode | 1 + target/arm/mve_helper.c| 7 +++ target/arm/translate-mve.c | 1 + 4 files changed, 13 insertions(+) Reviewe

Re: [PATCH 13/55] target/arm: Implement MVE VCLZ

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE VCLZ insn (and the necessary machinery for MVE 1-input vector ops). Note that for non-load instructions predication is always performed at a byte level granularity regardless of element size (R_ZLSJ), and so the masking logic here differs

Re: [PATCH 12/55] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns

On 6/7/21 9:57 AM, Peter Maydell wrote: +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ +static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ +{ \ +MVEGenLdStFn *ldfns[] =

Re: [PATCH 11/55] target/arm: Implement MVE VLDR/VSTR (non-widening forms)

On 6/8/21 2:33 PM, Richard Henderson wrote: +static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) +{ +    MVEGenLdStFn *ldfns[] = { static MVEGenLdStFn * const ldfns +    MVEGenLdStFn *stfns[] = { Likewise, though... +    return do_ldst(s, a, a->l ? ldfns[a->size] : stfns[a->s

Re: [PATCH 2/4] Python QEMU utils: introduce a generic feature list

Hi, On 6/8/21 11:09 AM, Cleber Rosa wrote: Which can be used to check for any "feature" that is available as a QEMU command line option, and that will return its list of available options. This is a generalization of the list_accel() utility function, which is itself re-implemented in terms of

RE: [PATCH v1 3/5] ui/egl: Add egl helpers to help with synchronization

Hi Gerd, > > +epoxy_has_egl_extension(qemu_egl_display, > > +"EGL_ANDROID_native_fence_sync")) { > > What about non-android? Is the name there just for historical reasons? > Or do we actually need something else for desktop systems? [Kasireddy, Vivek] It

Re: [PATCH 11/55] target/arm: Implement MVE VLDR/VSTR (non-widening forms)

On 6/7/21 9:57 AM, Peter Maydell wrote: +static uint16_t mve_element_mask(CPUARMState *env) +{ +/* + * Return the mask of which elements in the MVE vector should be + * updated. This is a combination of multiple things: + * (1) by default, we update every lane in the vector +

Re: [PATCH] Add Connor Kuehl as reviewer for AMD SEV

On 6/8/21 3:45 PM, Daniel P. Berrangé wrote: >> Right, I am just worried that if I am the only person that shows up in >> the get_maintainer.pl output, the submitter will have to know some other >> way who a relevant maintainer is that can take the patches otherwise >> they won't be CC'd. Or we'll

Re: [PATCH] Add Connor Kuehl as reviewer for AMD SEV

On 6/8/21 2:34 PM, Dr. David Alan Gilbert wrote: >> Note: because there's no maintainer entry, when running >> ./scripts/get_maintainers.pl on target/i386/sev.c, my name and the qemu >> mailing list is the only thing that shows up... it doesn't even show >> previous committers (as it would before a

Re: [PATCH] Add Connor Kuehl as reviewer for AMD SEV

On Tue, Jun 08, 2021 at 03:32:54PM -0500, Connor Kuehl wrote: > On 6/8/21 3:10 PM, Daniel P. Berrangé wrote: > > On Tue, Jun 08, 2021 at 02:25:37PM -0500, Connor Kuehl wrote: > >> It may not be appropriate for me to take over as a maintainer at this time, > >> but I would consider myself familiar w

Re: [PATCH] qemu-{img,nbd}: Don't report zeroed cluster as a hole

On Tue, Jun 8, 2021 at 9:46 PM Eric Blake wrote: > > On Tue, Jun 08, 2021 at 07:38:10PM +0300, Nir Soffer wrote: > > On Tue, Jun 8, 2021 at 12:22 AM Eric Blake wrote: > > > > > > On Mon, Jun 07, 2021 at 11:22:04PM +0300, Nir Soffer wrote: > > > > When zeroing a cluster in an image with backing fi

Re: [PATCH] tests/unit/test-char.c: Fix error handling issues

On Tue, Jun 08, 2021 at 11:51:35PM +0400, Marc-André Lureau wrote: > Hi > > On Tue, Jun 8, 2021 at 9:06 PM Peter Maydell > wrote: > > > Coverity spots some minor error-handling issues in this test code. > > These are mostly due to the test code assuming that the glib test > > macros g_assert_cmp

Re: [PULL 0/2] Libslirp patches

Hi On Tue, Jun 8, 2021 at 8:55 PM Peter Maydell wrote: > On Tue, 8 Jun 2021 at 16:55, Marc-André Lureau > wrote: > > > > Hi > > > > On Mon, Jun 7, 2021 at 4:17 PM Peter Maydell > wrote: > > >> >> clang sanitizer build: link failure: > >> >> subprojects/libslirp/libslirp.so.0.3.0.p/src_arp_tabl

Re: [PATCH] tests/unit/test-char.c: Fix error handling issues

On Tue, Jun 08, 2021 at 06:06:06PM +0100, Peter Maydell wrote: > Coverity spots some minor error-handling issues in this test code. > These are mostly due to the test code assuming that the glib test > macros g_assert_cmpint() and friends will always abort on failure. > This is not the case: if the

Re: [PATCH] Add Connor Kuehl as reviewer for AMD SEV

On 6/8/21 3:10 PM, Daniel P. Berrangé wrote: > On Tue, Jun 08, 2021 at 02:25:37PM -0500, Connor Kuehl wrote: >> It may not be appropriate for me to take over as a maintainer at this time, >> but I would consider myself familiar with AMD SEV and what this code is >> meant to be doing as part of a VM

[PATCH v2 3/3] hw/arm: quanta-q71l add pca954x muxes

Adds the pca954x muxes expected. Tested: Booted quanta-q71l image to userspace. Signed-off-by: Patrick Venture Reviewed-by: Hao Wu Reviewed-by: Joel Stanley --- hw/arm/Kconfig | 1 + hw/arm/aspeed.c | 11 --- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/arm/Kconf

[PATCH v2 2/3] hw/arm: gsj add pca9548

Tested: Quanta-gsj firmware booted. i2c /dev entries driver I2C init bus 1 freq 10 I2C init bus 2 freq 10 I2C init bus 3 freq 10 I2C init bus 4 freq 10 I2C init bus 8 freq 10 I2C init bus 9 freq 10 at24 9-0055: 8192 byte 24c64 EEPROM, writable, 1 bytes/write I2C init bus 10

[PATCH v2 1/3] hw/arm: gsj add i2c comments

Adds comments to the board init to identify missing i2c devices. Signed-off-by: Patrick Venture Reviewed-by: Hao Wu Reviewed-by: Joel Stanley --- hw/arm/npcm7xx_boards.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7x

[PATCH v2 0/3] With the pca954x i2c mux available, enable it on aspeed and nuvoton BMC boards.

v2: - Dropped sonorapass patch. Patrick Venture (3): hw/arm: gsj add i2c comments hw/arm: gsj add pca9548 hw/arm: quanta-q71l add pca954x muxes hw/arm/Kconfig | 2 ++ hw/arm/aspeed.c | 11 --- hw/arm/npcm7xx_boards.c | 14 +- 3 files changed, 23 insert

Re: [PATCH 05/26] configure, meson: convert pam detection to meson

On Tue, Jun 08, 2021 at 12:45:51PM -0700, Richard Henderson wrote: > On 6/8/21 4:22 AM, Paolo Bonzini wrote: > > +pam = not_found > > +if not get_option('auth_pam').auto() or have_system > > + pam = cc.find_library('pam', has_headers: ['security/pam_appl.h'], > > The condition doesn't look right.

Re: [PATCH] tests/unit/test-char.c: Fix error handling issues

On Tue, 8 Jun 2021 at 20:51, Marc-André Lureau wrote: > > Hi > > On Tue, Jun 8, 2021 at 9:06 PM Peter Maydell wrote: >> I think that improving the quality of the failure reporting >> in 'make check' is useful, and that we should probably turn >> on g_test_set_nonfatal_assertions() everywhere. (Th

Re: [PATCH] Add Connor Kuehl as reviewer for AMD SEV

On Tue, Jun 08, 2021 at 02:25:37PM -0500, Connor Kuehl wrote: > It may not be appropriate for me to take over as a maintainer at this time, > but I would consider myself familiar with AMD SEV and what this code is > meant to be doing as part of a VMM for launching SEV-protected guests. > > To that

Re: [PATCH 4/4] aspeed: sonorapass: enable pca954x muxes

On Wed, May 19, 2021 at 10:18 AM Patrick Venture wrote: > > On Tue, May 18, 2021 at 4:27 PM Joel Stanley wrote: > > > > On Tue, 18 May 2021 at 19:41, Patrick Venture wrote: > > > > > > Enables the pca954x muxes in the bmc board configuration. > > > > > > Signed-off-by: Patrick Venture > > > Rev

Re: [PATCH] tests/unit/test-char.c: Fix error handling issues

Hi On Tue, Jun 8, 2021 at 9:06 PM Peter Maydell wrote: > Coverity spots some minor error-handling issues in this test code. > These are mostly due to the test code assuming that the glib test > macros g_assert_cmpint() and friends will always abort on failure. > This is not the case: if the test

Re: [PATCH 05/26] configure, meson: convert pam detection to meson

On 6/8/21 12:45 PM, Richard Henderson wrote: On 6/8/21 4:22 AM, Paolo Bonzini wrote: +pam = not_found +if not get_option('auth_pam').auto() or have_system +  pam = cc.find_library('pam', has_headers: ['security/pam_appl.h'], The condition doesn't look right. Why are we looking for pam if --dis

Re: [PATCH 05/26] configure, meson: convert pam detection to meson

On 6/8/21 4:22 AM, Paolo Bonzini wrote: +pam = not_found +if not get_option('auth_pam').auto() or have_system + pam = cc.find_library('pam', has_headers: ['security/pam_appl.h'], The condition doesn't look right. Why are we looking for pam if --disable-pam-auth? Surely if not get_option('a

[PATCH v2 2/2] hw/arm: quanta-gbs-bmc add i2c comments

Add a comment and i2c method that describes the board layout. Tested: firmware booted to userspace. Signed-off-by: Patrick Venture Reviewed-by: Brandon Kim Reviewed-by: Hao Wu --- hw/arm/npcm7xx_boards.c | 60 + 1 file changed, 60 insertions(+) diff --g

[PATCH v2 1/2] hw/arm: add quanta-gbs-bmc machine

Adds initial quanta-gbs-bmc machine support. Tested: Boots to userspace. Signed-off-by: Patrick Venture Reviewed-by: Brandon Kim Reviewed-by: Hao Wu --- hw/arm/npcm7xx_boards.c | 33 + 1 file changed, 33 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/a

Re: [PATCH] hmp: Add "calc_dirty_rate" and "info dirty_rate" cmds

* Peter Xu (pet...@redhat.com) wrote: > On Tue, Jun 08, 2021 at 07:49:56PM +0100, Dr. David Alan Gilbert wrote: > > * Peter Xu (pet...@redhat.com) wrote: > > > These two commands are missing when adding the QMP sister commands. Add > > > them, > > > so developers can play with them easier. > > >

[PATCH v2 0/2] Adds quanta-gbs-bmc machine to nuvoton boards.

This is a board supported by OpenBmc. v2: - Fixed missing hyphen in Cortex name and dropped TODO on hardware strap value. Patrick Venture (2): hw/arm: add quanta-gbs-bmc machine hw/arm: quanta-gbs-bmc add i2c comments hw/arm/npcm7xx_boards.c | 93 + 1

Re: [PATCH] Add Connor Kuehl as reviewer for AMD SEV

* Connor Kuehl (cku...@redhat.com) wrote: > It may not be appropriate for me to take over as a maintainer at this time, > but I would consider myself familiar with AMD SEV and what this code is > meant to be doing as part of a VMM for launching SEV-protected guests. > > To that end, I would be hap

Re: [PATCH 04/26] configure, meson: convert libtasn1 detection to meson

On 6/8/21 4:22 AM, Paolo Bonzini wrote: Make it depend on gnutls too, since it is only used as part of gnutls tests. Signed-off-by: Paolo Bonzini --- configure | 19 --- meson.build| 9 + tests/unit/meson.build | 2 +- 3 files changed, 6 in

Re: [PATCH] Add Connor Kuehl as reviewer for AMD SEV

On 6/8/21 2:25 PM, Connor Kuehl wrote: > It may not be appropriate for me to take over as a maintainer at this time, > but I would consider myself familiar with AMD SEV and what this code is > meant to be doing as part of a VMM for launching SEV-protected guests. > > To that end, I would be happy

[PATCH] Add Connor Kuehl as reviewer for AMD SEV

It may not be appropriate for me to take over as a maintainer at this time, but I would consider myself familiar with AMD SEV and what this code is meant to be doing as part of a VMM for launching SEV-protected guests. To that end, I would be happy to volunteer as a reviewer for SEV-related change

[PATCH v1 1/1] vfio/migration: Correct device state from vmstate change for savevm case.

Set _SAVING flag for device state from vmstate change handler when it gets called from savevm. Currently State transition savevm/suspend is seen as: _RUNNING -> _STOP -> Stop-and-copy -> _STOP State transition savevm/suspend should be: _RUNNING -> Stop-and-copy -> _STOP State transition

Re: [PATCH v3 16/33] nbd/client-connection: add possibility of negotiation

12.05.2021 09:42, Vladimir Sementsov-Ogievskiy wrote: 11.05.2021 13:45, Roman Kagan wrote: On Fri, Apr 16, 2021 at 11:08:54AM +0300, Vladimir Sementsov-Ogievskiy wrote: Add arguments and logic to support nbd negotiation in the same thread after successful connection. Signed-off-by: Vladimir Se

Re: [PATCH] hmp: Add "calc_dirty_rate" and "info dirty_rate" cmds

On Tue, Jun 08, 2021 at 07:49:56PM +0100, Dr. David Alan Gilbert wrote: > * Peter Xu (pet...@redhat.com) wrote: > > These two commands are missing when adding the QMP sister commands. Add > > them, > > so developers can play with them easier. > > > > Cc: Dr. David Alan Gilbert > > Cc: Juan Quin

Re: [PATCH 03/26] configure, meson: convert crypto detection to meson

On 6/8/21 4:22 AM, Paolo Bonzini wrote: Signed-off-by: Paolo Bonzini --- configure | 188 +++-- crypto/meson.build | 41 +++-- meson.build| 81 +- meson_options.txt | 6 ++ tests/unit/meson.build |

Re: [PATCH v4 1/7] file-posix: fix max_iov for /dev/sg devices

08.06.2021 16:16, Paolo Bonzini wrote: Even though it was only called for devices that have bs->sg set (which must be character devices), sg_get_max_segments looked at /sys/dev/block which only works for block devices. On Linux the sg driver has its own way to provide the maximum number of iovec

RE: [PATCH v3] docs/devel: Explain in more detail the TB chaining mechanisms

From: Luis Pires > Signed-off-by: Luis Pires > --- > v3: > - Dropped "most common" from the sentence introducing the chaining > mechanisms > - Changed wording about using the TB address returned by exit_tb > > v2: > - s/outer execution loop/main loop > - Mention re-evaluation of cpu_exec_int

Re: [PATCH] blockdev: fix drive-backup transaction endless drained section

On Tue, Jun 08, 2021 at 08:18:52PM +0300, Vladimir Sementsov-Ogievskiy wrote: > drive_backup_prepare() does bdrv_drained_begin() in hope that > bdrv_drained_end() will be called in drive_backup_clean(). Still we > need to set state->bs for this to work. That's done too late: a lot of > failure path

Re: [PATCH v6 4/4] Jobs based on custom runners: add job definitions for QEMU's machines

Hi, On 6/8/21 10:36 AM, Cleber Rosa Junior wrote: On Tue, Jun 8, 2021 at 2:30 AM Philippe Mathieu-Daudé > wrote: Hi Alex, Stefan, On 6/8/21 5:14 AM, Cleber Rosa wrote: > The QEMU project has two machines (aarch64 and s390x) that can be used > for

Re: [PATCH v3 2/7] hmp: Add "calc_dirty_rate" and "info dirty_rate" cmds

* huang...@chinatelecom.cn (huang...@chinatelecom.cn) wrote: > From: Peter Xu > > These two commands are missing when adding the QMP sister commands. > Add them, so developers can play with them easier. > > Signed-off-by: Peter Xu > Signed-off-by: Hyman Huang(黄勇) I've queued 1 and 2 (with a l

Re: [PATCH v6 3/4] Jobs based on custom runners: docs and gitlab-runner setup playbook

Hi, On 6/8/21 12:14 AM, Cleber Rosa wrote: To have the jobs dispatched to custom runners, gitlab-runner must be installed, active as a service and properly configured. The variables file and playbook introduced here should help with those steps. The playbook introduced here covers the Linux di

Re: [PATCH v3 2/7] hmp: Add "calc_dirty_rate" and "info dirty_rate" cmds

* huang...@chinatelecom.cn (huang...@chinatelecom.cn) wrote: > From: Peter Xu > > These two commands are missing when adding the QMP sister commands. > Add them, so developers can play with them easier. > > Signed-off-by: Peter Xu > Signed-off-by: Hyman Huang(黄勇) Reviewed-by: Dr. David Alan

Re: [PATCH v3 1/7] migration/dirtyrate: make sample page count configurable

* Eric Blake (ebl...@redhat.com) wrote: > On Mon, Jun 07, 2021 at 09:11:34AM +0800, huang...@chinatelecom.cn wrote: > > From: Hyman Huang(黄勇) > > > > introduce optional sample-pages argument in calc-dirty-rate, > > making sample page count per GB configurable so that more > > accurate dirtyrate c

Re: [PATCH] hmp: Add "calc_dirty_rate" and "info dirty_rate" cmds

* Peter Xu (pet...@redhat.com) wrote: > These two commands are missing when adding the QMP sister commands. Add them, > so developers can play with them easier. > > Cc: Dr. David Alan Gilbert > Cc: Juan Quintela > Cc: Leonardo Bras Soares Passos > Cc: Chuan Zheng > Cc: huang...@chinatelecom.c

Re: [PATCH v6 2/4] Jobs based on custom runners: build environment docs and playbook

Hi, On 6/8/21 12:14 AM, Cleber Rosa wrote: To run basic jobs on custom runners, the environment needs to be properly set up. The most common requirement is having the right packages installed. The playbook introduced here covers the QEMU's project s390x and aarch64 machines. At the time this

Re: [PATCH] qemu-{img,nbd}: Don't report zeroed cluster as a hole

On Tue, Jun 08, 2021 at 07:38:10PM +0300, Nir Soffer wrote: > On Tue, Jun 8, 2021 at 12:22 AM Eric Blake wrote: > > > > On Mon, Jun 07, 2021 at 11:22:04PM +0300, Nir Soffer wrote: > > > When zeroing a cluster in an image with backing file, qemu-img and > > > qemu-nbd reported the area as a hole. T

Re: [PATCH v3 06/33] util/async: aio_co_schedule(): support reschedule in same ctx

14.05.2021 00:04, Paolo Bonzini wrote: On 12/05/21 09:15, Vladimir Sementsov-Ogievskiy wrote: I don't understand.  Why doesn't aio_co_enter go through the ctx != qemu_get_current_aio_context() branch and just do aio_co_schedule? That was at least the idea behind aio_co_wake and aio_co_enter

Re: [RFC PATCH] target/ppc: fix address translation bug for hash table mmus

On 08/06/2021 13:37, Bruno Piazera Larsen wrote: On 08/06/2021 12:35, Richard Henderson wrote: On 6/8/21 7:39 AM, Bruno Piazera Larsen wrote: That's odd.  We already have more arguments than the number of argument registers...  A 5x slowdown is distinctly odd. I did some more digging and the

Re: [PATCH v2 0/5] mptcp support

* Dr. David Alan Gilbert (git) (dgilb...@redhat.com) wrote: > From: "Dr. David Alan Gilbert" > > Hi, > This set adds support for multipath TCP (mptcp), and has > been tested for migration and (lightly) for NBD. > > Multipath-tcp is a bit like bonding, but at L3; you can use > it to handle fa

Re: [PATCH v6 1/4] Jobs based on custom runners: documentation and configuration placeholder

On 6/8/21 12:14 AM, Cleber Rosa wrote: As described in the included documentation, the "custom runner" jobs extend the GitLab CI jobs already in place. One of their primary goals of catching and preventing regressions on a wider number of host systems than the ones provided by GitLab's shared

Re: [PATCH v6 4/4] Jobs based on custom runners: add job definitions for QEMU's machines

Hi, On 6/8/21 12:14 AM, Cleber Rosa wrote: The QEMU project has two machines (aarch64 and s390x) that can be used for jobs that do build and run tests. This introduces those jobs, which are a mapping of custom scripts used for the same purpose. Signed-off-by: Cleber Rosa --- .gitlab-ci.d/cu

Re: [PATCH] migration/rdma: Fix cm event use after free

* Dr. David Alan Gilbert (dgilb...@redhat.com) wrote: > * Li Zhijian (lizhij...@cn.fujitsu.com) wrote: > > Signed-off-by: Li Zhijian > > Thanks! I don't think I understood that 'ack' actually meant 'free'! > > Reviewed-by: Dr. David Alan Gilbert Queued > > > --- > > migration/rdma.c | 11 ++

Re: [PATCH v4 4/7] file-posix: try BLKSECTGET on block devices too, do not round to power of 2

On Tue, Jun 08, 2021 at 03:16:31PM +0200, Paolo Bonzini wrote: > bs->sg is only true for character devices, but block devices can also > be used with scsi-block and scsi-generic. Unfortunately BLKSECTGET > returns bytes in an int for /dev/sgN devices, and sectors in a short > for block devices, so

Re: [PATCH v3 1/1] yank: Unregister function when using TLS migration

* Leonardo Bras (leobra...@gmail.com) wrote: > After yank feature was introduced in migration, whenever migration > is started using TLS, the following error happens in both source and > destination hosts: > > (qemu) qemu-kvm: ../util/yank.c:107: yank_unregister_instance: > Assertion `QLIST_EMPTY(

Re: [PATCH v3 0/4] target/i386/cpu: introduce new CPU models for x86-64 ABI levels

On Mon, Jun 07, 2021 at 06:33:10PM -0300, Eduardo Habkost wrote: > On Mon, Jun 07, 2021 at 02:58:39PM +0100, Daniel P. Berrangé wrote: > > This series is motivated by this blog that describes how RHEL-9 > > will recommend use of the x86-64-v2 microarchitectural ABI level: > > > > > > https://de

Re: [PATCH v4 3/7] block: add max_hw_transfer to BlockLimits

On Tue, Jun 08, 2021 at 03:16:30PM +0200, Paolo Bonzini wrote: > For block host devices, I/O can happen through either the kernel file > descriptor I/O system calls (preadv/pwritev, io_submit, io_uring) > or the SCSI passthrough ioctl SG_IO. > > In the latter case, the size of each transfer can be

Re: [PATCH v4 2/7] scsi-generic: pass max_segments via max_iov field in BlockLimits

On Tue, Jun 08, 2021 at 03:16:29PM +0200, Paolo Bonzini wrote: > I/O to a disk via read/write is not limited by the number of segments allowed > by the host adapter; the kernel can split requests if needed, and the limit > imposed by the host adapter can be very low (256k or so) to avoid that SG_IO

RE: [RFC] Adding the A64FX's HPC funtions.

Hi, peter. Thank you for your comment. > I think it would be worth scoping out how much work the a64fx CPU would > require (ie what else does it need beyond these extensions and whatever > features we currently implement?). If that's not a lot of work it might be > simpler > to just add it (poss

RE: [RFC] Adding the A64FX's HPC funtions.

Hi, Richard. > Well, Peter disagreed with having them enabled by default in -cpu max, so we > might need at least one extra property. I see no reason to have three > properties -- one property a64fx-hpc should be sufficient. But we might not > want any command-line properties, see below... I un

Re: [PATCH 02/26] configure: drop unused variables for xts

On 6/8/21 4:22 AM, Paolo Bonzini wrote: All XTS configuration uses qemu_private_xts. Drop other variables as they have only ever been used to generate the summary (which has since been moved to meson.build). Signed-off-by: Paolo Bonzini --- configure | 4 1 file changed, 4 deletions(-)

RE: [RFC] Adding the A64FX's HPC funtions.

Hi, Richard. Thank you for your comment. > My first thought is that -cpu max can simply enable the extensions, without > extra flags. The max cpu has all of the features that we can enable, and as I > see it this is just one more. Let me confirm a few things about the above comment. Does it mea

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