From: Hyman Huang(黄勇)
the dirtyrate measurement implemented by page-sampling originally, it
is not accurate in some scenarios, so we have introduced dirty-ring
based dirtyrate measurement(maybe it will be merged soon), it fix the
accuracy of page-sampling, and more importantly, it is at the
From: Hyman Huang(黄勇)
introduce dirty-bitmap mode as the third method of calc-dirty-rate.
implement dirty-bitmap dirtyrate calculation, which can be used
to measuring dirtyrate in the absence of dirty-ring.
introduce "dirty_bitmap:-b" option in hmp calc_dirty_rate to
indicate dirty bitmap
From: Hyman Huang(黄勇)
introduce kvm_get_manual_dirty_log_protect for measureing
dirtyrate via dirty bitmap. calculation of dirtyrate need
to sync dirty log and depends on the features of dirty log.
Signed-off-by: Hyman Huang(黄勇)
---
accel/kvm/kvm-all.c | 6 ++
include/sysemu/kvm.h | 1 +
From: Hyman Huang(黄勇)
introduce util functions to setup the DIRTY_MEMORY_DIRTY_RATE
dirty bits for the convenience of tracking dirty bitmap when
calculating dirtyrate.
Signed-off-by: Hyman Huang(黄勇)
---
include/exec/ram_addr.h | 121
From: Hyman Huang(黄勇)
intrduce DIRTY_MEMORY_DIRTY_RATE dirty bits to tracking vm
dirty page for calculating dirty rate
since dirtyrate and migration may be trigger concurrently,
reusing the exsiting DIRTY_MEMORY_MIGRATION dirty bits seems
not a good choice. introduce a fresh new dirty bits for
Hi folks,
I found this bug by my dwc2 fuzzer.
It seems that
* https://bugs.launchpad.net/qemu/+bug/1907042
* https://bugs.launchpad.net/qemu/+bug/1525123
or
* https://gitlab.com/qemu-project/qemu/-/issues/119
* https://gitlab.com/qemu-project/qemu/-/issues/303
have reported similar issues.
Would
When eptype is USB_ENDPOINT_XFER_CONTROL and pid is
TSIZ_SC_MC_PID_SETUP, usb_ep_get() should return the control endpoint.
In hw/usb/core.c, the assumed epnum of the control endpoint is 0. When
epnum is not 0, usb_ep_get() will crash due to the check assert(pid ==
USB_TOKEN_IN || pid ==
On 6/25/21 11:02 PM, Nolan Leake wrote:
> This is just enough to make reboot and poweroff work. Works for
> linux, u-boot, and the arm trusted firmware. Not tested, but should
> work for plan9, and bare-metal/hobby OSes, since they seem to generally
> do what linux does for reset.
>
> The
LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道：
> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field
> for the threshold level of the associated privilege mode.
>
> For horizontal interrupts, only the ones with higher interrupt levels
> than the threshold level are allowed to preempt.
>
>
Frank Chang 於 2021年6月27日 週日 上午1:15寫道：
> LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
>
>> The Core-Local Interrupt Controller (CLIC) provides low-latency,
>> vectored, pre-emptive interrupts for RISC-V systems.
>>
>> The CLIC also supports a new Selective Hardware Vectoring feature
>> that allow users
LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for either faster
>
On Mon, Jun 21, 2021 at 10:49 AM Peter Lieven wrote:
>
> Am 18.06.21 um 12:34 schrieb Ilya Dryomov:
> > On Fri, Jun 18, 2021 at 11:00 AM Peter Lieven wrote:
> >> Am 16.06.21 um 14:34 schrieb Ilya Dryomov:
> >>> On Wed, May 19, 2021 at 4:28 PM Peter Lieven wrote:
> Signed-off-by: Peter
LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道：
> The machine mode mclicbase CSR is an XLEN-bit read-only register providing
> the base address of CLIC memory mapped registers.
>
> Signed-off-by: LIU Zhiwei
> ---
> hw/intc/riscv_clic.c | 1 +
> target/riscv/cpu.h | 1 +
> 2 files changed, 2
Frank Chang 於 2021年6月26日 週六 下午11:03寫道：
> LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
>
>> The Core-Local Interrupt Controller (CLIC) provides low-latency,
>> vectored, pre-emptive interrupts for RISC-V systems.
>>
>> The CLIC also supports a new Selective Hardware Vectoring feature
>> that allow users
Hi,
I build qemu with MingW, and after the linking, I find the qemu.exe depends on
some dlls like below, I understand the glib dependencies, but why qemu uses
libffi-6.dll, libiconv-2.dll, libpcre-1.dll libssp-0.dll, libintl-8.dll,
libpixman-1-0.dll, zlib1.dll? I just want to use TCG function
LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for either faster
>
LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for either faster
>
On Fri, 25 Jun 2021, Mark Cave-Ayland wrote:
> Here is the next set of patches from my attempts to boot MacOS under
> QEMU's Q800 machine related to the Sonic network adapter.
>
> Patches 1 and 2 sort out checkpatch and convert from DPRINTF macros to
> trace-events.
>
> The discussion for the
On Wed, Jun 16, 2021 at 10:56 AM LIU Zhiwei wrote:
>
> On 6/13/21 6:10 PM, Frank Chang wrote:
>
> LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道：
>
>> The Core-Local Interrupt Controller (CLIC) provides low-latency,
>> vectored, pre-emptive interrupts for RISC-V systems.
>>
>> The CLIC also supports a new
On Mon, Jun 21, 2021 at 4:49 PM Or Ozeri wrote:
>
> Starting from ceph Pacific, RBD has built-in support for image-level
> encryption.
> Currently supported formats are LUKS version 1 and 2.
>
> There are 2 new relevant librbd APIs for controlling encryption, both expect
> an
> open image
Hi Nolan, Peter,
On 6/25/21 11:02 PM, Nolan Leake wrote:
> This is just enough to make reboot and poweroff work. Works for
> linux, u-boot, and the arm trusted firmware. Not tested, but should
> work for plan9, and bare-metal/hobby OSes, since they seem to generally
> do what linux does for
On 6/25/21 3:47 PM, Bin Meng wrote:
> On Thu, Jun 24, 2021 at 10:23 PM Philippe Mathieu-Daudé
> wrote:
>>
>> Log illegal commands as GUEST_ERROR.
>>
>> Note: we are logging back the SDIO commands (CMD5, CMD52-54).
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/sd/sd.c | 57
On 6/26/21 5:31 AM, Bin Meng wrote:
> On Sat, Jun 26, 2021 at 1:17 AM Philippe Mathieu-Daudé
> wrote:
>>
>> On 6/25/21 3:49 PM, Bin Meng wrote:
>>> On Thu, Jun 24, 2021 at 10:28 PM Philippe Mathieu-Daudé
>>> wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 21
On 6/26/21 8:36 AM, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c.inc | 12
> 1 file changed, 12 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 6/26/21 8:36 AM, Richard Henderson wrote:
> For INDEX_op_bswap32_i32, pass 0 for flags: input not zero-extended,
> output does not need extension within the host 64-bit register.
>
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 22
On 6/26/21 8:36 AM, Richard Henderson wrote:
> Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags
> in the internal uses for loads and stores.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.c.inc | 63
Patchew URL:
https://patchew.org/QEMU/20210626063631.2411938-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210626063631.2411938-1-richard.hender...@linaro.org
Subject: [PATCH v3
TCG_TARGET_HAS_MEMORY_BSWAP is already unset for this backend,
which means that MO_BSWAP be handled by the middle-end and
will never be seen by the backend. Thus the indexes used with
qemu_{ld,st}_helpers will always be zero.
Tidy the comments and asserts in tcg_out_qemu_{ld,st}_direct.
It is
The memory bswap support in the aarch64 backend merely dates from
a time when it was required. There is nothing special about the
backend support that could not have been provided by the middle-end
even prior to the introduction of the bswap flags.
Reviewed-by: Peter Maydell
Signed-off-by:
On 25/06/2021 13.27, Alex Bennée wrote:
Aside from a minor bloat to file size the ability to have TCG plugins
has no real impact on performance unless a plugin is actively loaded.
Even then the libempty.so plugin shows only a minor degradation in
performance caused by the extra book keeping the
The new bswap flags can implement the semantics exactly.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/arm/translate.c
Now that the middle-end can replicate the same tricks as tcg/arm
used for optimizing bswap for signed loads and for stores, do not
pretend to have these memory ops in the backend.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 +-
Remove TCG_BSWAP_IZ and the preceding zero-extension.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/sh4/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 147219759b..4dcfff81f6 100644
We can perform any required sign-extension via TCG_BSWAP_OS.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/tcg/tcg-op.c
We can eliminate the requirement for a zero-extended output,
because the following store will ignore any garbage high bits.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 6 ++
1 file changed, 2
By removing TCG_BSWAP_IZ we indicate that the input is
not zero-extended, and thus can remove an explicit extend.
By removing TCG_BSWAP_OZ, we allow the implementation to
leave high bits set, which will be ignored by the store.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
For the sf version, we are performing two 32-bit bswaps
in either half of the register. This is equivalent to
performing one 64-bit bswap followed by a rotate.
For the non-sf version, we can remove TCG_BSWAP_IZ
and the preceding zero-extension.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe
Implement the new semantics in the fallback expansion.
Change all callers to supply the flags that keep the
semantics unchanged locally.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h| 8 +--
Use a break instead of an ifdefed else.
There's no need to move the values through s->T0.
Remove TCG_BSWAP_IZ and the preceding zero-extension.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 14 --
1 file changed, 4 insertions(+), 10
There were two bugs here: (1) the required endianness was
not present in the MemOp, and (2) we were not providing a
zero-extended input to the bswap as semantics required.
The best fix is to fold the bswap into the memory operation,
producing the desired result directly.
Acked-by: Philippe
Merge tcg_out_bswap32 and tcg_out_bswap32s.
Use the flags in the internal uses for loads and stores.
For mips32r2 bswap32 with zero-extension, standardize on
WSBH+ROTR+DEXT. This is the same number of insns as the
previous DSBH+DSHD+DSRL but fits in better with the flags check.
Reviewed-by:
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 12
1 file changed, 12 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 8619e54fca..72aa7e0e74 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++
Notice when the input is known to be zero-extended and force
the TCG_BSWAP_IZ flag on. Honor the TCG_BSWAP_OS bit during
constant folding. Propagate the input to the output mask.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 56
Cc: qemu-...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 38 ++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index
For INDEX_op_bswap16_i64, use 64-bit instructions so that we can
easily provide the extension to 64-bits. Drop the special case,
previously used, where the input is already zero-extended -- the
minor code size savings is not worth the complication.
Cc: qemu-s3...@nongnu.org
Signed-off-by:
The existing interpreter zero-extends, ignoring high bits.
Simply add a separate sign-extension opcode if required.
Ensure that the interpreter supports ext16s when bswap16 is enabled.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c| 3 ++-
Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags
in the internal uses for loads and stores.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 63 +++
1 file changed, 30 insertions(+), 33
For INDEX_op_bswap32_i32, pass 0 for flags: input not zero-extended,
output does not need extension within the host 64-bit register.
Cc: qemu-...@nongnu.org
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 22 --
1 file changed, 16 insertions(+), 6
We will shortly require sari in other context;
split out both for cleanliness sake.
Cc: qemu-...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git
With the use of a suitable temporary, we can use the same
algorithm when src overlaps dst. The result is the same
number of instructions either way.
Cc: qemu-...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 34
Cc: qemu-...@nongnu.org
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 33f0139519..e0f4665213 100644
--- a/tcg/ppc/tcg-target.c.inc
+++
Retain the current rorw bswap16 expansion for the zero-in/zero-out case.
Otherwise, perform a wider bswap plus a right-shift or extend.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 20 +++-
1 file changed, 19 insertions(+), 1
Cc: qemu-...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 64 +---
1 file changed, 34 insertions(+), 30 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index
Combine the three bswap16 routines, and differentiate via the flags.
Use the correct flags combination from the load/store routines, and
pass along the constant parameter from tcg_out_op.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 101
Changes for v3:
* Comment improvments for mips (phil).
* Patch 3 is new, rearranging some tcg/aarch64 helpers.
Changes for v2:
* Merge tcg_out_rev{16,32,64}, which perhaps solves the issue of
mnemonics vs actual opcodes, and also preps for Phil suggestion
of adding additional tcg
We will shortly require these in other context;
make the expansion as clear as possible.
Cc: qemu-...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 31 +--
1 file changed,
This will eventually simplify front-end usage, and will allow
backends to unset TCG_TARGET_HAS_MEMORY_BSWAP without loss of
optimization.
The argument is added during expansion, not currently exposed to the
front end translators. The backends currently only support a flags
value of either
Pass in the input and output size. We currently use 3 of the 5
possible combinations; the others may be used by new tcg opcodes.
Cc: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 42 ++--
1 file changed, 16 insertions(+), 26
Ping. A local rebase seems to apply clean.
r~
On 3/16/21 3:07 PM, Richard Henderson wrote:
This is intending to fix the current aarch64 host failure
for s390x guest cdrom-test. This is caused by the io thread
issuing memory barriers that are supposed to be matched by
the vcpu, but are elided
59 matches
Mail list logo
