On Tue, Aug 17, 2021 at 06:30:37AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 8/16/21 11:59 PM, David Gibson wrote:
> > On Mon, Aug 16, 2021 at 02:53:13PM -0300, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 8/10/21 12:39 AM, David Gibson wrote:
> > > > On Mon, Aug 09, 2021 at 10:10:4
On 17/08/2021 11.30, Cédric Le Goater wrote:
Fetch the OpenPOWER images to boot the powernv8 and powernv9 machines
with a simple PCI layout.
Cc: Cleber Rosa
Cc: Philippe Mathieu-Daudé
Cc: Wainer dos Santos Moschetta
Signed-off-by: Cédric Le Goater
---
Since v2:
- Change the skiboot.lid
On Aug 3 12:54, Padmakar Kalghatgi wrote:
> From: padmakar
>
> This patch contains the implementation of certain commands
> of nvme-mi specification.The MI commands are useful to
> manage/configure/monitor the device.Eventhough the MI commands
> can be sent via the inband NVMe-MI send/recieve c
在 2021/8/18 11:50, Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
写道:
>
>
> 在 2021/8/18 4:26, Alex Williamson 写道:
>> On Fri, 13 Aug 2021 12:06:14 +0800
>> "Longpeng(Mike)" wrote:
>>
>>> In migration resume phase, all unmasked msix vectors need to be
>>> setup when load the VF sta
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1858814
Title:
'make -C ro
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1880763
Title:
Missing pag
在 2021/8/18 4:26, Alex Williamson 写道:
> On Fri, 13 Aug 2021 12:06:14 +0800
> "Longpeng(Mike)" wrote:
>
>> In migration resume phase, all unmasked msix vectors need to be
>> setup when load the VF state. However, the setup operation would
>> takes longer if the VF has more unmasked vectors.
>>
On Tue, 2021-08-17 at 16:10 -0700, Steve Rutherford wrote:
> On Tue, Aug 17, 2021 at 3:57 PM James Bottomley
> wrote:
> > Realistically, migration is becoming a royal pain, not just for
> > confidential computing, but for virtual functions in general. I
> > really think we should look at S3 suspe
Add configurable property memory region which can connect with IOMMU region to
support SMMU translate.
Signed-off-by: Jianxian Wen
---
v3 -> v4 (after review of Philippe Mathieu-Daudé):
- Avoid adding unnecessary AS, add AS if we connect with IOMMU region.
v2 -> v3 (after review of Philippe Mat
From: Peter Maydell
In v8A, the PSTATE.IL bit is set for various kinds of illegal
exception return or mode-change attempts. We already set PSTATE.IL
(or its AArch32 equivalent CPSR.IL) in all those cases, but we
weren't implementing the part of the behaviour where attempting to
execute an instru
Both single-step and pc alignment faults have priority over
breakpoint exceptions.
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2983e36dd3..3
For A64, any input to an indirect branch can cause this.
For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not. This includes the BX instruction but also
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED UNDEF
It is confusing to have different exits from translation
for various conditions in separate functions.
Merge disas_a64_insn into its only caller. Standardize
on the "s" name for the DisasContext, as the code from
disas_a64_insn had more instances.
Signed-off-by: Richard Henderson
---
target/ar
As discussed earlier today at
https://lists.gnu.org/archive/html/qemu-devel/2021-08/msg02686.html
Raise pc alignment faults.
Fix single-step and pc-align priority over breakpoints.
Not yet fixing insn abort priority over breakpoints.
r~
Peter Maydell (1):
target/arm: Take an exception if PST
On Tue, Aug 17, 2021 at 03:45:19PM -0400, Vivek Goyal wrote:
> On Tue, Aug 17, 2021 at 10:27:16AM +0200, Hanna Reitz wrote:
> > On 16.08.21 21:44, Vivek Goyal wrote:
> > > On Wed, Aug 11, 2021 at 08:41:18AM +0200, Hanna Reitz wrote:
> > >
> > > [..]
> > > > > > But given the inotify complications,
On Tue, Aug 17, 2021 at 10:51 PM Tobin Feldman-Fitzthum
wrote:
> This is essentially what we do in our prototype, although we have an
> even simpler approach. We have a 1:1 mapping that maps an address to
> itself with the cbit set. During Migration QEMU asks the migration
> handler to import/expo
On Tue, Aug 17, 2021 at 3:57 PM James Bottomley wrote:
> Realistically, migration is becoming a royal pain, not just for
> confidential computing, but for virtual functions in general. I really
> think we should look at S3 suspend, where we shut down the drivers and
> then reattach on S3 resume a
On Mon, 16 Aug 2021 09:42:34 -0700
Elena Ufimtseva wrote:
> +Authentication
> +--
> +
> +For ``AF_UNIX``, we rely on OS mandatory access controls on the socket files,
> +therefore it is up to the management layer to set up the socket as required.
> +Socket types than span guests or hos
On Wed, 2021-08-18 at 00:37 +0200, Paolo Bonzini wrote:
> On Tue, Aug 17, 2021 at 11:54 PM Steve Rutherford
> wrote:
> > > 1) the easy one: the bottom 4G of guest memory are mapped in the
> > > mirror
> > > VM 1:1. The ram_addr_t-based addresses are shifted by either 4G
> > > or a
> > > huge valu
On Tue, Aug 17, 2021 at 11:54 PM Steve Rutherford
wrote:
> > 1) the easy one: the bottom 4G of guest memory are mapped in the mirror
> > VM 1:1. The ram_addr_t-based addresses are shifted by either 4G or a
> > huge value such as 2^42 (MAXPHYADDR - physical address reduction - 1).
> > This even le
On 8/17/21 10:21 PM, Viktor Prutyanov wrote:
> Make 'qemu-img commit' work on Windows.
>
> Command 'commit' requires reopening backing file in RW mode. So,
> add reopen prepare/commit/abort handlers and change dwShareMode
> for CreateFile call in order to allow further read/write reopening.
>
> R
On 8/17/21 11:18 PM, Richard Henderson wrote:
> Exit early if check_access fails.
> Split out do_hlv, do_hsv, do_hlvx subroutines.
> Use dest_gpr, get_gpr in the new subroutines.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/insn32.decode | 1 +
> target/riscv/insn_tra
On 8/17/21 11:17 PM, Richard Henderson wrote:
> Move these helpers near their use by the trans_*
> functions within insn_trans/trans_rvb.c.inc.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 233 ---
> target/riscv/insn_trans/trans_rvb.
On 8/17/21 11:17 PM, Richard Henderson wrote:
> Move these helpers near their use by the trans_*
> functions within insn_trans/trans_rvm.c.inc.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 112
> target/riscv/insn_trans/trans_rvm
On 8/16/21 8:03 AM, Peter Maydell wrote:
Peter Maydell (2):
target/arm: Implement HSTR.TTEE
target/arm: Implement HSTR.TJDBX
Reviewed-by: Richard Henderson
r~
On 8/17/21 11:17 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 58 -
> target/riscv/insn_trans/trans_rva.c.inc | 18
> target/riscv/insn_trans/trans_rvb.c.inc | 4 +-
> target/riscv/insn_trans/tr
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fifth release candidate for the QEMU 6.1 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-6.1.0-rc4.tar.xz
http://downl
On 8/17/21 5:39 AM, Richard Henderson wrote:
Hmm, you're correct that we get this wrong.
We probably didn't do these in the right priority
order before this series, though, and I dunno whether
we get the insn-abort vs swstep ordering right either...
And you're correct that we got it wrong bef
On Tue, Aug 17, 2021 at 1:50 PM Tobin Feldman-Fitzthum
wrote:
>
>
> On 8/17/21 12:32 PM, Paolo Bonzini wrote:
> > There's three possibilities for this:
> >
> > 1) the easy one: the bottom 4G of guest memory are mapped in the
> > mirror VM 1:1. The ram_addr_t-based addresses are shifted by either
On Tue, Aug 17, 2021 at 9:32 AM Paolo Bonzini wrote:
>
> On 17/08/21 01:53, Steve Rutherford wrote:
> > Separately, I'm a little weary of leaving the migration helper mapped
> > into the shared address space as writable.
>
> A related question here is what the API should be for how the migration
>
Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use dest_gpr, get_gpr in the new subroutines.
Signed-off-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvh.c.inc | 266 +---
2 files cha
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvd.c.inc | 125
1 file changed, 60 insertions(+), 65 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index 11b9b3f90b..db9ae15755 100644
--- a
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvf.c.inc | 146
1 file changed, 70 insertions(+), 76 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index fb9f7f9c00..bddbd418d9 100644
--- a
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 36 +
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index af3e0bc0e6..f616a26c82 100644
--- a
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++-
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index af7694ed29..d5a036b1f3 100644
--- a/t
Introduce csrr and csrw helpers, for read-only and write-only insns.
Note that we do not properly implement this in riscv_csrrw, in that
we cannot distinguish true read-only (rs1 == 0) from any other zero
write_mask another source register -- this should still raise an
exception for read-only regi
Remove gen_get_gpr, as the function becomes unused.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 13 ++---
target/riscv/insn_trans/trans_rvv.c.inc | 74 +++--
2 files changed, 26 insertions(+), 61 deletions(-)
diff --git a/target/riscv/trans
Narrow the scope of t0 in trans_jalr.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
in
Replicate the bswap special case from gen_grevi for
the word-sized operation.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvb.c.inc | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/in
These operations are greatly simplified by ctx->w, which allows
us to fold gen_shiftw into gen_shift. Split gen_shifti into
gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 110 +---
target
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rva.c.inc | 47 ++---
1 file changed, 19 insertions(+), 28 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc
b/target/riscv/insn_trans/trans_rva.c.inc
index 3cc3c3b073..6ea07d89b0 100644
--- a
Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 14 ++
target/riscv/insn_trans/trans_rvb.c.inc | 24 +---
2 files changed, 1
Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.
Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 69 +++--
t
Split out gen_mulh and gen_mulhu and use the common helper.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvm.c.inc | 40 +++--
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc
b/target/riscv/insn_tr
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 58 -
target/riscv/insn_trans/trans_rva.c.inc | 18
target/riscv/insn_trans/trans_rvb.c.inc | 4 +-
target/riscv/insn_trans/trans_rvd.c.inc | 32 +++---
target/riscv/insn_trans
Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
tcg globals into temps, returning a constant 0 for $zero as source and
a new temp for $zero as destination.
Introduce ctx->w for simplifying word operations, such as addw.
Signed-off-by: Richard Henderson
---
target/riscv/tr
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvb.c.inc.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 233 ---
target/riscv/insn_trans/trans_rvb.c.inc | 234
2 files changed, 234 i
Use ctx->w and the enhanced gen_arith function.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 42 -
target/riscv/insn_trans/trans_rvm.c.inc | 16 +-
2 files changed, 8 insertions(+), 50 deletions(-)
diff --git a/target/riscv/trans
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvm.c.inc.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 112
target/riscv/insn_trans/trans_rvm.c.inc | 112
2 files changed, 112
Utilize the condition in the movcond more; this allows some of
the setcond that were feeding into movcond to be removed.
Do not write into source1 and source2. Re-name "condN" to "tempN"
and use the temporaries for more than holding conditions.
Signed-off-by: Richard Henderson
---
target/riscv/
Replace uses of tcg_const_* with the allocate and free close together.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 36 --
target/riscv/insn_trans/trans_rvf.c.inc | 3 +-
target/ris
Replace use of tcg_const_*, which makes a copy into a temp
which must be freed, with direct use of the constant.
Reorg handling of $zero, with different accessors for
source and destination.
Reorg handling of csrs, passing the actual write_mask
instead of a regno.
Use more helpers for RVH expans
On 8/17/21 12:32 PM, Paolo Bonzini wrote:
On 17/08/21 01:53, Steve Rutherford wrote:
Separately, I'm a little weary of leaving the migration helper mapped
into the shared address space as writable.
A related question here is what the API should be for how the
migration helper sees the memor
On 8/17/21 10:26 AM, Peter Maydell wrote:
On Tue, 17 Aug 2021 at 21:18, Peter Maydell wrote:
Currently we rely on all the callsites of cpsr_write() to rebuild the
cached hflags if they change one of the CPSR bits which we use as a
TB flag and cache in hflags. This is a bit awkward when we wan
On 8/17/21 6:21 AM, Peter Maydell wrote:
In v8A, the PSTATE.IL bit is set for various kinds of illegal
exception return or mode-change attempts. We already set PSTATE.IL
(or its AArch32 equivalent CPSR.IL) in all those cases, but we
weren't implementing the part of the behaviour where attempting
On Tue, 17 Aug 2021 at 21:18, Peter Maydell wrote:
>
> Currently we rely on all the callsites of cpsr_write() to rebuild the
> cached hflags if they change one of the CPSR bits which we use as a
> TB flag and cache in hflags. This is a bit awkward when we want to
> change the set of CPSR bits tha
On Fri, 13 Aug 2021 12:06:14 +0800
"Longpeng(Mike)" wrote:
> In migration resume phase, all unmasked msix vectors need to be
> setup when load the VF state. However, the setup operation would
> takes longer if the VF has more unmasked vectors.
>
> In our case, the VF has 65 vectors and each one
Make 'qemu-img commit' work on Windows.
Command 'commit' requires reopening backing file in RW mode. So,
add reopen prepare/commit/abort handlers and change dwShareMode
for CreateFile call in order to allow further read/write reopening.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/418
Currently we rely on all the callsites of cpsr_write() to rebuild the
cached hflags if they change one of the CPSR bits which we use as a
TB flag and cache in hflags. This is a bit awkward when we want to
change the set of CPSR bits that we cache, because it means we need
to re-audit all the cpsr_
Make 'qemu-img commit' work on Windows.
Command 'commit' requires reopening backing file in RW mode. So,
add reopen prepare/commit/abort handlers and change dwShareMode
for CreateFile call in order to allow further read/write reopening.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/418
On Tue, Aug 03, 2021 at 02:29:29PM -0400, John Snow wrote:
> The Message class is here primarily to serve as a solid type to use for
> mypy static typing for unambiguous annotation and documentation.
>
> We can also stuff JSON serialization and deserialization into this class
> itself so it can be
On Tue, Aug 17, 2021 at 10:27:16AM +0200, Hanna Reitz wrote:
> On 16.08.21 21:44, Vivek Goyal wrote:
> > On Wed, Aug 11, 2021 at 08:41:18AM +0200, Hanna Reitz wrote:
> >
> > [..]
> > > > > But given the inotify complications, there’s really a good reason we
> > > > > should
> > > > > use mountinf
On Tue, Aug 03, 2021 at 02:29:28PM -0400, John Snow wrote:
> This is added as a courtesy: many protocols are line-based, including
> QMP. Putting it in AsyncProtocol lets us keep the QMP class
> implementation just a pinch more abstract.
>
> (And, if we decide to add a QTEST implementation later,
On Tue, Aug 03, 2021 at 02:29:27PM -0400, John Snow wrote:
> Add hooks designed to log/filter incoming/outgoing messages. The primary
> intent for these is to be able to support iotests which may want to log
> messages with specific filters for reproducible output.
>
> Another use is for plugging
On Tue, Aug 03, 2021 at 02:29:26PM -0400, John Snow wrote:
> QMP can transmit some pretty big messages, and the default limit of 64KB
> isn't sufficient. Make sure that we can configure it.
>
> Reported-by: G S Niteesh Babu
> Signed-off-by: John Snow
> ---
> python/qemu/aqmp/protocol.py | 18 ++
On Tue, Aug 03, 2021 at 02:29:25PM -0400, John Snow wrote:
> It's a little messier than connect, because it wasn't designed to accept
> *precisely one* connection. Such is life.
>
> Signed-off-by: John Snow
> ---
> python/qemu/aqmp/protocol.py | 89 ++--
> 1 file
If users try to add an isa-vga device that was already registered,
still in command line, qemu will crash:
$ qemu-system-mips64el -M pica61 -device isa-vga
RAMBlock "vga.vram" already registered, abort!
Aborted (core dumped)
That particular board registers the device automaticaly, so it's
not obv
On Tue, Aug 03, 2021 at 02:29:24PM -0400, John Snow wrote:
> Give the connection and the reader/writer tasks nicknames, and add
> logging statements throughout.
>
> Signed-off-by: John Snow
> ---
> python/qemu/aqmp/protocol.py | 82
> 1 file changed, 73 inser
On Tue, Aug 03, 2021 at 02:29:23PM -0400, John Snow wrote:
> Signed-off-by: John Snow
> ---
> python/qemu/aqmp/util.py | 56
> 1 file changed, 56 insertions(+)
>
Reviewed-by: Eric Blake
--
Eric Blake, Principal Software Engineer
Red Hat, Inc.
On Tue, Aug 17, 2021 at 10:21 AM John Snow wrote:
>
>
> On Fri, Jul 30, 2021 at 4:19 PM G S Niteesh Babu
> wrote:
>
>> Instead of manually connecting and disconnecting from the
>> server. We now rely on the runstate to manage the QMP
>> connection.
>>
>> Along with this the ability to reconnect
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 17 Aug 2021 at 17:27, Dr. David Alan Gilbert
> wrote:
> >
> > * Gabriel Southern (gsout...@qti.qualcomm.com) wrote:
> > > Hi,
> > >
> > > Are there plans to support using -loadvm with -snapshot?
> > >
> > > I saw some past discussion on m
On Tue, Aug 17, 2021 at 10:07:55AM +0200, Philippe Mathieu-Daudé wrote:
> On 8/17/21 9:36 AM, Mark Cave-Ayland wrote:
> > On 17/08/2021 08:25, Thomas Huth wrote:
> >
> >> On 16/08/2021 15.55, Jose R. Ziviani wrote:
> >>> If users try to add an isa-vga device that was already registered,
> >>> stil
On Tue, 17 Aug 2021 at 17:27, Dr. David Alan Gilbert
wrote:
>
> * Gabriel Southern (gsout...@qti.qualcomm.com) wrote:
> > Hi,
> >
> > Are there plans to support using -loadvm with -snapshot?
> >
> > I saw some past discussion on mailing list including bug that was closed
> > earlier this year but
Drop migration_bitmap_sync_precopy() since dirty bitmap is initialized to all
ones anyways, so no need to sync at start.
Since at it, clean the locks up a bit:
- RCU lock is only needed to walk the ramblocks, move it into
ram_list_init_bitmaps().
- The ram_list lock seems to be unnecessa
On 8/17/21 6:12 PM, Christian Schoenebeck wrote:
> On Dienstag, 17. August 2021 14:41:27 CEST Gerd Hoffmann wrote:
>> Hi,
>>
+Overall Audio frontends
>>>
>>> I would call that "Audio Hardware Emulation" instead of "Overall Audio
>>> frontends".
>>>
+Overall Audio backends
>>>
>>> Likewi
On Mon, Aug 16, 2021 at 2:44 AM Leonardo Bras Soares Passos
wrote:
>
> Hello Lukas,
>
> On Wed, Aug 4, 2021 at 4:27 PM Lukas Straub wrote:
> >
> > When introducing yank functionality in the migration code I forgot
> > to cover the multifd send side.
> >
> > Signed-off-by: Lukas Straub
> > ---
>
On 17/08/21 01:53, Steve Rutherford wrote:
Separately, I'm a little weary of leaving the migration helper mapped
into the shared address space as writable.
A related question here is what the API should be for how the migration
helper sees the memory in both physical and virtual address.
Fir
On Tue, Aug 17, 2021 at 05:53:34AM -1000, Richard Henderson wrote:
> On 8/17/21 5:36 AM, Andrew Jones wrote:
> > On Tue, Aug 17, 2021 at 05:23:17AM -1000, Richard Henderson wrote:
> > > On 8/17/21 1:56 AM, Andrew Jones wrote:
> > > > I guess it's fine. You could easily create a new cpu_arm_set_sve_
* Gabriel Southern (gsout...@qti.qualcomm.com) wrote:
> Hi,
>
> Are there plans to support using -loadvm with -snapshot?
>
> I saw some past discussion on mailing list including bug that was closed
> earlier this year but no recent activity:
>
> https://lore.kernel.org/qemu-devel/162424905685.1
In v8A, the PSTATE.IL bit is set for various kinds of illegal
exception return or mode-change attempts. We already set PSTATE.IL
(or its AArch32 equivalent CPSR.IL) in all those cases, but we
weren't implementing the part of the behaviour where attempting to
execute an instruction with PSTATE.IL t
On Tue, 17 Aug 2021 at 16:57, Paolo Bonzini wrote:
> On 17/08/21 16:31, Kenneth Adam Miller wrote:
> > I am trying to discover how to schedule QEMU to begin actual emulation
> > as currently my target correctly starts QEMU but only shows the shell,
> > and not even boot loading occurs within QEMU.
On 8/17/21 5:59 PM, Peter Maydell wrote:
> On Tue, 17 Aug 2021 at 16:55, Damien Hedde wrote:
>>
>>
>>
>> On 8/12/21 11:33 AM, Peter Maydell wrote:
>> According to
>> https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Address-Map/The-system-timer--SysTick/SysTick-
On Dienstag, 17. August 2021 14:41:27 CEST Gerd Hoffmann wrote:
> Hi,
>
> > > +Overall Audio frontends
> >
> > I would call that "Audio Hardware Emulation" instead of "Overall Audio
> > frontends".
> >
> > > +Overall Audio backends
> >
> > Likewise I would call this section "Shared/common QEM
On Tue, Aug 17, 2021 at 09:25:56AM +0200, David Hildenbrand wrote:
> On 17.08.21 03:37, Peter Xu wrote:
> > Trace at memory_region_sync_dirty_bitmap() for log_sync() or
> > global_log_sync()
> > on memory regions. One trace line should suffice when it finishes, so as to
> > estimate the time used
On 17.08.21 18:05, Peter Xu wrote:
On Tue, Aug 17, 2021 at 09:25:56AM +0200, David Hildenbrand wrote:
On 17.08.21 03:37, Peter Xu wrote:
Trace at memory_region_sync_dirty_bitmap() for log_sync() or global_log_sync()
on memory regions. One trace line should suffice when it finishes, so as to
es
On 8/12/21 11:33 AM, Peter Maydell wrote:
> The implementation of the Stellaris general purpose timer module
> device stellaris-gptm is currently in the same source file as the
> board model. Split it out into its own source file in hw/timer.
>
> Apart from the new file comment headers and the
On Tue, 17 Aug 2021 at 16:55, Damien Hedde wrote:
>
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> According to
> https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Address-Map/The-system-timer--SysTick/SysTick-Calibration-value-Register--SYST-CALIB
> , the field
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Now that all users of the systick devices wire up the clock inputs,
> use those instead of the system_clock_scale and the hardwired 1MHz
> value for the reference clock.
>
> This will fix various board models where we were incorrectly
> providing a 1M
On 17/08/21 16:31, Kenneth Adam Miller wrote:
I am trying to discover how to schedule QEMU to begin actual emulation
as currently my target correctly starts QEMU but only shows the shell,
and not even boot loading occurs within QEMU. I'm trying to learn from
example, and so will focus my que
On 8/17/21 5:36 AM, Andrew Jones wrote:
On Tue, Aug 17, 2021 at 05:23:17AM -1000, Richard Henderson wrote:
On 8/17/21 1:56 AM, Andrew Jones wrote:
I guess it's fine. You could easily create a new cpu_arm_set_sve_vq()
which would forbid changing the properties if you wanted to, but then
we need
On Tue, 17 Aug 2021 at 08:14, David Hildenbrand wrote:
>
> On 16.08.21 22:52, Peter Xu wrote:
> > On Thu, Aug 05, 2021 at 11:23:50AM +0200, David Hildenbrand wrote:
> >> When adding RAM_NORESERVE, we forgot to remove the old assertion when
> >> adding the updated one, most probably when reworking
On Tue, 17 Aug 2021 at 13:56, Andrew Jones wrote:
>
> Commit 1e63fe685804 ("machine: pass QAPI struct to mc->smp_parse")
> introduced documentation stating that a zero input value for an SMP
> parameter indicates that its value should be automatically configured.
> This is indeed how things work t
On 8/17/21 3:33 AM, Peter Maydell wrote:
On Wed, 21 Jul 2021 at 21:00, Richard Henderson
wrote:
Trigger breakpoints before beginning translation of a TB
that would begin with a BP. Thus we never generate code
for the BP at all.
I happened to notice in the Arm ARM today a corner case that th
On Tue, Aug 17, 2021 at 05:23:17AM -1000, Richard Henderson wrote:
> On 8/17/21 1:56 AM, Andrew Jones wrote:
> > I guess it's fine. You could easily create a new cpu_arm_set_sve_vq()
> > which would forbid changing the properties if you wanted to, but then
> > we need to answer Peter's question in
On 8/17/21 1:56 AM, Andrew Jones wrote:
I guess it's fine. You could easily create a new cpu_arm_set_sve_vq()
which would forbid changing the properties if you wanted to, but then
we need to answer Peter's question in order to see if there's a
precedent for that type of property.
I don't see th
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a
> frequency which is programmably either /4, /8, /16 or /32 of the main
> CPU clock. We don't currently model the register which allows the
> guest to set the divisor, so implement th
On Thu, Aug 12, 2021 at 10:41:45AM +0200, Hanna Reitz wrote:
> .bdrv_co_block_status() implementations are free to return a *pnum that
> exceeds @bytes, because bdrv_co_block_status() in block/io.c will clamp
> *pnum as necessary.
>
> On the other hand, if drivers' implementations return values fo
On 8/17/21 12:46 PM, Peter Maydell wrote:
> On Tue, 17 Aug 2021 at 10:59, Damien Hedde wrote:
>>
>>
>>
>> On 8/12/21 11:33 AM, Peter Maydell wrote:
>
>>> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
>>> +{
>>> +assert(divider != 0);
>>> +
>>> +clk->multipl
Hi Jean,
On 8/10/21 10:45 AM, Jean-Philippe Brucker wrote:
> Allow instantiating a virtio-iommu device on ACPI systems by adding a
> Virtual I/O Translation table (VIOT). Enable x86 support for VIOT.
Don't you need your other patch
"virtio-iommu: Default to bypass during boot"?
Without this latt
On 8/16/21 10:50 AM, Philippe Mathieu-Daudé wrote:
Trivial patches:
- Remove unused macros
- Use tcg_constant_i32()
- Inline the macros when few uses
- Move macro definitions in translate.h
Philippe Mathieu-Daudé (8):
target/mips: Remove gen_helper_0e3i()
target/mips: Remove gen_helper_1e2
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