[PATCH v3] hw/intc/sifive_clint: Fix overflow in sifive_clint_write_timecmp()

`muldiv64` would overflow in cases where the final 96-bit value does not fit in a `uint64_t`. This would result in small values that cause an interrupt to be triggered much sooner than intended. The overflow can be detected in most cases by checking if the new value is smaller than the previous

RE: [PATCH v4 1/3] target-arm: Add support for Fujitsu A64FX

> I think this will be more clear once I get the patch posted (which I haven't > started > writing yet). I'll try to get it posted by tomorrow evening though, since I > have > vacation on Friday. While Andrew is working on the patch in a hurry, I'm sorry, I'll be on vacation for a while

[PATCH 4/9] hw/nvram: Introduce Xilinx ZynqMP eFuse device

This implements the Xilinx ZynqMP eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx ZynqMP product family. The command argument: -drive if=pflash,index=N,... Can be used to optionally connect the storage array to a backend storage,

[PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM

This series implements the Xilinx eFUSE and BBRAM devices for the Versal and ZynqMP product families. Furthermore, both new devices are connected to the xlnx-versal-virt board and the xlnx-zcu102 board. See changes in docs/system/arm/xlnx-versal-virt.rst for detail. Tong Ho (9):

[PATCH 3/9] hw/nvram: Introduce Xilinx Versal eFuse device

This implements the Xilinx Versal eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx Versal product family. The command argument: -drive if=pflash,index=N,... Can be used to optionally connect the storage array to a backend storage,

[PATCH 5/9] hw/nvram: Introduce Xilinx battery-backed ram

This device is present in Versal and ZynqMP product families to store a 256-bit encryption key. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan Boddu Signed-off-by: Tong Ho --- hw/nvram/Kconfig | 4 +

[PATCH 1/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage

Add BBRAM and eFUSE usage to the Xilinx Versal Virt board document. Signed-off-by: Tong Ho --- docs/system/arm/xlnx-versal-virt.rst | 49 1 file changed, 49 insertions(+) diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst

[PATCH 9/9] hw/arm: xlnx-zynqmp: Add Xilinx eFUSE device

Connect the support for ZynqMP eFUSE one-time field-programmable bit array. Signed-off-by: Tong Ho --- hw/arm/xlnx-zynqmp.c | 29 + include/hw/arm/xlnx-zynqmp.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c

[PATCH 7/9] hw/arm: xlnx-versal: Add Xilinx eFUSE device

Connect the support for Versal eFUSE one-time field-programmable bit array. Signed-off-by: Tong Ho --- hw/arm/xlnx-versal-virt.c| 36 + hw/arm/xlnx-versal.c | 39 include/hw/arm/xlnx-versal.h | 12 +++ 3

[PATCH 2/9] hw/nvram: Introduce Xilinx eFuse QOM

This introduces the QOM for Xilinx eFuse, an one-time field-programmable storage bit array. The actual mmio interface to the array varies by device families and will be provided in different change-sets. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E.

[PATCH 6/9] hw/arm: xlnx-versal: Add Xilinx BBRAM device

Connect the support for Versal Battery-Backed RAM (BBRAM) Signed-off-by: Tong Ho --- hw/arm/xlnx-versal-virt.c| 21 + hw/arm/xlnx-versal.c | 18 ++ include/hw/arm/xlnx-versal.h | 5 + 3 files changed, 44 insertions(+) diff --git

[PATCH 8/9] hw/arm: xlnx-zynqmp: Add Xilinx BBRAM device

Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM) Signed-off-by: Tong Ho --- hw/arm/xlnx-zynqmp.c | 21 + include/hw/arm/xlnx-zynqmp.h | 2 ++ 2 files changed, 23 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index

[PATCH v6 14/16] machine: Put all sanity-check in the generic SMP parser

Put both sanity-check of the input SMP configuration and sanity-check of the output SMP configuration uniformly in the generic parser. Then machine_set_smp() will become cleaner, also all the invalid scenarios can be tested only by calling the parser. Signed-off-by: Yanan Wang Reviewed-by:

[PATCH v6 12/16] machine: Remove smp_parse callback from MachineClass

Now we have a generic smp parser for all arches, and there will not be any other arch specific ones, so let's remove the callback from MachineClass and call the parser directly. Signed-off-by: Yanan Wang Reviewed-by: Andrew Jones --- hw/core/machine.c | 3 +-- include/hw/boards.h | 5 -

[PATCH v6 16/16] tests/unit: Add a unit test for smp parsing

Add a QEMU unit test for the parsing of given SMP configuration. Since all the parsing logic is in generic function smp_parse(), this test passes different SMP configurations to the function and compare the parsing result with what is expected. In the test, all possible collections of the

[PATCH v6 13/16] machine: Move smp_prefer_sockets to struct SMPCompatProps

Now we have a common structure SMPCompatProps used to store information about SMP compatibility stuff, so we can also move smp_prefer_sockets there for cleaner code. No functional change intended. Signed-off-by: Yanan Wang Acked-by: David Gibson Reviewed-by: Andrew Jones --- hw/arm/virt.c

[Patch 2/2] hw/arm/xlnx-zynqmp: Add unimplemented APU mmio

Add unimplemented APU mmio region to xlnx-zynqmp for booting bare-metal guests built with standalone bsp published at: https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit Signed-off-by: Tong Ho --- hw/arm/xlnx-zynqmp.c | 32

[PATCH v6 10/16] machine: Tweak the order of topology members in struct CpuTopology

Now that all the possible topology parameters are integrated in struct CpuTopology, tweak the order of topology members to be "cpus/sockets/ dies/cores/threads/maxcpus" for readability and consistency. We also tweak the comment by adding explanation of dies parameter. Signed-off-by: Yanan Wang

[PATCH v6 11/16] machine: Make smp_parse generic enough for all arches

Currently the only difference between smp_parse and pc_smp_parse is the support of dies parameter and the related error reporting. With some arch compat variables like "bool dies_supported", we can make smp_parse generic enough for all arches and the PC specific one can be removed. Making

[Patch 1/2] hw/arm/xlnx-versal: Add unimplemented APU mmio

Add unimplemented APU mmio region to xlnx-versal for booting bare-metal guests built with standalone bsp published at: https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit Signed-off-by: Tong Ho --- hw/arm/xlnx-versal.c | 2 ++

[Patch 0/2] hw/arm/xlnx-versal: hw/arm/xlnx-zynqmp: Add unimplemented mmio

This series adds the APU mmio region as an unimplemented device to each of two Xilinx SoC to support booting guests built with the standalone bsp published at: https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit Tong Ho (2): hw/arm/xlnx-versal: Add

[PATCH v6 08/16] machine: Prefer cores over sockets in smp parsing since 6.2

In the real SMP hardware topology world, it's much more likely that we have high cores-per-socket counts and few sockets totally. While the current preference of sockets over cores in smp parsing results in a virtual cpu topology with low cores-per-sockets counts and a large number of sockets,

[PATCH v6 07/16] hw: Add compat machines for 6.2

Add 6.2 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Yanan Wang Acked-by: David Gibson Reviewed-by: Andrew Jones Reviewed-by: Cornelia Huck Reviewed-by: Pankaj Gupta --- hw/arm/virt.c | 9 - hw/core/machine.c | 3 +++ hw/i386/pc.c

[PATCH v6 15/16] machine: Split out the smp parsing code

We are going to introduce an unit test for the parser smp_parse() in hw/core/machine.c, but now machine.c is only built in softmmu. In order to solve the build dependency on the smp parsing code and avoid building unrelated stuff for the unit tests, move the related code from machine.c into a new

[PATCH v6 01/16] docs/about/removed-features: Remove duplicated doc about -smp

There are two places describing the same thing about deprecation of invalid topologies of -smp CLI, so remove the duplicated one. Signed-off-by: Yanan Wang --- docs/about/removed-features.rst | 21 - 1 file changed, 4 insertions(+), 17 deletions(-) diff --git

[PATCH v6 04/16] machine: Uniformly use maxcpus to calculate the omitted parameters

We are currently using maxcpus to calculate the omitted sockets but using cpus to calculate the omitted cores/threads. This makes cmdlines like: -smp cpus=8,maxcpus=16 -smp cpus=8,cores=4,maxcpus=16 -smp cpus=8,threads=2,maxcpus=16 work fine but the ones like: -smp

[PATCH v6 02/16] machine: Deprecate "parameter=0" SMP configurations

In the SMP configuration, we should either provide a topology parameter with a reasonable value (greater than zero) or just omit it and QEMU will compute the missing value. The users shouldn't provide a configuration with any parameter of it specified as zero (e.g. -smp 8,sockets=0) which could

[PATCH v6 09/16] machine: Use ms instead of global current_machine in sanity-check

In the sanity-check of smp_cpus and max_cpus against mc in function machine_set_smp(), we are now using ms->smp.max_cpus for the check but using current_machine->smp.max_cpus in the error message. Tweak this by uniformly using the local ms. Signed-off-by: Yanan Wang Reviewed-by: Andrew Jones

[PATCH v6 03/16] machine: Minor refactor/fix for the smp parsers

To pave the way for the functional improvement in later patches, make some refactor/cleanup for the smp parsers, including using local maxcpus instead of ms->smp.max_cpus in the calculation, defaulting dies to 0 initially like other members, cleanup the sanity check for dies. We actually also fix

[PATCH v6 06/16] machine: Improve the error reporting of smp parsing

We have two requirements for a valid SMP configuration: the product of "sockets * cores * threads" must represent all the possible cpus, i.e., max_cpus, and then must include the initially present cpus, i.e., smp_cpus. So we only need to ensure 1) "sockets * cores * threads == maxcpus" at first

[PATCH v6 00/16] machine: smp parsing fixes and improvement

Rebased on upstream v6.1.0-rc4 with two more patches added. This series introduces some fixes and improvement for the SMP parsing. Behavior of specifying a CPU topology parameter as zero was implicitly allowed but undocumented before, while now it's explicitly deprecated. maxcpus is now uniformly

[PATCH v6 05/16] machine: Set the value of cpus to match maxcpus if it's omitted

Currently we directly calculate the omitted cpus based on the given incomplete collection of parameters. This makes some cmdlines like: -smp maxcpus=16 -smp sockets=2,maxcpus=16 -smp sockets=2,dies=2,maxcpus=16 -smp sockets=2,cores=4,maxcpus=16 not work. We should probably set the value of

Re: [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM

On Wed, Aug 18, 2021 at 5:18 AM Richard Henderson wrote: > > Move these helpers near their use by the trans_* > functions within insn_trans/trans_rvm.c.inc. > > Signed-off-by: Richard Henderson > --- > target/riscv/translate.c| 112 >

Re: [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB

On Wed, Aug 18, 2021 at 5:21 AM Richard Henderson wrote: > > Move these helpers near their use by the trans_* > functions within insn_trans/trans_rvb.c.inc. > > Signed-off-by: Richard Henderson > --- > target/riscv/translate.c| 233 --- >

Re: [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu

On Wed, Aug 18, 2021 at 5:23 AM Richard Henderson wrote: > > Split out gen_mulh and gen_mulhu and use the common helper. > > Signed-off-by: Richard Henderson > --- > target/riscv/insn_trans/trans_rvm.c.inc | 40 +++-- > 1 file changed, 18 insertions(+), 22 deletions(-) >

Re: [PATCH v2 06/21] target/riscv: Remove gen_arith_div*

On Wed, Aug 18, 2021 at 5:20 AM Richard Henderson wrote: > > Use ctx->w and the enhanced gen_arith function. > > Signed-off-by: Richard Henderson > --- > target/riscv/translate.c| 42 - > target/riscv/insn_trans/trans_rvm.c.inc | 16 +- > 2 files

Re: [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith*

On Wed, Aug 18, 2021 at 5:23 AM Richard Henderson wrote: > > Most arithmetic does not require extending the inputs. > Exceptions include division, comparison and minmax. > > Begin using ctx->w, which allows elimination of gen_addw, > gen_subw, gen_mulw. > > Signed-off-by: Richard Henderson > ---

Re: [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers

On 8/18/21 12:58 AM, Bin Meng wrote: +TCGv temp[4]; Why is 4? Is it enough? Perhaps a comment here is needed here? It's a round number that will cover three operands plus an extra for address computation. r~

[PATCH v2] net/colo: check vnet_hdr_support flag when using virtio-net

When COLO use only one vnet_hdr_support parameter between COLO network filter(filter-mirror, filter-redirector or filter-rewriter and colo-compare, packet will not be parsed correctly. Acquire network driver related to COLO, if it is nirtio-net, check vnet_hdr_support flag of COLO network filter

Re: [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers

On 8/18/21 12:58 AM, Bin Meng wrote: +static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) +{ +if (reg_num != 0) { +if (ctx->w) { +tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); What about zero extension? All of the RV64 word instructions sign-extend the result.

Re: [PATCH v2 2/3] target/riscv: update Zb[abcs] to 1.0.0 (public review) specification

On 8/18/21 10:32 AM, Philipp Tomsich wrote: The ratification package for Zb[abcs] does not contain all instructions that have been added to QEmu and don't define misa.B for these: the individual extensions are now Zba, Zbb, Zbc and Zbs. Some of the instructions that had previously been added

Re: [PATCH v2] hw/intc/sifive_clint: Fix overflow in sifive_clint_write_timecmp()

On Tue, Aug 17, 2021 at 6:00 PM Bin Meng wrote: > > On Tue, Aug 17, 2021 at 2:38 AM David Hoppenbrouwers > wrote: > > > > `next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This > > resulted in high values such as `UINT64_MAX` being converted to `-1`, > > which caused an

Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

I will provide a v3 to restore bisectability, On Thu, 19 Aug 2021 at 00:39, Richard Henderson < richard.hender...@linaro.org> wrote: > On 8/18/21 10:32 AM, Philipp Tomsich wrote: > > +++ b/target/riscv/cpu.h > > @@ -67,7 +67,6 @@ > > #define RVS RV('S') > > #define RVU RV('U') > > #define

Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

On 8/18/21 10:32 AM, Philipp Tomsich wrote: +++ b/target/riscv/cpu.h @@ -67,7 +67,6 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') -#define RVB RV('B') This patch does not compile by itself, because RVB is still used in insn_trans/trans_rvb.c.inc. r~

Re: [PATCH v2 2/5] target/mips: Replace GET_LMASK() macro by get_lmask(32) function

On 8/18/21 11:55 AM, Philippe Mathieu-Daudé wrote: The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove one use of the

Re: [PATCH v2 3/5] target/mips: Replace GET_LMASK64() macro by get_lmask(64) function

On 8/18/21 11:55 AM, Philippe Mathieu-Daudé wrote: The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove another use of

Re: [PATCH v2 1/5] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers

On 8/18/21 11:55 AM, Philippe Mathieu-Daudé wrote: The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. As a first step, inline the GET_OFFSET() macro, calling cpu_is_bigendian() to get the 'direction' of the offset. Signed-off-by: Philippe

Re: [PATCH 1/5] target/mips: Replace GET_OFFSET() macro by get_offset() function

On 8/18/21 11:31 AM, Philippe Mathieu-Daudé wrote:   I think you should drop get_offset() entirely and replace it with     int dir = cpu_is_bigendian(env) ? 1 : -1;     stb(env, arg2 + 1 * dir, data);     stb(env, arg2 + 2 * dir, data); Alternately, bite the bullet and split the

Re: [PATCH v3 09/16] tcg/mips: Drop special alignment for code_gen_buffer

On 8/18/21 10:19 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/region.c | 91 > 1 file changed, 91 deletions(-) Yay! Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 08/16] tcg/mips: Unset TCG_TARGET_HAS_direct_jump

On 8/18/21 10:19 PM, Richard Henderson wrote: > Only use indirect jumps. Finish weaning away from the > unique alignment requirements for code_gen_buffer. > > Signed-off-by: Richard Henderson > --- > tcg/mips/tcg-target.h | 12 +--- > tcg/mips/tcg-target.c.inc | 23

Re: [PATCH v3 05/16] tcg/mips: Move TCG_GUEST_BASE_REG to S7

On 8/18/21 10:19 PM, Richard Henderson wrote: > No functional change; just moving the saved reserved regs to the end. > > Signed-off-by: Richard Henderson > --- > tcg/mips/tcg-target.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/mips/tcg-target.c.inc

Re: [PATCH v3 04/16] tcg/mips: Move TCG_AREG0 to S8

On 8/18/21 10:19 PM, Richard Henderson wrote: > No functional change; just moving the saved reserved regs to the end. > > Signed-off-by: Richard Henderson > --- > tcg/mips/tcg-target.h | 2 +- > tcg/mips/tcg-target.c.inc | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-)

Re: [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup

Sorry, use Huacai's newer email . On Thu, Aug 19, 2021 at 12:07 AM Philippe Mathieu-Daudé wrote: > > Cc'ing Jiaxun & Huacai. > > On 8/18/21 10:19 PM, Richard Henderson wrote: > > Based-on: <20210818191920.390759-1-richard.hender...@linaro.org> > > ("[PATCH v3 00/66] Unaligned access for

Re: [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup

Cc'ing Jiaxun & Huacai. On 8/18/21 10:19 PM, Richard Henderson wrote: > Based-on: <20210818191920.390759-1-richard.hender...@linaro.org> > ("[PATCH v3 00/66] Unaligned access for user-only") > > Important points: > * Support unaligned accesses. > * Drop requirement for 256MB alignment of

Re: [PATCH v3 12/14] tcg/arm: More use of the TCGReg enum

On 8/18/21 11:29 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c.inc | 65 +--- > 1 file changed, 35 insertions(+), 30 deletions(-) I like it :) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 11/14] tcg/arm: More use of the ARMInsn enum

On 8/18/21 11:29 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c.inc | 20 ++-- > 1 file changed, 10 insertions(+), 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 10/14] tcg/arm: Give enum arm_cond_code_e a typedef and use it

On 8/18/21 11:29 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c.inc | 136 +++ > 1 file changed, 68 insertions(+), 68 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 09/14] tcg/arm: Drop inline markers

On 8/18/21 11:29 PM, Richard Henderson wrote: > Let the compiler decide about inlining. > Remove tcg_out_nop as unused. > > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c.inc | 234 +++ > 1 file changed, 114 insertions(+), 120 deletions(-)

Re: [PATCH v3 02/14] tcg/arm: Standardize on tcg_out__{reg,imm}

On 8/18/21 11:29 PM, Richard Henderson wrote: > Some of the functions specified _reg, some _imm, and some > left it blank. Make it clearer to which we are referring. > > Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when > we do not actually require BX semantics. > > Signed-off-by:

[PATCH v2 4/5] target/mips: Store CP0_Config0 in DisasContext

Most TCG helpers only have access to a DisasContext pointer, not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0 in DisasContext so we can access it from TCG helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id:

[PATCH v2 5/5] target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()

Add the inlined cpu_is_bigendian() function in "translate.h". Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to cpu_is_bigendian(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210818164321.2474534-6-f4...@amsat.org> ---

[PATCH v2 3/5] target/mips: Replace GET_LMASK64() macro by get_lmask(64) function

The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove another use of the TARGET_WORDS_BIGENDIAN definition.

[PATCH v2 2/5] target/mips: Replace GET_LMASK() macro by get_lmask(32) function

The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove one use of the TARGET_WORDS_BIGENDIAN definition. Signed-off-by:

[PATCH v2 1/5] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers

The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. As a first step, inline the GET_OFFSET() macro, calling cpu_is_bigendian() to get the 'direction' of the offset. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/ldst_helper.c | 55

[PATCH v2 0/5] target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()

Missing review: 1-3 MIPS CPU store its endianess in the CP0 Config0 register. Use that runtime information instead of #ifdef'ry checking TARGET_WORDS_BIGENDIAN by introducing the cpu_is_bigendian() helper. Since v1: - Addressed rth's comments (call cpu_is_bigendian/get_lmask once) - Add rth R-b

Re: [PATCH 1/5] target/mips: Replace GET_OFFSET() macro by get_offset() function

On 8/18/21 6:56 PM, Richard Henderson wrote: > On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote: >> The target endianess information is stored in the BigEndian >> bit of the Config0 register in CP0. >> >> As a first step, replace the GET_OFFSET() macro by an inlined >> get_offset() function,

[PATCH v3 12/14] tcg/arm: More use of the TCGReg enum

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 65 +--- 1 file changed, 35 insertions(+), 30 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2f55b94ada..35bd4c68d6 100644 --- a/tcg/arm/tcg-target.c.inc +++

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On 8/18/21 3:04 PM, Dr. David Alan Gilbert wrote: * Tobin Feldman-Fitzthum (to...@linux.ibm.com) wrote: On 8/17/21 6:04 PM, Steve Rutherford wrote: Ahh, It sounds like you are looking into sidestepping the existing AMD-SP flows for migration. I assume the idea is to spin up a VM on the target

[PATCH v3 14/14] tcg/arm: Support raising sigbus for user-only

For v6+, use ldm/stm, ldrd/strd for the normal case of alignment matching the access size. Otherwise, emit a test + branch sequence invoking helper_unaligned_{ld,st}. For v4+v5, use piecewise load and stores to implement misalignment. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h

[PATCH v3 05/14] tcg/arm: Examine QEMU_TCG_DEBUG environment variable

Use the environment variable to test an older ISA from the one supported by the host. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 8 +++- tcg/arm/tcg-target.c.inc | 32 2 files changed, 39 insertions(+), 1 deletion(-) diff --git

[PATCH v3 11/14] tcg/arm: More use of the ARMInsn enum

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b20c313615..2f55b94ada 100644 --- a/tcg/arm/tcg-target.c.inc +++

[PATCH v3 02/14] tcg/arm: Standardize on tcg_out__{reg,imm}

Some of the functions specified _reg, some _imm, and some left it blank. Make it clearer to which we are referring. Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when we do not actually require BX semantics. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 38

[PATCH v3 08/14] tcg/arm: Simplify usage of encode_imm

We have already computed the rotated value of the imm8 portion of the complete imm12 encoding. No sense leaving the combination of rot + rotation to the caller. Create an encode_imm12_nofail helper that performs an assert. This removes the final use of the local "rotl" function, which

[PATCH v3 10/14] tcg/arm: Give enum arm_cond_code_e a typedef and use it

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 136 +++ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 327032f0df..b20c313615 100644 --- a/tcg/arm/tcg-target.c.inc +++

[PATCH v3 04/14] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call

ARMv4T has BX as its only interworking instruction. In order to support testing of different architecture revisions with a qemu binary that may have been built for, say ARMv6T2, fill in the blank required to make calls to helpers in thumb mode. Signed-off-by: Richard Henderson ---

[PATCH v3 07/14] tcg/arm: Split out tcg_out_ldstm

Expand these hard-coded instructions symbolically. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c55167cc84..63b786a3e5 100644 ---

Re: [PATCH 2/5] target/mips: Replace GET_LMASK() macro by get_lmask(32) function

On 8/18/21 7:09 PM, Richard Henderson wrote: > On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote: >> -    if (GET_LMASK(arg2) <= 2) { >> +    if (get_lmask(env, arg2, 32) <= 2) { > > Whatever you decide to do with respect to the previous patch, the result > of get_lmask is constant across the

[PATCH v3 09/14] tcg/arm: Drop inline markers

Let the compiler decide about inlining. Remove tcg_out_nop as unused. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 234 +++ 1 file changed, 114 insertions(+), 120 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc

[PATCH v3 00/14] tcg/arm: Unaligned access and other cleanup

Based-on: <20210818191920.390759-1-richard.hender...@linaro.org> ("[PATCH v3 00/66] Unaligned access for user-only") Important points: * Support unaligned accesses. * Add environment variable to for testing older architecture revs. * More use of enum types. r~ Richard Henderson (14):

[PATCH v3 06/14] tcg/arm: Support unaligned access for softmmu

>From armv6, the architecture supports unaligned accesses. All we need to do is perform the correct alignment check in tcg_out_tlb_read and not use LDRD/STRD when the access is not aligned. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 69

[PATCH v3 03/14] tcg/arm: Simplify use_armvt5_instructions

According to the Arm ARM DDI 0406C, section A1.3, the valid variants are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb. Therefore simplify the test from preprocessor ifdefs to base architecture revision. Retain the "t" in the name to minimize churn. Signed-off-by: Richard

[PATCH v3 13/14] tcg/arm: Reserve a register for guest_base

Reserve a register for the guest_base using aarch64 for reference. By doing so, we do not have to recompute it for every memory load. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 39 --- 1 file changed, 28 insertions(+), 11 deletions(-)

[PATCH v3 01/14] tcg/arm: Remove fallback definition of __ARM_ARCH

GCC since 4.8 provides the definition and we now require 7.5. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 19 --- 1 file changed, 19 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index d113b7f8db..18bb16c784 100644 ---

Re: [PATCH v3 64/66] tcg: Canonicalize alignment flags in MemOp

On 8/18/21 9:19 PM, Richard Henderson wrote: > Having observed e.g. al8+leq in dumps, canonicalize to al+leq. > > Signed-off-by: Richard Henderson > --- > tcg/tcg-op.c | 7 ++- > 1 file changed, 6 insertions(+), 1 deletion(-) Nice. Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 58/66] include/exec: Move cpu_signal_handler declaration

On 8/18/21 9:19 PM, Richard Henderson wrote: > There is nothing target specific about this. The implementation > is host specific, but the declaration is 100% common. > > Signed-off-by: Richard Henderson > --- > include/exec/exec-all.h | 13 + > target/alpha/cpu.h | 6 --

Re: [PATCH v3 57/66] accel/tcg/user-exec: Convert DEBUG_SIGNAL to tracepoint

On 8/18/21 9:19 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > accel/tcg/user-exec.c | 9 +++-- > accel/tcg/trace-events | 3 +++ > 2 files changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 52/66] target/alpha: Reorg fp memory operations

On 8/18/21 9:19 PM, Richard Henderson wrote: > Pass in the context to each mini-helper, instead of an > incorrectly named "flags". Separate gen_load_fp and > gen_store_fp, away from the integer helpers. > > Signed-off-by: Richard Henderson > --- > target/alpha/translate.c | 83

Re: [PATCH v3 48/66] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass

On 8/18/21 9:19 PM, Richard Henderson wrote: > Despite the comment, the members were not kept at the end. > > Signed-off-by: Richard Henderson > --- > include/hw/core/cpu.h | 11 +++ > 1 file changed, 7 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 22/66] accel/tcg: Drop signness in tracing in cputlb.c

On 8/18/21 9:18 PM, Richard Henderson wrote: > We are already inconsistent about whether or not > MO_SIGN is set in trace_mem_get_info. Dropping it > entirely allows some simplification. > > Signed-off-by: Richard Henderson > --- > accel/tcg/cputlb.c| 10 +++--- > accel/tcg/user-exec.c

Re: [PATCH v3 2/7] tcg/sparc: Introduce tcg_out_mov_delay

On 8/18/21 10:45 PM, Richard Henderson wrote: > This version of tcg_out_mov is emits a nop to fill the > delay slot if the move is not required. > > The only current use, for INDEX_op_goto_ptr, will always > require the move but properly documents the delay slot. > > Signed-off-by: Richard

Re: [PATCH v3 1/7] tcg/sparc: Drop inline markers

On 8/18/21 10:45 PM, Richard Henderson wrote: > Let the compiler decide about inlining. > > Signed-off-by: Richard Henderson > --- > tcg/sparc/tcg-target.c.inc | 45 +++--- > 1 file changed, 22 insertions(+), 23 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 03/16] tcg/mips: Drop inline markers

On 8/18/21 10:19 PM, Richard Henderson wrote: > Let the compiler decide about inlining. > Remove tcg_out_ext8s and tcg_out_ext16s as unused. > > Signed-off-by: Richard Henderson > --- > tcg/mips/tcg-target.c.inc | 76 ++- > 1 file changed, 27 insertions(+),

[PATCH v3 4/7] tcg/sparc: Improve code gen for shifted 32-bit constants

We had code for checking for 13 and 21-bit shifted constants, but we can do better and allow 32-bit shifted constants. This is still 2 insns shorter than the full 64-bit sequence. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 12 ++-- 1 file changed, 6 insertions(+),

[PATCH v3 3/7] tcg/sparc: Add scratch argument to tcg_out_movi_int

This will allow us to control exactly what scratch register is used for loading the constant. Also, fix a theoretical problem in recursing through tcg_out_movi, which may provide a different value for in_prologue. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 20

[PATCH v3 7/7] tcg/sparc: Support unaligned access for user-only

This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. This inline code expansion is somewhat large, but it takes quite a few instructions to make a function call to a helper

[PATCH v3 2/7] tcg/sparc: Introduce tcg_out_mov_delay

This version of tcg_out_mov is emits a nop to fill the delay slot if the move is not required. The only current use, for INDEX_op_goto_ptr, will always require the move but properly documents the delay slot. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 21

[PATCH v3 6/7] tcg/sparc: Add tcg_out_jmpl_const for better tail calls

Due to mapping changes, we now rarely place the code_gen_buffer near the main executable. Which means that direct calls will now rarely be in range. So, always use indirect calls for tail calls, which allows us to avoid clobbering %o7, and therefore we need not save and restore it.

[PATCH v3 1/7] tcg/sparc: Drop inline markers

Let the compiler decide about inlining. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 45 +++--- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index

[PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

The 1.0.0 (public review) version of the RISC-V bitmanip-instructions does not define a B-extension, but rather 4 separate Zb[abcs] extensions. Signed-off-by: Philipp Tomsich --- (no changes since v1) target/riscv/cpu.c | 31 --- target/riscv/cpu.h | 7 --- 2

[PATCH v3 5/7] tcg/sparc: Use the constant pool for 64-bit constants

Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 15 +++ 1 file changed, 15 insertions(+) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 16e2258b9b..b64760e736 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@

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