Hi,
> This also seems to me to be the tail wagging the dog. If we think
> 'info mtree' has too much duplicate information (which it certainly
> does) then we should make mtree_info() smarter about reducing that
> duplication. Off the top of my head, we could change the code that
> prints ASes to
The AVX_VNNI feature is not in Cooperlake platform, remove it
from cpu model.
Signed-off-by: Yang Zhong
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 34a7ce865b..24ddc5b926 100644
--- a/target/i386/cpu.c
+++
The current SMMU V3 device model only support PCI/PCIe devices,
so we update it to support non-PCI/PCIe devices.
hw/arm/smmuv3:
. Create IOMMU memory regions for non-PCI/PCIe devices based on their
SID
. Add sid-map property to store non-PCI/PCIe devices SID
. Update i
On Mon, Aug 9, 2021 at 3:00 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/7/21 11:42 AM, Warner Losh wrote:
> > +static inline int setup_initial_stack(struct bsd_binprm *bprm,
> > +abi_ulong *ret_addr, abi_ulong *stringp)
> > +{
> > +int i;
> > +abi_ulong stack
在 2021/7/13 下午11:37, Andrew Melnychenko 写道:
Libvirt usually launches qemu with strict permissions.
To enable eBPF RSS steering, qemu-ebpf-rss-helper was added.
Added property "ebpf_rss_fds" for "virtio-net" that allows to
initialize eBPF RSS context with passed program & maps fds.
Added qemu-
在 2021/7/13 下午11:37, Andrew Melnychenko 写道:
Helper program. Loads eBPF RSS program and maps and passes them through unix
socket.
Libvirt may launch this helper and pass eBPF fds to qemu virtio-net.
I wonder if this can be done as helper for TAP/bridge.
E.g it's the qemu to launch those hel
在 2021/7/13 下午11:37, Andrew Melnychenko 写道:
eBPF RSS program and maps now may be passed during initialization.
Initially was implemented for libvirt to launch qemu without permissions.
Signed-off-by: Andrew Melnychenko
---
hw/net/virtio-net.c| 77
在 2021/7/13 下午11:37, Andrew Melnychenko 写道:
-static bool ebpf_rss_set_indirections_table(struct EBPFRSSContext *ctx,
-uint16_t *indirections_table,
-size_t len)
-{
-uint32_t i = 0;
+ctx->program_fd =
> On Aug 10, 2021, at 11:27 AM, Richard Henderson
> wrote:
>
> On 8/7/21 11:42 AM, Warner Losh wrote:
>> From: Warner Losh
>> Add a stubbed-out version of the bsd-user fork's core dump support. This
>> allows elfload.c to be almost the same between what's upstream and
>> what's in qemu-projec
On Wed, Aug 18, 2021 at 08:01:03AM +0200, Klaus Jensen wrote:
On Aug 3 12:54, Padmakar Kalghatgi wrote:
From: padmakar
This patch contains the implementation of certain commands
of nvme-mi specification.The MI commands are useful to
manage/configure/monitor the device.Eventhough the MI comman
On 2021/8/19 21:50, Cornelia Huck wrote:
On Thu, Aug 19 2021, Yanan Wang wrote:
There are two places describing the same thing about deprecation
of invalid topologies of -smp CLI, so remove the duplicated one.
Signed-off-by: Yanan Wang
---
docs/about/removed-features.rst | 13 ---
Unify the subject format in deprecated.rst to "since X.Y".
Unify the subject format in removed-features.rst to "removed in X.Y".
Signed-off-by: Yanan Wang
---
docs/about/deprecated.rst | 56 -
docs/about/removed-features.rst | 28 -
2 files c
There are two places describing the same thing about deprecation
of invalid topologies of -smp CLI, so remove the duplicated one.
Signed-off-by: Yanan Wang
Reviewed-by: Cornelia Huck
---
docs/about/removed-features.rst | 13 -
1 file changed, 13 deletions(-)
diff --git a/docs/about
These two patches (one of which has been reviewed) originally come from [1].
Here resend them separately as a short doc clean-up series.
[1]
https://lore.kernel.org/qemu-devel/20210819031027.41104-1-wangyana...@huawei.com/
Yanan Wang (2):
docs/about: Remove the duplicated doc
docs/about: Uni
On Thu, Aug 19, 2021 at 7:08 PM Richard Henderson
wrote:
>
> Move these helpers near their use by the trans_*
> functions within insn_trans/trans_rvm.c.inc.
>
> Reviewed-by: Bin Meng
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alista
> On Aug 10, 2021, at 9:18 AM, Richard Henderson
> wrote:
>
> On 8/7/21 11:42 AM, Warner Losh wrote:
>> From: Warner Losh
>> Rewrite target definnitions to interface with the FreeBSD system calls.
>> This covers basic types (time_t, iovec, umtx_time, timespec, timeval,
>> rusage, rwusage) and
On 8/19/21 2:42 AM, Peter Maydell wrote:
Maybe we should fix this by making the 'struct Int128' field order
depend on HOST_WORDS_BIGENDIAN...
Yes, I think so.
At some point I had a notion of supporting Int128 natively in TCG, at least as far as data
movement and the host function call abi.
On 8/19/21 9:37 PM, Andrew Jones wrote:
> Allow CPUs that support SVE to specify which SVE vector lengths they
> support by setting them in this bitmap. Currently only the 'max' and
> 'host' CPU types supports SVE and 'host' requires KVM which obtains
> its supported bitmap from the host. So, we on
On 8/19/21 9:37 PM, Andrew Jones wrote:
> bitmap_clear() only clears the given range. While the given
> range should be sufficient in this case we might as well be
> 100% sure all bits are zeroed by using bitmap_zero().
>
> Signed-off-by: Andrew Jones
> ---
> target/arm/kvm64.c | 2 +-
> 1 file
On Fri, Aug 20, 2021 at 2:35 AM Philippe Mathieu-Daudé
wrote:
>
> If some property are not set, we'll return indicating a failure,
> so it is pointless to allocate / initialize some fields too early.
> Move the trivial checks earlier in realize().
>
> Signed-off-by: Philippe Mathieu-Daudé
Review
On Fri, Aug 20, 2021 at 2:35 AM Philippe Mathieu-Daudé
wrote:
>
> If we link QOM object (a) as a property of QOM object (b),
> we must set the property *before* (b) is realized.
>
> Move QSPI realization *after* QSPI DMA.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
On Thu, 2021-08-19 at 15:28 +0100, Dr. David Alan Gilbert wrote:
> * James Bottomley (j...@linux.ibm.com) wrote:
> > On Thu, 2021-08-19 at 09:22 +0100, Dr. David Alan Gilbert wrote:
[...]
> > > I think it really does have to cope with migration to a new
> > > version of host.
> >
> > Well, you're
On 8/19/21 9:24 AM, Peter Maydell wrote:
(Did you check the M-profile code too? That also architecturally I think
should never let PC have the low bit set; hopefully the code I wrote
actually ensures that...)
Exception handling in m-profile is much harder to follow, but certainly normal updates
On Thu, 19 Aug 2021 at 20:18, Peter Maydell wrote:
> Just noticed that section G1.16.7 says that when we report
> PC alignment faults to AArch32 they should be prefetch aborts,
> not UDEF. The fault address and fault status registers also need
> to be set (with slightly varying behaviour for when
Now that we have an ARMCPU member sve_vq_supported we no longer
need the local kvm_supported bitmap for KVM's supported vector
lengths.
Signed-off-by: Andrew Jones
---
target/arm/cpu64.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu64.c b
On 19/08/2021 09:42, Peter Maydell wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa
confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail
suspeito entre imediatamente em contato com o DTI.
On Wed, 18 Aug 2021 at 12:11, wrote:
From: Matheu
Future CPU types may specify which vector lengths are supported.
We can apply nearly the same logic to validate those lengths
as we do for KVM's supported vector lengths. We merge the code
where we can, but unfortunately can't completely merge it because
KVM requires all vector lengths, power-of-tw
Allow CPUs that support SVE to specify which SVE vector lengths they
support by setting them in this bitmap. Currently only the 'max' and
'host' CPU types supports SVE and 'host' requires KVM which obtains
its supported bitmap from the host. So, we only need to initialize the
bitmap for 'max' with
bitmap_clear() only clears the given range. While the given
range should be sufficient in this case we might as well be
100% sure all bits are zeroed by using bitmap_zero().
Signed-off-by: Andrew Jones
---
target/arm/kvm64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tar
While reviewing the new A64FX CPU type it became clear that CPU
types should be able to specify which SVE vector lengths are
supported. This series adds a new bitmap member to ARMCPU and
modifies arm_cpu_sve_finalize() to validate inputs against it.
So far we only need to set the bitmap for the 'ma
On Tue, 3 Aug 2021 at 05:18, Richard Henderson
wrote:
>
> Cc: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> linux-user/mips/cpu_loop.c| 20
> target/mips/cpu.c | 2 +-
> target/mips/tcg/op_helper.c | 3 +--
> target/mips/t
On 8/19/21 6:06 AM, Peter Maydell wrote:
On Wed, 18 Aug 2021 at 20:39, Richard Henderson
wrote:
Since the prctl constants are supposed to be generic, supply
any that are not provided by the host.
Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE,
PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR
On Thu, 19 Aug 2021 at 17:57, Richard Henderson
wrote:
>
> On 8/19/21 6:50 AM, Richard Henderson wrote:
> > On 8/19/21 3:40 AM, Peter Maydell wrote:
> >>> uint32_t insn;
> >>> bool is_16bit;
> >>>
> >>> -if (arm_pre_translate_insn(dc)) {
> >>> +if (arm_check_ss_active(dc) || ar
On 8/19/21 5:46 AM, Peter Maydell wrote:
On Wed, 18 Aug 2021 at 20:26, Richard Henderson
wrote:
Cc: Yoshinori Sato
Signed-off-by: Richard Henderson
---
linux-user/sh4/cpu_loop.c | 8
target/sh4/cpu.c | 2 +-
target/sh4/op_helper.c| 3 ---
3 files changed, 9 inserti
On Wed, 18 Aug 2021 at 02:04, Richard Henderson
wrote:
>
> For A64, any input to an indirect branch can cause this.
>
> For A32, many indirect branch paths force the branch to be aligned,
> but BXWritePC does not. This includes the BX instruction but also
> other interworking changes to PC. Prio
On 8/19/21 5:39 AM, Peter Maydell wrote:
cpu_ldl_code() in the unaligned-access handler is strictly speaking
bogus, because the page might have been unmapped after translation
but before we got round to actually running it. Better would be to
stash the relevant bits of info from the insn in the i
On Thu, Aug 19, 2021 at 05:14:30PM +0200, Hanna Reitz wrote:
> On 19.08.21 16:31, Jose R. Ziviani wrote:
> > Hello Hanna,
> >
> > On Thu, Aug 19, 2021 at 12:12:00PM +0200, Hanna Reitz wrote:
> > > We cannot write to images opened with O_DIRECT unless we allow them to
> > > be resized so they are a
On Sat, Jul 24, 2021 at 04:38:46PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> There is no conflict and no dependency if we have parallel writes to
> different subclusters of one cluster when cluster itself is already
when the cluster itself
> allocated. So, relax extra dependency.
>
> Measure
On Sat, Jul 24, 2021 at 04:38:45PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> No logic change, just prepare for the following commit.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> block/qcow2-cluster.c | 49 ---
> 1 file changed, 28 insertions(
Add syntax highlighting for the incoming and outgoing QMP messages.
This is achieved using the pygments module which was added in a
previous commit.
The current implementation is a really simple one which doesn't
allow for any configuration. In future this has to be improved
to allow for easier th
Added pygments as optional dependency for AQMP TUI.
This is required for the upcoming syntax highlighting feature
in AQMP TUI.
The dependency has also been added in the devel optional group.
Added mypy 'ignore_missing_imports' for pygments since it does
not have any type stubs.
Signed-off-by: G S
The connection manager will take care of connecting/disconnecting
to the server. This will also try to reconnect to the server in
certain situations where the client has been disconnected due to
some error condition.
Signed-off-by: G S Niteesh Babu
---
python/qemu/aqmp/aqmp_tui.py | 127
Added dependencies for the upcoming AQMP TUI under the optional
'tui' group.
The same dependencies have also been added under the devel group
since no work around has been found for optional groups to imply
other optional groups.
Signed-off-by: G S Niteesh Babu
---
python/Pipfile.lock | 12
Add an entry point for aqmp-tui. This will allow it to be run from
the command line using "aqmp-tui localhost:1234"
More options available in the TUI can be found using "aqmp-tui -h"
Signed-off-by: G S Niteesh Babu
---
python/setup.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git a/python/s
Added a draft of AQMP TUI.
Implements the follwing basic features:
1) Command transmission/reception.
2) Shows events asynchronously.
3) Shows server status in the bottom status bar.
Also added type annotations and necessary pylint,
mypy configurations
Signed-off-by: G S Niteesh Babu
---
pytho
Disable missing-docstring and fixme pylint warnings.
This is because since the AQMP is just a prototype
it is currently not documented properly and lot
of todo and fixme's are still in place.
Signed-off-by: G S Niteesh Babu
---
python/setup.cfg | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hello all,
Gitlab: https://gitlab.com/niteesh.gs/qemu/-/commits/aqmp-tui-prototype-v4
CI: https://gitlab.com/niteesh.gs/qemu/-/pipelines/356024270
Revision since v3:
1) Added docstrings
2) Minor changes in AQMP TUI Draft
3) Switched to constant retry delay in QMP connection manager and other
m
On 8/19/21 1:00 AM, Bin Meng wrote:
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
{
-TCGv cond1, cond2, zeroreg, resultopt1;
+TCGv temp1, temp2, zero, one, mone, min;
-cond1 = tcg_temp_new();
-cond2 = tcg_temp_new();
-zeroreg = tcg_constant_tl(0);
-resulto
pci_get_address_space() returns an AddressSpace. In some
cases we want a MemoryRegion. Add the pci_dma_memory_region()
equivalent helper.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/
Simplify by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
removing need for heap allocation.
Update the MicroVM machine to pass the default system memory instead
of a NULL value.
We don't need to change the Versal machine,
Do not ignore eventual error if we failed at setting the 'host'
property of the TYPE_XHCI model.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-xhci-pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
index e934b1a5b1f..71
Simplify the XHCI based devices by always passing a MemoryRegion
property to the device. Doing so we can move the AddressSpace
field to the device struct, removing need for heap allocation.
Philippe Mathieu-Daudé (3):
hw/pci: Introduce pci_dma_memory_region() helper
hw/usb/hcd-xhci-pci: Abort
On 8/19/21 6:50 AM, Richard Henderson wrote:
On 8/19/21 3:40 AM, Peter Maydell wrote:
uint32_t insn;
bool is_16bit;
- if (arm_pre_translate_insn(dc)) {
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
Is it not possible to get a misaligned PC in the Thumb case ?
On Thu, Aug 19, 2021 at 04:26:10PM +0100, Peter Maydell wrote:
> On Wed, 18 Aug 2021 at 21:09, Richard Henderson
> wrote:
> >
> > The comment in cpu-common.c is absolutely correct, we can't
> > rely on the ifdef in a file built once. This was only "working"
> > because we used ifndef.
> >
> > Sig
On 8/19/21 3:40 AM, Peter Maydell wrote:
uint32_t insn;
bool is_16bit;
-if (arm_pre_translate_insn(dc)) {
+if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
Is it not possible to get a misaligned PC in the Thumb case ?
No. The thumb bit is always removed, leavi
On Thu, Aug 19, 2021 at 11:48:16AM -0400, John Snow wrote:
> On Thu, Aug 19, 2021 at 10:50 AM Eric Blake wrote:
>
> > On Wed, Aug 18, 2021 at 10:24:52AM -0400, John Snow wrote:
> > > > >
> > > > > +@upper_half
> > > > > +@require(Runstate.IDLE)
> > > > > +async def accept(self, addres
* Max Reitz (mre...@redhat.com) wrote:
> When the inode_file_handles option is set, try to generate a file handle
> for new inodes instead of opening an O_PATH FD.
>
> Being able to open these again will require CAP_DAC_READ_SEARCH, so the
> description text tells the user they will also need to s
On 24.07.21 15:38, Vladimir Sementsov-Ogievskiy wrote:
Add simple grammar-parsing template benchmark.
This doesn’t really say much, and FWIW, for like ten minutes I thought
this would do something completely different than it did (while I was
trying to parse the help text).
(I thought this
Simplify by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
removing need for heap allocation.
Update the Xilinx ZynqMP / Versal SoC models to pass the default
system memory instead of a NULL value.
Suggested-by: Peter Maydel
Simplify by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
removing need for heap allocation.
Update the Xilinx ZynqMP SoC model to pass the default system
memory instead of a NULL value.
Suggested-by: Peter Maydell
Signed-
If we link QOM object (a) as a property of QOM object (b),
we must set the property *before* (b) is realized.
Move QSPI realization *after* QSPI DMA.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/xlnx-zynqmp.c | 42 --
1 file changed, 20 insertions(+),
If some property are not set, we'll return indicating a failure,
so it is pointless to allocate / initialize some fields too early.
Move the trivial checks earlier in realize().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/dma/xlnx_csu_dma.c | 10 +-
1 file changed, 5 insertions(+), 5 de
Fix a qdev realization ordering, then simplify a pair of DMA
devices by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
removing need for heap allocation.
Philippe Mathieu-Daudé (4):
hw/arm/xlnx-zynqmp: Realize qspi controll
Since commit
36b79e3219d ("hw/acpi/Kconfig: Add missing Kconfig dependencies (build error)"),
ACPI_MEMORY_HOTPLUG and ACPI_NVDIMM is implicitly turned on when
ACPI_HW_REDUCED is selected. ACPI_HW_REDUCED is already enabled. No need to
turn on ACPI_MEMORY_HOTPLUG or ACPI_NVDIMM explicitly. This is a
On Thu, 19 Aug 2021 15:32:16 +
John Johnson wrote:
> > On Aug 17, 2021, at 7:04 PM, Alex Williamson
> > wrote:
> >
> >
> > The address/size paradigm falls into the same issues as the vfio kernel
> > interface where we can't map or unmap the entire 64-bit address space,
> > ie. size is lim
On Thu, Aug 19, 2021 at 12:25:01PM +0200, Hanna Reitz wrote:
> This post explains when FUSE block exports are useful, how they work,
> and that it is fun to export an image file on its own path so it looks
> like your image file (in whatever format it was) is a raw image now.
>
> Signed-off-by: Ha
Since commit
36b79e3219d ("hw/acpi/Kconfig: Add missing Kconfig dependencies (build error)",
ACPI_MEMORY_HOTPLUG and ACPI_NVDIMM is implicitly turned on when
ACPI_HW_REDUCED is selected. ACPI_HW_REDUCED is already enabled. No need to
turn on ACPI_MEMORY_HOTPLUG or ACPI_NVDIMM explicitly. This is a
On Wed, 18 Aug 2021 at 20:39, Richard Henderson
wrote:
>
> Since the prctl constants are supposed to be generic, supply
> any that are not provided by the host.
>
> Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE,
> PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL,
> PR_GET_TA
On Wed, 18 Aug 2021 at 20:38, Richard Henderson
wrote:
>
> A mostly generic test for unaligned access raising SIGBUS.
>
> Signed-off-by: Richard Henderson
> ---
> tests/tcg/multiarch/sigbus.c | 68
> 1 file changed, 68 insertions(+)
Reviewed-by: Peter Maydel
On Wed, 18 Aug 2021 at 21:11, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/i386/tcg-target.h | 2 -
> tcg/i386/tcg-target.c.inc | 107 --
> 2 files changed, 102 insertions(+), 7 deletions(-)
Reviewed-by: Peter Maydell
than
On Wed, 18 Aug 2021 at 21:03, Richard Henderson
wrote:
>
> To be called from tcg generated code on hosts that support
> unaligned accesses natively, in response to an access that
> is supposed to be aligned.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 18 Aug 2021 at 21:06, Richard Henderson
wrote:
>
> These functions are much closer to the softmmu helper
> functions, in that they take the complete MemOpIdx,
> and from that they may enforce required alignment.
>
> The previous cpu_ldst.h functions did not have alignment info,
> and so di
On Wed, 18 Aug 2021 at 20:51, Richard Henderson
wrote:
>
> We (will) often have the complete MemOpIdx handy, so use that.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, Aug 19, 2021 at 10:50 AM Eric Blake wrote:
> On Wed, Aug 18, 2021 at 10:24:52AM -0400, John Snow wrote:
> > > >
> > > > +@upper_half
> > > > +@require(Runstate.IDLE)
> > > > +async def accept(self, address: Union[str, Tuple[str, int]],
> > > > + ssl: Option
On Wed, 18 Aug 2021 at 20:26, Richard Henderson
wrote:
>
> Cc: Yoshinori Sato
> Signed-off-by: Richard Henderson
> ---
> linux-user/sh4/cpu_loop.c | 8
> target/sh4/cpu.c | 2 +-
> target/sh4/op_helper.c| 3 ---
> 3 files changed, 9 insertions(+), 4 deletions(-)
>
> diff -
On Wed, 18 Aug 2021 at 20:23, Richard Henderson
wrote:
>
> For simplicity on the linux-user side, always use SPR_DAR.
>
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> linux-user/ppc/cpu_loop.c | 2 +-
> target/ppc/cpu_init.c | 2 +-
> target/ppc/excp_helper.c | 2 ++
>
On Wed, 18 Aug 2021 at 20:33, Richard Henderson
wrote:
>
> We ought to have been recording the virtual address for reporting
> to the guest trap handler.
>
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> target/ppc/excp_helper.c | 14 ++
> 1 file changed, 14 inse
On Wed, 18 Aug 2021 at 20:24, Richard Henderson
wrote:
>
> By doing this while sending the exception, we will have already
> done the unwinding, which makes the ppc_cpu_do_unaligned_access
> code a bit cleaner.
>
> Update the comment about the expected instruction format.
>
> Signed-off-by: Richar
On Wed, 18 Aug 2021 at 20:27, Richard Henderson
wrote:
>
> Cc: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> linux-user/mips/cpu_loop.c| 20
> target/mips/cpu.c | 2 +-
> target/mips/tcg/op_helper.c | 3 +--
> target/mips/
On Wed, 18 Aug 2021 at 20:22, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/hppa/cpu_loop.c | 2 +-
> target/hppa/cpu.c | 9 ++---
> 2 files changed, 7 insertions(+), 4 deletions(-)
Reviewed-by: Peter Maydell
thanks
-- PMM
> On Aug 17, 2021, at 7:04 PM, Alex Williamson
> wrote:
>
>
> The address/size paradigm falls into the same issues as the vfio kernel
> interface where we can't map or unmap the entire 64-bit address space,
> ie. size is limited to 2^64 - 1. The kernel interface also requires
> PAGE_SIZE gra
On Wed, 18 Aug 2021 at 21:09, Richard Henderson
wrote:
>
> The comment in cpu-common.c is absolutely correct, we can't
> rely on the ifdef in a file built once. This was only "working"
> because we used ifndef.
>
> Signed-off-by: Richard Henderson
Fixes: 1b36e4f5a5de585
which moved the propert
> -Original Message-
> From: Philippe Mathieu-Daudé [mailto:phi...@redhat.com]
> Sent: 19 August 2021 15:50
> To: Ani Sinha
> Cc: Peter Maydell ; QEMU Developers
> ; qemu-arm ; Michael S.
> Tsirkin ; Igor Mammedov ;
> Shameerali Kolothum Thodi
> Subject: Re: [PATCH] hw/arm/Kconfig: no n
On 19.08.21 16:31, Jose R. Ziviani wrote:
Hello Hanna,
On Thu, Aug 19, 2021 at 12:12:00PM +0200, Hanna Reitz wrote:
We cannot write to images opened with O_DIRECT unless we allow them to
be resized so they are aligned to the sector size: Since 9c60a5d1978,
bdrv_node_refresh_perm() ensures that
On Wed, 18 Aug 2021 at 20:22, Richard Henderson
wrote:
>
> This seems to be either a glibc or gcc bug, but the code
> appears to be fine with the warning suppressed.
>
> Signed-off-by: Richard Henderson
> ---
> util/qemu-thread-posix.c | 19 +++
> 1 file changed, 19 insertions(+)
On 19.08.21 16:51, Christian Borntraeger wrote:
On 19.08.21 10:43, Christian Borntraeger wrote:
Interestingly enough this breaks my rpmbuild (both rpmbuild and mock).
(mostly with a modified f35 spec file):
cc -Isubprojects/libvhost-user/libvhost-user.a.p -Isubprojects/libvhost-user -I../s
On Wed, Aug 18, 2021 at 09:02:59PM -0700, Tong Ho wrote:
> This series implements the Xilinx eFUSE and BBRAM devices for
> the Versal and ZynqMP product families.
>
> Furthermore, both new devices are connected to the xlnx-versal-virt
> board and the xlnx-zcu102 board.
Hi Tong,
A few general com
On Thu, 19 Aug 2021 at 15:40, Philippe Mathieu-Daudé wrote:
>
> On 8/19/21 4:21 PM, Peter Maydell wrote:
> > On Thu, 19 Aug 2021 at 15:15, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Fixes: 35593573b25 ("hw/dma: Implement a Xilinx CSU DMA model")
> >> Signed-off-by: Philippe Mathieu-Daudé
> >>
On 19.08.21 10:43, Christian Borntraeger wrote:
Interestingly enough this breaks my rpmbuild (both rpmbuild and mock).
(mostly with a modified f35 spec file):
cc -Isubprojects/libvhost-user/libvhost-user.a.p -Isubprojects/libvhost-user
-I../subprojects/libvhost-user -fdiagnostics-color=auto -
On Wed, Aug 18, 2021 at 10:24:52AM -0400, John Snow wrote:
> > >
> > > +@upper_half
> > > +@require(Runstate.IDLE)
> > > +async def accept(self, address: Union[str, Tuple[str, int]],
> > > + ssl: Optional[SSLContext] = None) -> None:
> > > +"""
> > > +
Cc'ing Shameer Kolothum.
On 8/19/21 3:36 PM, Ani Sinha wrote:
> On Thu, 19 Aug 2021, Ani Sinha wrote:
>> On Thu, 19 Aug 2021, Peter Maydell wrote:
>>> On Tue, 17 Aug 2021 at 05:45, Ani Sinha wrote:
>>> Is it intended that ACPI_HW_REDUCED must always imply
>>> ACPI_MEMORY_HOTPLUG, or is it just a
On 8/19/21 4:38 PM, Peter Maydell wrote:
> On Thu, 19 Aug 2021 at 15:32, Philippe Mathieu-Daudé
> wrote:
>>
>> On 8/19/21 4:22 PM, Peter Maydell wrote:
>>> On Thu, 19 Aug 2021 at 15:21, Philippe Mathieu-Daudé
>>> wrote:
Replace g_malloc0() + address_space_init() by address_space_creat
On 8/19/21 4:34 PM, Peter Maydell wrote:
> On Thu, 19 Aug 2021 at 15:21, Philippe Mathieu-Daudé
> wrote:
>>
>> We already have a global AddressSpace created along with the
>> global get_system_memory(): address_space_memory. Return it
>> directly instead of creating the same AS with a different n
On 8/19/21 4:21 PM, Peter Maydell wrote:
> On Thu, 19 Aug 2021 at 15:15, Philippe Mathieu-Daudé
> wrote:
>>
>> Fixes: 35593573b25 ("hw/dma: Implement a Xilinx CSU DMA model")
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/dma/xlnx_csu_dma.c | 8
>> 1 file changed, 8 insertions(+
On Thu, 19 Aug 2021 at 15:32, Philippe Mathieu-Daudé wrote:
>
> On 8/19/21 4:22 PM, Peter Maydell wrote:
> > On Thu, 19 Aug 2021 at 15:21, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Replace g_malloc0() + address_space_init() by address_space_create().
> >> Release the resource in DeviceUnrealiz
On Thu, 19 Aug 2021 at 15:27, Philippe Mathieu-Daudé wrote:
>
> qdev_init_gpio_out() states it "creates an array of anonymous
> output GPIO lines" but doesn't document how this array is
> released. Add a note that it is automatically free'd in qdev
> instance_finalize().
>
> Signed-off-by: Philipp
On 8/19/21 4:24 PM, Peter Maydell wrote:
> On Thu, 19 Aug 2021 at 15:20, Philippe Mathieu-Daudé
> wrote:
>>
>> Introduce address_space_create(). In is similar to
>> address_space_init() but returns a pointer to a heap
>> allocated AddressSpace.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
On Aug 19 18:39, Naveen Nagar wrote:
> From: Naveen
>
> This patch supports namespace management : create and delete operations.
>
> Since v1:
> - Modified and moved nvme_ns_identify_common in ns.c file
> - Added check for CSI field in NS management
> - Indentation fix in namespace create
>
>
On Thu, 19 Aug 2021 at 15:21, Philippe Mathieu-Daudé wrote:
>
> We already have a global AddressSpace created along with the
> global get_system_memory(): address_space_memory. Return it
> directly instead of creating the same AS with a different name.
>
> diff --git a/softmmu/memory.c b/softmmu/
On 8/19/21 4:22 PM, Peter Maydell wrote:
> On Thu, 19 Aug 2021 at 15:21, Philippe Mathieu-Daudé
> wrote:
>>
>> Replace g_malloc0() + address_space_init() by address_space_create().
>> Release the resource in DeviceUnrealize().
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/dma/xlnx-zd
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