On Fri, Jan 14, 2022 at 06:46:10PM -0300, Fabiano Rosas wrote:
> David Gibson writes:
>
> > On Mon, Jan 10, 2022 at 03:15:40PM -0300, Fabiano Rosas wrote:
> >> Signed-off-by: Fabiano Rosas
> >> ---
> >> target/ppc/cpu_init.c | 2 ++
> >> 1 file changed, 2 insertions(+)
> >>
> >> diff --git
On Thu, Jan 13, 2022 at 12:43 PM Peter Maydell
wrote:
> On Sun, 9 Jan 2022 at 16:41, Warner Losh wrote:
> >
> > Implement conversion of host to target siginfo.
> >
> > Signed-off-by: Stacey Son
> > Signed-off-by: Kyle Evans
> > Signed-off-by: Warner Losh
> > ---
> > bsd-user/signal.c | 37
> -Original Message-
> From: Brian Cain
> Sent: Friday, October 1, 2021 7:23 PM
> To: Richard Henderson ; Alex Bennée
> ; qemu-devel@nongnu.org
> Cc: Taylor Simpson
> Subject: RE: hexagon container update
>
> > -Original Message-
> > From: Brian Cain
> ...
> > > -Original
On Thu, Jan 13, 2022 at 6:28 PM Philipp Tomsich
wrote:
>
> On Thu, 13 Jan 2022 at 06:07, Alistair Francis wrote:
> >
> > On Thu, Jan 13, 2022 at 1:42 AM Philipp Tomsich
> > wrote:
> > >
> > > Alistair,
> > >
> > > Do you (and the other RISC-V custodians of target/riscv) have any opinion
> > >
David Gibson writes:
> On Mon, Jan 10, 2022 at 03:15:40PM -0300, Fabiano Rosas wrote:
>> Signed-off-by: Fabiano Rosas
>> ---
>> target/ppc/cpu_init.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
>> index a50ddaeaae..9097948e67
On 1/14/22 3:38 PM, Matthew Rosato wrote:
Double-check I'm doing this right + test.
Argh... This should have been squashed into the preceding patch
'target/s390x: add zpci-interp to cpu models'
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-virtio-ccw.c | 1 +
1 file changed, 1
Idan Horowitz wrote:
>
> cbnz x9, 0x5168abc8
>
I forgot to include the addresses of the instructions, making this
jump undecipherable, here's the snippet again but with addresses this
time:
0x5168abb0 movkx0, #0x0
0x5168abb4 movkx0, #0x0, lsl #16
0x5168abb8 movkx0, #0xff80, lsl
On Fri, Jan 14, 2022 at 11:25 AM Peter Maydell
wrote:
> Fix a typo in a comment in the arm cpu_loop code.
>
> Signed-off-by: Peter Maydell
> ---
> linux-user/arm/cpu_loop.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Warner Losh
> diff --git
Use the associated vfio feature ioctl to enable adapter event notification
and forwarding for devices when requested. This feature will be set up
with or without firmware assist based upon the 'intassist' setting.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 24
Lack of MSI-X support is not an issue for interpreted passthrough
devices, so let's let these in. This will allow, for example, ISM
devices to be passed through -- but only when interpretation is
available and being used.
Reviewed-by: Thomas Huth
Reviewed-by: Pierre Morel
Signed-off-by:
Use the associated vfio feature ioctl to enable interpretation for devices
when requested. As part of this process, we must use the host function
handle rather than a QEMU-generated one -- this is provided as part of the
ioctl payload.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c
For QEMU, the majority of the work in enabling instruction interpretation
is handled via new VFIO ioctls to SET the appropriate interpretation and
interrupt forwarding modes, and to GET the function handle to use for
interpretive execution.
This series implements these new ioctls, as well as
This is a placeholder that pulls in 5.17 + unmerged kernel changes
required by this item. A proper header sync can be done once the
associated kernel code merges.
Signed-off-by: Matthew Rosato
---
include/standard-headers/asm-x86/kvm_para.h | 1 +
include/standard-headers/drm/drm_fourcc.h
When using the IOAT assist via interpretation, we should advertise what
the host driver supports, not QEMU.
Reviewed-by: Pierre Morel
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-vfio.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/s390x/s390-pci-vfio.c
Let's use the reserved pool of simulated PCI groups to allow intercept
devices to have separate groups from interpreted devices as some group
values may be different. If we run out of simulated PCI groups, subsequent
intercept devices just get the default group.
Furthermore, if we encounter any
Allow the underlying kvm host to handle the Refresh PCI Translation
instruction intercepts.
Reviewed-by: Pierre Morel
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 6 ++--
hw/s390x/s390-pci-inst.c | 51 ++--
hw/s390x/s390-pci-vfio.c
The zpci-interp feature is used to specify whether zPCI interpretation is
to be used for this guest.
Signed-off-by: Matthew Rosato
---
target/s390x/cpu_features_def.h.inc | 1 +
target/s390x/gen-features.c | 2 ++
target/s390x/kvm/kvm.c | 1 +
3 files changed, 4
Double-check I'm doing this right + test.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-virtio-ccw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 84e3e63c43..e02fe11b07 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++
On Mon, Jan 10, 2022 at 06:29:02PM -0500, John Snow wrote:
> Simply import the type defition from the new location.
definition
>
> Signed-off-by: John Snow
> Reviewed-by: Vladimir Sementsov-Ogievskiy
> Reviewed-by: Beraldo Leal
> ---
> tests/qemu-iotests/iotests.py | 2 +-
> 1 file changed,
On Thu, Jan 13, 2022 at 12:28 PM Peter Maydell
wrote:
> On Sun, 9 Jan 2022 at 16:29, Warner Losh wrote:
> >
> > Initialize the signal state for the emulator. Setup a set of sane
> > default signal handlers, mirroring the host's signals. For fatal signals
> > (those that exit by default),
On Thu, Jan 13, 2022 at 10:45 AM Peter Maydell
wrote:
> On Sun, 9 Jan 2022 at 16:29, Warner Losh wrote:
> >
> > Implement host_to_target_signal and target_to_host_signal.
> >
> > Signed-off-by: Stacey Son
> > Signed-off-by: Kyle Evans
> > Signed-off-by: Warner Losh
> > ---
> >
On Fri, 14 Jan 2022 at 18:14, Warner Losh wrote:
>
>
>
> On Thu, Jan 13, 2022 at 10:40 AM Peter Maydell
> wrote:
>>
>> On Sun, 9 Jan 2022 at 16:29, Warner Losh wrote:
>> >
>> > Update for the richer set of data faults that are now possible. Copied
>> > largely from linux-user/arm/cpu_loop.c
>>
Fix a typo in a comment in the arm cpu_loop code.
Signed-off-by: Peter Maydell
---
linux-user/arm/cpu_loop.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index f153ab503a8..032e1ffddfb 100644
---
On Thu, Jan 13, 2022 at 04:32:49PM +0100, Sebastian Hasler wrote:
> With the current implementation, blocking flock can lead to
> deadlock. Thus, it's better to return EOPNOTSUPP if a user attempts
> to perform a blocking flock request.
>
> Signed-off-by: Sebastian Hasler
Reviewed-by: Vivek
On Thu, Jan 13, 2022 at 10:40 AM Peter Maydell
wrote:
> On Sun, 9 Jan 2022 at 16:29, Warner Losh wrote:
> >
> > Update for the richer set of data faults that are now possible. Copied
> > largely from linux-user/arm/cpu_loop.c
> >
> > Signed-off-by: Warner Losh
> > ---
> >
This function does not use 'stack' anymore. Rename it to
pnv_pec_phb_update_map().
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
Split intersecting-requests functionality out of block-copy to be
reused in copy-before-write filter.
Note: while being here, fix tiny typo in MAINTAINERS.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/reqlist.h | 67
This patch changes the design of the PEC device to create and realize PHB4s
instead of PecStacks. After all the recent changes, PHB4s now contain all
the information needed for their proper functioning, not relying on PecStack
in any capacity.
All changes are being made in a single patch to avoid
'stack->stack_no' represents the order that a stack appears in its PEC.
Its primary use is in XSCOM address space calculation in
pnv_phb4_xscom_realize() when calculating the memory region offset.
This attribute is redundant with phb->phb_id, which is calculated via
pnv_phb4_pec_get_phb_id()
On Fri, Jan 14, 2022 at 05:05:56PM +0100, Halil Pasic wrote:
> On Thu, 13 Jan 2022 20:54:52 +0100
> Halil Pasic wrote:
>
> > > > This is the very reason for which commit 7ef7e6e3b ("vhost: correctly
> > > > turn on VIRTIO_F_IOMMU_PLATFORM") for, which fences _F_ACCESS_PLATFORM
> > > > form the
pnv_pec_default_phb_realize() stopped using it after the previous patch and
no one else is using it.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4_pec.c | 2 --
include/hw/pci-host/pnv_phb4.h | 3 ---
2 files changed, 5 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c
This property will track the owner PEC of this PHB. For now it's
redundant since we can retrieve the PEC via phb->stack->pec but it
will not be redundant when we get rid of the stack device.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c
This pointer was being used for two reasons: pnv_phb4_update_regions()
was using it to access the PHB and phb4_realize() was using it as a way
to determine if the PHB was user created.
We can determine if the PHB is user created via phb->pec, introduced in
the previous patch, and
All the complexity that was scattered between PnvPhb4PecStack and
PnvPHB4 are now centered in the PnvPHB4 device. PnvPhb4PecStack does not
serve any purpose in the current code base.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4_pec.c | 33
Move the current pnv_pec_stk_default_phb_realize() call to
pec_realize(), renaming the function to pnv_pec_default_phb_realize(),
and set the PHB attributes using the PEC object directly.
This will be important to allow for PECs devices to handle PHB4s
directly later on.
Reviewed-by: Cédric Le
Hi,
This second version contains improvements suggested by Cedric in the
v1 review.
Patches 1-10 from v1 are already accepted and aren't included in this
v2.
Changes from v1:
- v1 patches 1-10: already accepted, not included in the v2
- 'stack-stack_no' use is eliminated. We're now deriving
On Thu, Jan 13, 2022 at 04:55:11PM +, Daniel P. Berrangé wrote:
> Traditionally the OVMF firmware has been loaded using the pflash
> mechanism. This is because it is usually provided as a pair of
> files, one read-only containing the code and one writable to
> provided persistence of
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
Split block_copy_reset() out of block_copy_reset_unallocated() to be
used separately later.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block-copy.h | 1 +
block/block-copy.c | 21 +
2
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
This brings "incremental" mode to copy-before-write filter: user can
specify bitmap so that filter will copy only "dirty" areas.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json | 10 +-
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
This will be used in the following commit to bring "incremental" mode
to copy-before-write filter.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block-copy.h | 2 +-
block/block-copy.c | 14 --
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
We are going to complicate bitmap initialization in the further
commit. And in future, backup job will be able to work without filter
(when source is immutable), so we'll need same bitmap initialization in
copy-before-write filter and in
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
That simplifies handling failure in existing code and in further new
usage of bdrv_merge_dirty_bitmap().
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/dirty-bitmap.h| 2 +-
block/dirty-bitmap.c| 9
Alex Bennée wrote:
>
>
> For multi-patch series please include a cover letter which is the parent
> of all the patches. This is the default for git-send-email.
>
Sorry, I will do so from now on.
>
> The code itself looks fine but what sort of improvements are we talking
> about here? What
On Thu, 13 Jan 2022 20:54:52 +0100
Halil Pasic wrote:
> > > This is the very reason for which commit 7ef7e6e3b ("vhost: correctly
> > > turn on VIRTIO_F_IOMMU_PLATFORM") for, which fences _F_ACCESS_PLATFORM
> > > form the vhost device that does not need it, because on the vhost
> > > interface
Currently, we have to use OpenSBI firmware ELF as bios for the spike
machine because the HTIF console requires ELF for parsing "fromhost"
and "tohost" symbols.
The latest OpenSBI can now optionally pick-up HTIF register address
from HTIF DT node so using this feature spike machine can now use
Daniel P. Berrangé writes:
> On Fri, Jan 14, 2022 at 12:22:13PM +0100, Markus Armbruster wrote:
>> Nikita Lapshin writes:
>>
>> > If this capability is enabled migration stream
>> > will have RAM section only.
>> >
>> > Signed-off-by: Nikita Lapshin
>>
>> [...]
>>
>> > diff --git
On Fri, 14 Jan 2022 at 15:50, Peter Maydell wrote:
>
> In linux-user/signal.c we have two FIXME comments claiming that
> parts of the signal-handling code are not threadsafe. These are
> very old, as they were first introduced in commit 624f7979058
> in 2008. Since then we've radically overhauled
On 14/1/22 16:37, Peter Maydell wrote:
The linux-user queue_signal() function always returns 1, and none of
its callers check the return value. Give it a void return type
instead.
The return value is a leftover from the old pre-2016 linux-user
signal handling code, which really did have a
>
> are available in the Git repository at:
>
> git://git.kraxel.org/qemu tags/kraxel-20220114-pull-request
>
> for you to fetch changes up to 17f6315ef883a142b6a41a491b63a6554e784a5c:
>
> ui/input-legacy: pass horizontal scroll
Idan Horowitz writes:
> When the length of the range is large enough, clearing the whole cache is
> faster than iterating over the (possibly extremely large) set of pages
> contained in the range.
>
> This mimics the pre-existing similar optimization done on the flush of the
> tlb itself.
>
>
The linux-user queue_signal() function always returns 1, and none of
its callers check the return value. Give it a void return type
instead.
The return value is a leftover from the old pre-2016 linux-user
signal handling code, which really did have a queue of signals and so
might return a
In linux-user/signal.c we have two FIXME comments claiming that
parts of the signal-handling code are not threadsafe. These are
very old, as they were first introduced in commit 624f7979058
in 2008. Since then we've radically overhauled the signal-handling
logic, while carefully preserving these
The linux-user struct TaskState has an 'aligned(16)' attribute. When
the struct was first added in commit 851e67a1b46f in 2003, there was
a justification in a comment (still present in the source today):
/* NOTE: we force a big alignment so that the stack stored after is
aligned too */
In linux-user/signal.c we have two FIXME comments claiming that
parts of the signal-handling code are not threadsafe. These are
very old, as they were first introduced in commit 624f7979058
in 2008. Since then we've radically overhauled the signal-handling
logic, while carefully preserving these
On 14/1/22 12:32, Philippe Mathieu-Daudé wrote:
On 13/1/22 20:44, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
We fairly regularly forget VMSTATE_END_OF_LIST markers off descriptions;
given that the current check is only for ->name being NULL, sometimes
we get unlucky
Hi,
This series attempts to add support for Xilinx Versal's PMC SLCR
(system-level control registers) and OSPI flash memory controller to
Xilinx Versal virt machine.
The series start with adding a model of Versal's PMC SLCR and connecting
the model to the Versal virt machine. The series then
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 243 +
docs/devel/index.rst | 1 +
3 files changed, 245 insertions(+)
On 14/1/22 16:37, Peter Maydell wrote:
In commit c599d4d6d6e9bfdb64 in 2016 we renamed the old force_sig()
function to dump_core_and_abort(), but we forgot to rename the
associated tracepoint. Rename the tracepoint to to match the
function it's called from.
Signed-off-by: Peter Maydell
---
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 93
include/hw/arm/xlnx-versal.h | 20 ++
2 files
In commit c599d4d6d6e9bfdb64 in 2016 we renamed the old force_sig()
function to dump_core_and_abort(), but we forgot to rename the
associated tracepoint. Rename the tracepoint to to match the
function it's called from.
Signed-off-by: Peter Maydell
---
linux-user/signal.c | 2 +-
This patchset fixes up some minor nits in the linux-user code that I
noticed while I was reading code to assist with reviewing the
bsd-user signal handling.
thanks
-- PMM
Peter Maydell (3):
linux-user: Remove unnecessary 'aligned' attribute from TaskState
linux-user: Rename user_force_sig
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1856 +
include/hw/ssi/xlnx-versal-ospi.h | 111 +++
3 files changed, 1968
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 20
1 file changed, 20 insertions(+)
diff --git
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6ccdec7f02..0e31569d65 100644
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++
An option on real hardware when embedding a DMA engine into a peripheral
is to make the peripheral control the engine through a custom DMA control
(hardware) interface between the two. Software drivers in this scenario
configure and trigger DMA operations through the controlling peripheral's
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c| 2 +-
hw/arm/xlnx-versal.c | 28 ++--
include/hw/arm/xlnx-versal.h | 5 +++--
3 files changed,
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 71 +++-
include/hw/arm/xlnx-versal.h | 5
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446
On [2022 Jan 07] Fri 16:07:17, Peter Maydell wrote:
> On Tue, 14 Dec 2021 at 11:04, Francisco Iglesias
> wrote:
> >
> > Also, since being the author, list myself as maintainer for the file.
> >
> > Signed-off-by: Francisco Iglesias
>
>
> > +DmaCtrlIfClass
> > +--
> > +
> > +The
On 14.01.22 15:15, Philippe Mathieu-Daudé wrote:
On 14/1/22 15:09, Hanna Reitz wrote:
On 06.01.22 00:56, Philippe Mathieu-Daudé wrote:
When building on macOS 12 we get:
../block/file-posix.c:3335:18: warning: 'IOMasterPort' is
deprecated: first deprecated in macOS 12.0
On 14/1/22 14:52, Kevin Wolf wrote:
From: Philippe Mathieu-Daudé
When building QEMU with --disable-vhost-user and using introspection,
query-qmp-schema lists vhost-user-blk even though it's not actually
available:
{ "execute": "query-qmp-schema" }
{
"return": [
...
On Fri, Jan 14, 2022 at 7:57 PM Igor Mammedov wrote:
> Previous patch [1] added explicit whitespace padding to OEM_ID/OEM_TABLE_ID
> values used in test_oem_fields() testcase to avoid false positive and
> bisection issues when QEMU is switched to \0' padding. As result
> testcase ceased to test
On 1/10/22 03:52, Alexey Kardashevskiy wrote:
On 08/01/2022 00:39, Greg Kurz wrote:
On Fri, 7 Jan 2022 23:19:03 +1100
David Gibson wrote:
On Fri, Jan 07, 2022 at 12:57:47PM +0100, Greg Kurz wrote:
On Fri, 7 Jan 2022 18:24:23 +1100
Alexey Kardashevskiy wrote:
"PowerPC Processor binding
Viresh Kumar writes:
> This allows is to instantiate a vhost-user-gpio device as part of a PCI
> bus. It is mostly boilerplate which looks pretty similar to the
> vhost-user-fs-pci device.
>
> Signed-off-by: Viresh Kumar
Reviewed-by: Alex Bennée
--
Alex Bennée
On 06.01.22 00:56, Philippe Mathieu-Daudé wrote:
When building on macOS 12 we get:
../block/file-posix.c:3335:18: warning: 'IOMasterPort' is deprecated: first
deprecated in macOS 12.0 [-Wdeprecated-declarations]
kernResult = IOMasterPort( MACH_PORT_NULL, );
在 2022/1/14 下午9:59, Anup Patel 写道:
On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote:
It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is
sequentially consistent and doesn't model PMAs currently
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Tested-by: Heiko
Viresh Kumar writes:
> This creates the QEMU side of the vhost-user-gpio device which connects
> to the remote daemon. It is based of vhost-user-i2c code.
>
> Signed-off-by: Viresh Kumar
> +++ b/include/hw/virtio/vhost-user-gpio.h
> @@ -0,0 +1,35 @@
> +/*
> + * Vhost-user GPIO virtio device
On 14/1/22 15:09, Hanna Reitz wrote:
On 06.01.22 00:56, Philippe Mathieu-Daudé wrote:
When building on macOS 12 we get:
../block/file-posix.c:3335:18: warning: 'IOMasterPort' is
deprecated: first deprecated in macOS 12.0 [-Wdeprecated-declarations]
kernResult = IOMasterPort(
在 2022/1/14 下午10:01, Anup Patel 写道:
On Fri, Jan 14, 2022 at 7:24 PM Weiwei Li wrote:
Thanks for your comments.
在 2022/1/14 下午9:40, Anup Patel 写道:
On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote:
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c
Now that the devices present in the extended memory map are checked
against the available PA space and disabled when they don't fit,
there is no need to keep the same checks against highmem, as
highmem really is a shortcut for the PA space being 32bit.
Reviewed-by: Eric Auger
Signed-off-by: Marc
Just like we can control the enablement of the highmem PCIe ECAM
region using highmem_ecam, let's add a control for the highmem
PCIe MMIO region.
Similarily to highmem_ecam, this region is disabled when highmem
is off.
Signed-off-by: Marc Zyngier
---
hw/arm/virt-acpi-build.c | 10 --
Just like we can control the enablement of the highmem PCIe region
using highmem_ecam, let's add a control for the highmem GICv3
redistributor region.
Similarily to highmem_ecam, these redistributors are disabled when
highmem is off.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zyngier
---
Even when the VM is configured with highmem=off, the highest_gpa
field includes devices that are above the 4GiB limit.
Similarily, nothing seem to check that the memory is within
the limit set by the highmem=off option.
This leads to failures in virt_kvm_type() on systems that have
a crippled IPA
The highmem attribute is nothing but another way to express the
PA range of a VM. To support HW that has a smaller PA range then
what QEMU assumes, pass this PA range to the virt_set_memmap()
function, allowing it to correctly exclude highmem devices
if they are outside of the PA range.
Previous patch [1] added explicit whitespace padding to OEM_ID/OEM_TABLE_ID
values used in test_oem_fields() testcase to avoid false positive and
bisection issues when QEMU is switched to \0' padding. As result
testcase ceased to test values that were shorter than max possible
length values.
Here's yet another stab at enabling QEMU on systems with
pathologically reduced IPA ranges such as the Apple M1 (previous
version at [1]). Eventually, we're able to run a KVM guest with more
than just 3GB of RAM on a system with a 36bit IPA space, and at most
123 vCPUs.
This also addresses some
Viresh Kumar writes:
> This creates the QEMU side of the vhost-user-gpio device which connects
> to the remote daemon. It is based of vhost-user-i2c code.
>
> Signed-off-by: Viresh Kumar
Reviewed-by: Alex Bennée
--
Alex Bennée
On Fri, Jan 14, 2022 at 7:24 PM Weiwei Li wrote:
>
> Thanks for your comments.
>
> 在 2022/1/14 下午9:40, Anup Patel 写道:
>
> On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/cpu.c | 1 +
>
The calculation in sector2cluster() is done relative to the offset of
the root directory. Any writes to blocks before the start of the root
directory (in particular, writes to the FAT) result in negative values,
which are not handled correctly in vvfat_write().
This changes sector2cluster() to
On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote:
>
> It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is
> sequentially consistent and doesn't model PMAs currently
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Tested-by: Heiko Stuebner
> ---
>
Thanks for your comments.
在 2022/1/14 下午9:40, Anup Patel 写道:
On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote:
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
This demonstrates what happens when the block status changes in
sub-min_sparse granularity, but all of the parts are zeroed out. The
alignment logic in is_allocated_sectors() prevents that the target image
remains fully sparse as expected, but turns it into a data cluster of
explicit zeros.
From: Vladimir Sementsov-Ogievskiy
First, this permission never protected a node from being changed, as
generic child-replacing functions don't check it.
Second, it's a strange thing: it presents a permission of parent node
to change its child. But generally, children are replaced by different
From: Vladimir Sementsov-Ogievskiy
Consider the case when the whole buffer is zero and end is unaligned.
If i <= tail, we return 1 and do one unaligned WRITE, RMW happens.
If i > tail, we do on aligned WRITE_ZERO (or skip if target is zeroed)
and again one unaligned WRITE, RMW happens.
Let's
The size of the qcow size was calculated so that only the FAT partition
would fit on it, but not the whole disk. However, offsets relative to
the whole disk are used to access it, so increase its size to be large
enough for that.
Signed-off-by: Kevin Wolf
Message-Id:
In order to only keep the highmem devices that actually fit in
the PA range, check their location against the range and update
highest_gpa if they fit. If they don't, mark them as disabled.
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 34 --
1 file changed, 28
From: Hanna Reitz
With CAP_DAC_OVERRIDE (which e.g. root generally has), permission checks
will be bypassed when opening files.
308 in one instance tries to open a read-only file (FUSE export) with
qemu-io as read/write, and expects this to fail. However, when running
it as root, opening will
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