Re: [PULL 00/10] Block layer patches

On Tue, 1 Feb 2022 at 15:21, Kevin Wolf wrote: > > The following changes since commit 804b30d25f8d70dc2dea951883ea92235274a50c: > > Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220130' into > staging (2022-01-31 11:10:08 +) > > are available in the Git repository at: > >

Re: [PATCH 1/2] migration/rdma: Increase the backlog from 5 to 128

* Pankaj Gupta (pankaj.gu...@ionos.com) wrote: > > > > > migration/rdma.c | 2 +- > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > diff --git a/migration/rdma.c b/migration/rdma.c > > > > > index c7c7a384875b..2e223170d06d 100644 > > > > > --- a/migration/rdma.c > > > >

Re: [PATCH v5 03/18] pci: isolated address space for PCI bus

On Tue, Feb 01, 2022 at 10:34:32PM -0700, Alex Williamson wrote: > On Wed, 2 Feb 2022 01:13:22 + > Jag Raman wrote: > > > > On Feb 1, 2022, at 5:47 PM, Alex Williamson > > > wrote: > > > > > > On Tue, 1 Feb 2022 21:24:08 + > > > Jag Raman wrote: > > > > > >>> On Feb 1, 2022, at 10:

Re: [PATCH v4 00/12] KVM: mm: fd-based approach for supporting KVM guest private memory

Hi Jun, On 02/02/2022 02:28, Nakajima, Jun wrote: > >> On Jan 28, 2022, at 8:47 AM, Steven Price wrote: >> >> On 18/01/2022 13:21, Chao Peng wrote: >>> This is the v4 of this series which try to implement the fd-based KVM >>> guest private memory. The patches are based on latest kvm/queue branch

Re: [PATCH v5 03/18] pci: isolated address space for PCI bus

On Tue, 1 Feb 2022 at 23:51, Alex Williamson wrote: > > On Tue, 1 Feb 2022 21:24:08 + > Jag Raman wrote: > > The PCIBus data structure already has address_space_mem and > > address_space_io to contain the BAR regions of devices attached > > to it. I understand that these two PCIBus members fo

Re: [PATCH 1/2] migration/rdma: Increase the backlog from 5 to 128

On Wed, Feb 2, 2022 at 10:20 AM Dr. David Alan Gilbert wrote: > > * Pankaj Gupta (pankaj.gu...@ionos.com) wrote: > > > > > > migration/rdma.c | 2 +- > > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/migration/rdma.c b/migration/rdma.c > > > > > > inde

Re: [PATCH v5 03/18] pci: isolated address space for PCI bus

On Wed, Feb 02, 2022 at 09:30:42AM +, Peter Maydell wrote: > > I/O port space is always the identity mapped CPU address space unless > > sparse translations are used to create multiple I/O port spaces (not > > implemented). I/O port space is only accessed by the CPU, there are no > > device in

Re: [PATCH 2/2] migration/rdma: set the REUSEADDR option for destination

* Jack Wang (jinpu.w...@ionos.com) wrote: > This allow address could be reused to avoid rdma_bind_addr error > out. In what case do you get the error - after a failed migrate and then a retry? Dave > Signed-off-by: Jack Wang > --- > migration/rdma.c | 7 +++ > 1 file changed, 7 insertions(

arm: singlestep bug

Hello TCG developers, We have new debug test cases in kvm-unit-tests thanks to Ricardo Koller. The singlestep test cases are failing with TCG. Enabling TCG debug outputs the error TCG hflags mismatch (current:(0x04a1,0x4000) rebuilt:(0x04a3,0x4000) I noticed th

[PATCH v2] hw/rx: rx-gdbsim DTB load address aligned of 16byte.

Linux kernel required alined address of DTB. But missing align in dtb load function. Fixed to load to the correct address. v2 changes. Use ROUND_DOWN macro. Signed-off-by: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé --- hw/rx/rx-gdbsim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletio

Re: [PATCH 2/2] migration/rdma: set the REUSEADDR option for destination

On Wed, Feb 2, 2022 at 11:15 AM Dr. David Alan Gilbert wrote: > > * Jack Wang (jinpu.w...@ionos.com) wrote: > > This allow address could be reused to avoid rdma_bind_addr error > > out. > > In what case do you get the error - after a failed migrate and then a > retry? Yes, what I saw is in case o

[PATCH] hw/arm/smmuv3: Fix device reset

We currently miss a bunch of register resets in the device reset function. This sometimes prevents the guest from rebooting after a system_reset (with virtio-blk-pci). For instance, we may get the following errors: invalid STE smmuv3-iommu-memory-region-0-0 translation failed for iova=0x13a9d2000

Re: [PATCH v2 3/3] migration: Perform vmsd structure check during tests

* Juan Quintela (quint...@redhat.com) wrote: > "Dr. David Alan Gilbert" wrote: > > * Juan Quintela (quint...@redhat.com) wrote: > >> "Dr. David Alan Gilbert (git)" wrote: > >> > From: "Dr. David Alan Gilbert" > >> > > >> > Perform a check on vmsd structures during test runs in the hope > >> > of

Re: [PULL 18/20] block/nbd: drop connection_co

Am 27.09.21 um 23:55 schrieb Eric Blake: > From: Vladimir Sementsov-Ogievskiy > > OK, that's a big rewrite of the logic. > > Pre-patch we have an always running coroutine - connection_co. It does > reply receiving and reconnecting. And it leads to a lot of difficult > and unobvious code around d

[RFC PATCH] arm: force flag recalculation when messing with DAIF

The recently introduced debug tests in kvm-unit-tests exposed an error in our handling of singlestep cause by stale hflags. This is caught by --enable-debug-tcg when running the tests. Signed-off-by: Alex Bennée Cc: Richard Henderson Cc: Andrew Jones --- target/arm/helper-a64.c | 2 ++ 1 file

Re: arm: singlestep bug

On Wed, Feb 02, 2022 at 11:16:46AM +, Alex Bennée wrote: ... > Side note: > > ad5fb8830150071487025b3594a7b1bf218d12d8 is the first bad commit > commit ad5fb8830150071487025b3594a7b1bf218d12d8 > Author: Zixuan Wang > Date: Mon Oct 4 13:49:19 2021 -0700 > > breaks the running on kvm

Re: arm: singlestep bug

Andrew Jones writes: > Hello TCG developers, > > We have new debug test cases in kvm-unit-tests thanks to Ricardo > Koller. Yay tests ;-) > The singlestep test cases are failing with TCG. Enabling TCG debug outputs > the error > > TCG hflags mismatch (current:(0x04a1,0x4000)

Re: [RFC PATCH] arm: force flag recalculation when messing with DAIF

On Wed, Feb 02, 2022 at 12:23:53PM +, Alex Bennée wrote: > The recently introduced debug tests in kvm-unit-tests exposed an error > in our handling of singlestep cause by stale hflags. This is caught by > --enable-debug-tcg when running the tests. > > Signed-off-by: Alex Bennée > Cc: Richard

Re: [PATCH v2] hw/rx: rx-gdbsim DTB load address aligned of 16byte.

On 2/2/22 11:30, Yoshinori Sato wrote: Linux kernel required alined address of DTB. But missing align in dtb load function. Fixed to load to the correct address. v2 changes. Use ROUND_DOWN macro. Signed-off-by: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé --- hw/rx/rx-gdbsim.c | 2 +-

Re: [PATCH v2 3/3] migration: Perform vmsd structure check during tests

"Dr. David Alan Gilbert" wrote: > * Juan Quintela (quint...@redhat.com) wrote: >> "Dr. David Alan Gilbert" wrote: >> > * Juan Quintela (quint...@redhat.com) wrote: >> >> "Dr. David Alan Gilbert (git)" wrote: >> >> > From: "Dr. David Alan Gilbert" >> >> > >> >> > Perform a check on vmsd structur

Re: [PATCH v2 3/4] virtio-iommu: Support bypass domain

Hi Dave, On 1/31/22 2:07 PM, Dr. David Alan Gilbert wrote: > * Eric Auger (eric.au...@redhat.com) wrote: >> Hi Jean, >> >> On 1/27/22 3:29 PM, Jean-Philippe Brucker wrote: >>> The driver can create a bypass domain by passing the >>> VIRTIO_IOMMU_ATTACH_F_BYPASS flag on the ATTACH request. Bypass d

Re: [PATCH v3 1/1] virtio: fix the condition for iommu_platform not supported

On Wed, 2 Feb 2022 02:06:12 -0500 "Michael S. Tsirkin" wrote: [..] > > In my opinion not forcing the guest to negotiate IOMMU_PLATFORM when > > ->get_dma_as() is not set is at least unfortunate. Please observe, that > > virtio-pci is not affected by this omission because for virtio-pci > > de

Re: [PATCH v3 1/1] virtio: fix the condition for iommu_platform not supported

On 2/1/22 22:15, Halil Pasic wrote: On Tue, 1 Feb 2022 16:31:22 -0300 Daniel Henrique Barboza wrote: On 2/1/22 15:33, Halil Pasic wrote: On Tue, 1 Feb 2022 12:36:25 -0300 Daniel Henrique Barboza wrote: +vdev_has_iommu = virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM);

Re: [PATCH v3 0/2] tests/9pfs: Fix leak and add some more g_auto* annotations

On Dienstag, 1. Februar 2022 16:15:06 CET Greg Kurz wrote: > This is the continuation of: > > https://lore.kernel.org/qemu-devel/2022020137.732325b4@bahia/T/#t > > v3: - fix leak in its own patch > > Greg Kurz (2): > tests/9pfs: Fix leak of local_test_path > tests/9pfs: Use g_autofree an

Re: [PATCH 10/20] tcg/i386: Implement avx512 immediate sari shift

Richard Henderson writes: > AVX512 has VPSRAQ with immediate operand, in the same form as > with AVX, but requires EVEX encoding and W1. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re: [PATCH 09/20] tcg/i386: Implement avx512 scalar shift

Richard Henderson writes: > AVX512VL has VPSRAQ. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re: [PATCH v2 3/3] migration: Perform vmsd structure check during tests

On Wed, 2 Feb 2022 at 11:32, Dr. David Alan Gilbert wrote: > Because in my local world I did the changes to libslirp; I wanted to > make sure qemu people were happy with the changes before proposing them > to libslirp. > > Which I've just done: > > https://gitlab.freedesktop.org/slirp/libslirp/-/m

Re: [PULL 18/20] block/nbd: drop connection_co

On Wed, Feb 02, 2022 at 12:49:36PM +0100, Fabian Ebner wrote: > Am 27.09.21 um 23:55 schrieb Eric Blake: > > From: Vladimir Sementsov-Ogievskiy > > > > OK, that's a big rewrite of the logic. > > > > Pre-patch we have an always running coroutine - connection_co. It does > > reply receiving and re

[PATCH v5 00/43] CXl 2.0 emulation Support

Changes since v4: https://lore.kernel.org/linux-cxl/20220124171705.10432-1-jonathan.came...@huawei.com/ Note documentation patch that Alex requested to follow. I don't want to delay getting this out as Alex mentioned possibly having time to continue reviewing in latter part of this week. Issues i

[PATCH v5 01/43] hw/pci/cxl: Add a CXL component type (interface)

From: Ben Widawsky A CXL component is a hardware entity that implements CXL component registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 general types. 1. Host Bridge 2. Ports (root, upstream, downstream) 3. Devices (memory, other) A CXL component can be conceptually thought of

[PATCH v5 04/43] hw/cxl/device: Introduce a CXL device (8.2.8)

From: Ben Widawsky A CXL device is a type of CXL component. Conceptually, a CXL device would be a leaf node in a CXL topology. From an emulation perspective, CXL devices are the most complex and so the actual implementation is reserved for discrete commits. This new device type is specifically c

[PATCH v5 03/43] MAINTAINERS: Add entry for Compute Express Link Emulation

From: Jonathan Cameron The CXL emulation will be jointly maintained by Ben Widawsky and Jonathan Cameron. Broken out as a separate patch to improve visibility. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/

Re: [PATCH 12/20] tcg/i386: Implement avx512 variable rotate

Richard Henderson writes: > AVX512VL has VPROLVQ and VPRORVQ. > > Signed-off-by: Richard Henderson I could make the same comment from the previous patch about the goto gen_simd stuff. Anyway: Reviewed-by: Alex Bennée -- Alex Bennée

Re: [PATCH 11/20] tcg/i386: Implement avx512 immediate rotate

Richard Henderson writes: > AVX512VL has VPROLD and VPROLQ, layered onto the same > opcode as PSHIFTD, but requires EVEX encoding and W. > > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target.h | 2 +- > tcg/i386/tcg-target.c.inc | 15 +-- > 2 files changed, 14 inse

[PATCH v5 02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)

From: Ben Widawsky A CXL 2.0 component is any entity in the CXL topology. All components have a analogous function in PCIe. Except for the CXL host bridge, all have a PCIe config space that is accessible via the common PCIe mechanisms. CXL components are enumerated via DVSEC fields in the extende

[PATCH v5 18/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)

From: Ben Widawsky CXL host bridges themselves may have MMIO. Since host bridges don't have a BAR they are treated as special for MMIO. This patch includes i386/pc support. Signed-off-by: Ben Widawsky Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron --- hw/i386/acpi-build.c

[PATCH v5 05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2)

From: Ben Widawsky This implements all device MMIO up to the first capability. That includes the CXL Device Capabilities Array Register, as well as all of the CXL Device Capability Header Registers. The latter are filled in as they are implemented in the following patches. Endianness and alignme

[PATCH v5 11/43] hw/pxb: Use a type for realizing expanders

From: Ben Widawsky This opens up the possibility for more types of expanders (other than PCI and PCIe). We'll need this to create a CXL expander. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- hw/pci-bridge/pci_expander_bridge.c | 11 +++ 1 f

[PATCH v5 07/43] hw/cxl/device: Add memory device utilities

From: Ben Widawsky Memory devices implement extra capabilities on top of CXL devices. This adds support for that. A large part of memory devices is the mailbox/command interface. All of the mailbox handling is done in the mailbox-utils library. Longer term, new CXL devices that are being emulate

[PATCH v5 24/43] acpi/cxl: Create the CEDT (9.14.1)

From: Ben Widawsky The CXL Early Discovery Table is defined in the CXL 2.0 specification as a way for the OS to get CXL specific information from the system firmware. CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware

[PATCH v5 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4)

From: Ben Widawsky This is the beginning of implementing mailbox support for CXL 2.0 devices. The implementation recognizes when the doorbell is rung, handles the command/payload, clears the doorbell while returning error codes and data. Generally the mailbox mechanism is designed to permit comm

[PATCH v5 12/43] hw/pci/cxl: Create a CXL bus type

From: Ben Widawsky The easiest way to differentiate a CXL bus, and a PCIE bus is using a flag. A CXL bus, in hardware, is backward compatible with PCIE, and therefore the code tries pretty hard to keep them in sync as much as possible. The other way to implement this would be to try to cast the

[PATCH v5 26/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing

From: Ben Widawsky This should introduce no change. Subsequent work will make use of this new class member. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-mailbox-utils.c | 3 +++ hw/mem/cxl_type3.c | 24 +--- include/hw/cxl/cxl_devic

[PATCH v5 14/43] tests/acpi: allow DSDT.viot table changes.

From: Jonathan Cameron The next patch unifies some of the PCI host bridge DSDT generation code and results in some minor changes to this file. Signed-off-by: Jonathan Cameron --- v5: No change, but Alex suggested we combine this and next two patches. I'd like feedback from the bios tables test

[PATCH v5 13/43] hw/pxb: Allow creation of a CXL PXB (host bridge)

From: Ben Widawsky This works like adding a typical pxb device, except the name is 'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as follows: -device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1 A CXL PXB is backward compatible with PCIe. What this means in practice is that an ope

[PATCH v5 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)

From: Ben Widawsky Using the previously implemented stubbed helpers, it is now possible to easily add the missing, required commands to the implementation. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- v5: Follow through on upper casing defines in pa

[PATCH v5 15/43] acpi/pci: Consolidate host bridge setup

From: Ben Widawsky This cleanup will make it easier to add support for CXL to the mix. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- v5: Make the PCI bus type a typed enum. hw/i386/acpi-build.c | 39 ++- 1 file c

[PATCH v5 25/43] hw/cxl/device: Add some trivial commands

From: Ben Widawsky GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to info already returned in the IDENTIFY command. To have a more robust implementation, add those. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- v5: Follow through on rework of how mailbo

[PATCH v5 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3)

From: Ben Widawsky Errata F4 to CXL 2.0 clarified the meaning of the timer as the sum of the value set with the timestamp set command and the number of nano seconds since it was last set. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- v5: Reponses to Alex's review. - Change

Re: [PATCH 13/20] tcg/i386: Support avx512vbmi2 vector shift-double instructions

Richard Henderson writes: > We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

[PATCH v5 16/43] tests/acpi: Add update DSDT.viot

From: Jonathan Cameron The consolidation of DSDT AML generation for PCI host bridges lead to some minor ordering changes and the addition of _ADR with a default of 0 for those case that didn't already have it. Only DSDT.viot test is affected. Changes all similar to: Scope (\_SB) { D

[PATCH v5 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL

From: Ben Widawsky CXL specification provides for the ability to obtain logs from the device. Logs are either spec defined, like the "Command Effects Log" (CEL), or vendor specific. UUIDs are defined for all log types. The CEL is a mechanism to provide information to the host about which command

[PATCH v5 28/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding

From: Jonathan Cameron Both registers and the CFMWS entries in CDAT use simple encodings for the number of interleave ways and the interleave granularity. Introduce simple conversion functions to/from the unencoded number / size. So far the iw decode has not been needed so is it not implemented.

[PATCH v5 37/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl

Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. The CFMWs are placed above the extended memmap. Signed-off-by: Jonathan Cameron Signed-off-by: Ben Widawsky --- hw/arm/virt-acpi-build.c | 30 ++

[PATCH v5 29/43] hw/cxl/host: Add support for CXL Fixed Memory Windows.

From: Jonathan Cameron The concept of these is introduced in [1] in terms of the description the CEDT ACPI table. The principal is more general. Unlike once traffic hits the CXL root bridges, the host system memory address routing is implementation defined and effectively static once observable b

[PATCH v5 38/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file

From: Jonathan Cameron Inorder to implement memory interleaving we need a means to proxy the calls. Adding mem_ops allows such proxying. Note should have no impact on use cases not using _dispatch_read/write. For now, only file backed hostmem is considered to seek feedback on the approach before

[PATCH v5 21/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12)

From: Ben Widawsky A device's volatile and persistent memory are known Host Defined Memory (HDM) regions. The mechanism by which the device is programmed to claim the addresses associated with those regions is through dedicated logic known as the HDM decoder. In order to allow the OS to properly

[PATCH v5 17/43] cxl: Machine level control on whether CXL support is enabled

From: Jonathan Cameron There are going to be some potential overheads to CXL enablement, for example the host bridge region reserved in memory maps. Add a machine level control so that CXL is disabled by default. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- v5: From Alex review

[PATCH v5 30/43] acpi/cxl: Introduce CFMWS structures in CEDT

From: Ben Widawsky The CEDT CXL Fixed Window Memory Window Structures (CFMWs) define regions of the host phyiscal address map which (via an impdef means) are configured such that they have a particular interleave setup across one or more CXL Host Bridges. Reported-by: Alison Schofield Signed-of

[PATCH v5 22/43] acpi/cxl: Add _OSC implementation (9.14.2)

From: Ben Widawsky CXL 2.0 specification adds 2 new dwords to the existing _OSC definition from PCIe. The new dwords are accessed with a new uuid. This implementation supports what is in the specification. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- v5: Fix for issue seen o

[PATCH v5 43/43] scripts/device-crash-test: Add exception for pxb-cxl

The CXL expander bridge has several requirements but the one that is checked first is that it is attached to a PCI Express bus, not a PCI one so document that. Signed-off-by: Jonathan Cameron --- v5: New patch - should probably be pushed down to introduction of pxb-cxl. Will do that in v6 sc

Re: [PULL 18/20] block/nbd: drop connection_co

On 02.02.22 14:53, Eric Blake wrote: On Wed, Feb 02, 2022 at 12:49:36PM +0100, Fabian Ebner wrote: Am 27.09.21 um 23:55 schrieb Eric Blake: From: Vladimir Sementsov-Ogievskiy OK, that's a big rewrite of the logic. Pre-patch we have an always running coroutine - connection_co. It does reply r

[PATCH v5 19/43] hw/cxl/rp: Add a root port

From: Ben Widawsky This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to

[PATCH v5 33/43] CXL/cxl_component: Add cxl_get_hb_cstate()

From: Jonathan Cameron Accessor to get hold of the cxl state for a CXL host bridge without exposing the internals of the implementation. Signed-off-by: Jonathan Cameron --- hw/pci-bridge/pci_expander_bridge.c | 7 +++ include/hw/cxl/cxl_component.h | 2 ++ 2 files changed, 9 insertion

Re: [PATCH v1 12/22] plugins: stxp test case from Aaron (!upstream)

On Feb 01 15:29, Alex Bennée wrote: > > Aaron Lindsay writes: > > > On Jan 24 20:15, Alex Bennée wrote: > >> Signed-off-by: Alex Bennée > >> Cc: Aaron Lindsay > >> Message-ID: > >> > >> --- > >> [AJB] this was for testing, I think you can show the same stuff with > >> the much more complete

[PATCH v5 20/43] hw/cxl/device: Add a memory device (8.2.8.5)

From: Ben Widawsky A CXL memory device (AKA Type 3) is a CXL component that contains some combination of volatile and persistent memory. It also implements the previously defined mailbox interface as well as the memory device firmware interface. Although the memory device is configured like a no

[PATCH v5 23/43] tests/acpi: allow CEDT table addition

From: Ben Widawsky Following patches will add a new ACPI table, the CXL Early Discovery Table (CEDT). Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- tests/data/acpi/pc/CEDT | 0 tests/data/acpi/q35/CEDT| 0 tests/qtest/bios-tables-test-

[PATCH v5 35/43] cxl/cxl-host: Add memops for CFMWS region.

From: Jonathan Cameron These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional the

[PATCH v5 27/43] hw/cxl/device: Implement get/set Label Storage Area (LSA)

From: Ben Widawsky Implement get and set handlers for the Label Storage Area used to hold data describing persistent memory configuration so that it can be ensured it is seen in the same configuration after reboot. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- v5: Fix wrong

[PATCH v5 34/43] mem/cxl_type3: Add read and write functions for associated hostmem.

From: Jonathan Cameron Once a read or write reaches a CXL type 3 device, the HDM decoders on the device are used to establish the Device Physical Address which should be accessed. These functions peform the required maths and then directly access the hostmem->mr to fullfil the actual operation.

[PATCH v5 39/43] hw/cxl/component Add a dumb HDM decoder handler

From: Ben Widawsky Add a trivial handler for now to cover the root bridge where we could do some error checking in future. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-component-utils.c | 31 +++ 1 file changed, 31 insertions(+) diff

[PATCH v5 31/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl

This adds code to instantiate the slightly extended ACPI root port description in DSDT as per the CXL 2.0 specification. Basically a cut and paste job from the i386/pc code. Signed-off-by: Jonathan Cameron Signed-off-by: Ben Widawsky --- v5: No change to this patch, but build issue seen here w

[PATCH v5 41/43] qtest/acpi: Add reference CEDT tables.

From: Jonathan Cameron More sophisticated tests will come later, but for now deal with the NULL case. Signed-off-by: Jonathan Cameron --- tests/data/acpi/pc/CEDT | Bin 0 -> 36 bytes tests/data/acpi/q35/CEDT| Bin 0 -> 36 bytes tests/data/acpi/virt/CEDT

[PATCH v1] an547: Correct typo that swaps ahb and apb peripherals

Turns out that this manifests in being unable to configure the ethernet access permissions, as the IotKitPPC looks these up by name. With this fix, eth is configurable Signed-off-by: Jimmy Brisson --- hw/arm/mps2-tz.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ar

[PATCH v5 42/43] qtest/cxl: Add very basic sanity tests

From: Ben Widawsky Simple 'does it boot tests' with up to 2x PXB host bridge, each with 2x CXL RP and each of those with a Type 3 memory device. Single CFMWS to interleave across the two HBs and ultimate the 4 devices. More complete tests may be possible but CXL interleave setup is complex so a

[PATCH v5 32/43] pci/pcie_port: Add pci_find_port_by_pn()

From: Jonathan Cameron Simple function to search a PCIBus to find a port by it's port number. CXL interleave decoding uses the port number as a target so it is necessary to locate the port when doing interleave decoding. Signed-off-by: Jonathan Cameron --- hw/pci/pcie_port.c | 25

[PATCH v5 36/43] arm/virt: Allow virt/CEDT creation

From: Jonathan Cameron Allow for the creation of the CEDT ACPI table without qtest fails due to the unknown ACPI tables. Signed-off-by: Jonathan Cameron --- tests/data/acpi/virt/CEDT | 0 tests/qtest/bios-tables-test-allowed-diff.h | 1 + 2 files changed, 1 insertion(+) crea

[PATCH] qemu-options: fix incorrect description for '-drive index='

qemu-options.hx contains grammar that a native English-speaking person would never use. Replace "This option defines where is connected the drive" by "This option defines where the drive is connected". Fixes: https://gitlab.com/qemu-project/qemu/-/issues/853 Signed-off-by: Laurent Vivier --- qe

Re: [PATCH 10/12] block.c: add subtree_drains where needed

On 01/02/2022 15:47, Vladimir Sementsov-Ogievskiy wrote: > 18.01.2022 19:27, Emanuele Giuseppe Esposito wrote: >> Protect bdrv_replace_child_noperm, as it modifies the >> graph by adding/removing elements to .children and .parents >> list of a bs. Use the newly introduced >> bdrv_subtree_drained

[PATCH v5 40/43] i386/pc: Enable CXL fixed memory windows

From: Jonathan Cameron Add the CFMWs memory regions to the memorymap and adjust the PCI window to avoid hitting the same memory. Signed-off-by: Jonathan Cameron --- hw/i386/pc.c | 31 ++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/h

Re: [PATCH v5 03/18] pci: isolated address space for PCI bus

On Wed, 2 Feb 2022 05:06:49 -0500 "Michael S. Tsirkin" wrote: > On Wed, Feb 02, 2022 at 09:30:42AM +, Peter Maydell wrote: > > > I/O port space is always the identity mapped CPU address space unless > > > sparse translations are used to create multiple I/O port spaces (not > > > implemented).

Re: [PATCH v1 1/1] target/i386: Mask xstate_bv based on the cpu enabled features

On Tuesday, 2022-02-01 at 16:09:57 -03, Leonardo Brás wrote: > Hello David, thanks for this feedback! > > On Mon, 2022-01-31 at 12:53 +, David Edmondson wrote: >> On Saturday, 2022-01-29 at 06:46:45 -03, Leonardo Bras wrote: >> >> > The following steps describe a migration bug: >> > 1 - Bring

Re: [PATCH v3 1/1] virtio: fix the condition for iommu_platform not supported

On 2/2/22 13:23, Halil Pasic wrote: On Wed, 2 Feb 2022 10:24:51 -0300 Daniel Henrique Barboza wrote: On 2/1/22 22:15, Halil Pasic wrote: On Tue, 1 Feb 2022 16:31:22 -0300 Daniel Henrique Barboza wrote: On 2/1/22 15:33, Halil Pasic wrote: On Tue, 1 Feb 2022 12:36:25 -0300 Daniel Henr

Re: [PATCH v3 04/11] 9p: darwin: Handle struct dirent differences

Does the version proposed in v3 address the V9fsFidState issues? In 9p.c for v2 to v3, we propose -return telldir(fidp->fs.dir.stream); +return v9fs_co_telldir(pdu, fidp); and in codir.c from v2 to v3 we propose -saved_dir_pos = telldir(fidp->fs.dir.stream); +saved_dir_pos

Re: [PATCH] hw/i2c: flatten pca954x mux device

On 1/2/22 21:54, Patrick Venture wrote: On Tue, Feb 1, 2022 at 11:02 AM Philippe Mathieu-Daudé > wrote: On 1/2/22 17:30, Patrick Venture wrote: > Previously this device created N subdevices which each owned an i2c bus. > Now this device simply owns th

Re: [PATCH] hw/i2c: flatten pca954x mux device

On Wed, Feb 2, 2022 at 8:34 AM Patrick Venture wrote: > > > On Tue, Feb 1, 2022 at 12:54 PM Patrick Venture > wrote: > >> >> >> On Tue, Feb 1, 2022 at 11:02 AM Philippe Mathieu-Daudé >> wrote: >> >>> On 1/2/22 17:30, Patrick Venture wrote: >>> > Previously this device created N subdevices which

[PATCH v2] hw/i2c: flatten pca954x mux device

Previously this device created N subdevices which each owned an i2c bus. Now this device simply owns the N i2c busses directly. Tested: Verified devices behind mux are still accessible via qmp and i2c from within an arm32 SoC. Reviewed-by: Hao Wu Signed-off-by: Patrick Venture Reviewed-by: Phil

Re: [PATCH v2] 9pfs: Fix segfault in do_readdir_many caused by struct dirent overread

On Freitag, 28. Januar 2022 23:33:26 CET Vitaly Chikunov wrote: > `struct dirent' returned from readdir(3) could be shorter than > `sizeof(struct dirent)', thus memcpy of sizeof length will overread > into unallocated page causing SIGSEGV. Example stack trace: > > #0 0x559ebeed v9fs_co_r

Re: [PATCH] hw/i2c: flatten pca954x mux device

On Tue, Feb 1, 2022 at 12:54 PM Patrick Venture wrote: > > > On Tue, Feb 1, 2022 at 11:02 AM Philippe Mathieu-Daudé > wrote: > >> On 1/2/22 17:30, Patrick Venture wrote: >> > Previously this device created N subdevices which each owned an i2c bus. >> > Now this device simply owns the N i2c busse

Re: [PATCH v3 1/1] virtio: fix the condition for iommu_platform not supported

On Wed, 2 Feb 2022 10:24:51 -0300 Daniel Henrique Barboza wrote: > On 2/1/22 22:15, Halil Pasic wrote: > > On Tue, 1 Feb 2022 16:31:22 -0300 > > Daniel Henrique Barboza wrote: > > > >> On 2/1/22 15:33, Halil Pasic wrote: > >>> On Tue, 1 Feb 2022 12:36:25 -0300 > >>> Daniel Henrique Barboza

Re: [PATCH v5 03/18] pci: isolated address space for PCI bus

On Wed, Feb 02, 2022 at 08:49:33AM -0700, Alex Williamson wrote: > > Alex, what did you refer to? > > My evidence is largely by omission, but that might be that in practice > it's not used rather than explicitly forbidden. I note that the bus > master enable bit specifies: > > Bus Master E

Re: [PATCH v6 1/3] nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class

On 2/1/22 18:57, Shivaprasad G Bhat wrote: A new subclass inheriting NVDIMMDevice is going to be introduced in subsequent patches. The new subclass uses the realize and unrealize callbacks. Add them on NVDIMMClass to appropriately call them as part of plug-unplug. Signed-off-by: Shivaprasad G

Re: [PATCH v3 1/1] virtio: fix the condition for iommu_platform not supported

On Wed, Feb 02, 2022 at 05:23:53PM +0100, Halil Pasic wrote: > On Wed, 2 Feb 2022 10:24:51 -0300 > Daniel Henrique Barboza wrote: > > > On 2/1/22 22:15, Halil Pasic wrote: > > > On Tue, 1 Feb 2022 16:31:22 -0300 > > > Daniel Henrique Barboza wrote: > > > > > >> On 2/1/22 15:33, Halil Pasic wr

Re: [PATCH v5 03/18] pci: isolated address space for PCI bus

On Wed, 2 Feb 2022 09:30:42 + Peter Maydell wrote: > On Tue, 1 Feb 2022 at 23:51, Alex Williamson > wrote: > > > > On Tue, 1 Feb 2022 21:24:08 + > > Jag Raman wrote: > > > The PCIBus data structure already has address_space_mem and > > > address_space_io to contain the BAR regions of

Re: [PATCH v6 21/33] block: move BQL logic of bdrv_co_invalidate_cache in bdrv_activate

On 1/27/22 12:03, Kevin Wolf wrote: +int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs, Error **errp) +{ +Error *local_err = NULL; + +if (bs->drv->bdrv_co_invalidate_cache) { +bs->drv->bdrv_co_invalidate_cache(bs, &local_err); +if (local_err) { +bs

Re: [PATCH] hw/i2c: flatten pca954x mux device

On 2/2/22 17:40, Patrick Venture wrote: Philippe, I0202 08:29:45.380384  6641 stream.go:31] qemu: child buses at "pca9546": "channel[*]", "channel[*]", "channel[*]", "channel[*]" Ok, so that's interesting.  In one system (using qom-list) it's correct, but then when using it

Re: [PATCH 10/12] block.c: add subtree_drains where needed

On 2/2/22 16:37, Emanuele Giuseppe Esposito wrote: So we have disk B with backing file C, and new disk A that wants to have backing file C. I think I understand what you mean, so in theory the operation would be - create new child - add child to A->children list - add child to C->parents list S

Re: [PATCH v3 04/11] 9p: darwin: Handle struct dirent differences

On Mittwoch, 2. Februar 2022 16:07:09 CET Will Cohen wrote: > Does the version proposed in v3 address the V9fsFidState issues? In 9p.c > for v2 to v3, we propose > > -return telldir(fidp->fs.dir.stream); > +return v9fs_co_telldir(pdu, fidp); > > and in codir.c from v2 to v3 we propose > -

[PULL 5/6] hw/display/artist: Mouse cursor fixes for HP-UX

This patch fix the behaviour and positioning of the X11 mouse cursor in HP-UX. The current code missed to subtract the offset of the CURSOR_CTRL register from the current mouse cursor position. The HP-UX graphics driver stores in this register the offset of the mouse graphics compared to the curre

[PULL 6/6] hw/display/artist: Fix draw_line() artefacts

From: Sven Schnelle The draw_line() function left artefacts on the screen because it was using the x/y variables which were incremented in the loop before. Fix it by using the unmodified x1/x2 variables instead. Signed-off-by: Sven Schnelle Signed-off-by: Helge Deller Cc: qemu-sta...@nongnu.or

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