Queued, thanks!
Fabian Holler writes:
> The examples for the snapshot-* and calc-dirty-rate commands document
> that arguments for the commands are passed in a 'data' field.
> This is wrong, passing them in a "data" field results in
> the error:
> {"error": {"class": "GenericError", "desc": "QMP input member '
On Tue, Feb 22, 2022 at 12:51:59PM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > Two tests are added: a normal postcopy preempt test, and a recovery test.
>
> Yes, this is difficult; without hugepages the tests are limited; did you
> see if this test actually cau
On Tue, Feb 22, 2022 at 11:32:10AM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > To allow postcopy recovery, the ram fast load (preempt-only) dest QEMU
> > thread
> > needs similar handling on fault tolerance. When ram_load_postcopy() fails,
> > instead of stopp
Excerpts from David Gibson's message of February 17, 2022 10:17 am:
> On Wed, Feb 16, 2022 at 04:39:02PM +1000, Nicholas Piggin wrote:
>> The behaviour of the Address Translation Mode on Interrupt resource is
>> not consistently supported by all CPU versions or all KVM versions:
>> KVM-HV does not
On Tue, Feb 22, 2022 at 10:52:23AM +, Dr. David Alan Gilbert wrote:
> This does get a bit complicated, which worries me a bit; the code here
> is already quite complicated.
Right, it's the way I chose in this patchset on solving this problem. Not
sure whether there's any better and easier way
On Wed, Feb 23, 2022 at 4:09 AM Atish Patra wrote:
>
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter IS
On Tue, Feb 22, 2022 at 10:57:34AM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > We used to use postcopy_try_recover() to replace migration_incoming_setup()
> > to
> > setup incoming channels. That's fine for the old world, but in the new
> > world
> > there ca
This adds support for breakpoints and stepping when debugging
WHPX-accelerated guests with gdb.
It enables reliable debugging of the Linux kernel in both single-CPU and SMP
modes.
Signed-off-by: Ivan Shcherbakov
---
gdbstub.c| 10 +
include/exec/gdbstub.h | 8
This fixes the following error triggered when stopping and resuming a 64-bit
Linux kernel via gdb:
qemu-system-x86_64.exe: WHPX: Failed to set virtual processor context,
hr=c0350005
The previous logic for synchronizing the values did not take into account
that the lower 4 bits of
the CR8 register
Hi All,
We have been looking into kernel-debugging Linux VMs running on Windows with
Hyper-V enabled (that forces the virtualization software to use WHPX), and
it turned out, none of the major virtualization tools supports it properly.
I've added the missing parts to QEMU and it looks pretty solid
Hi Stefan:
Recently I found intel vIOMMU gives the following warning when using
virtio-blk:
qemu-system-x86_64: vtd_iova_to_slpte: detected slpte permission error
(iova=0x7ffde000, level=0x3, slpte=0x0, write=0)
qemu-system-x86_64: vtd_iommu_translate: detected translation failure
(dev=01:00
On Wed, Feb 23, 2022 at 8:09 AM Atish Patra wrote:
>
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra
Do y
On Wed, Feb 23, 2022 at 7:45 AM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> Conenct spi host[1/0] to opentitan.
>
> Signed-off-by: Wilfred Mallawa
> ---
> hw/riscv/opentitan.c | 42
> include/hw/riscv/opentitan.h | 16 --
> 2 fi
On Wed, Feb 23, 2022 at 8:09 AM Atish Patra wrote:
>
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra
Revi
On Tue, Feb 22, 2022 at 4:06 PM Eugenio Perez Martin
wrote:
>
> On Tue, Feb 22, 2022 at 8:41 AM Jason Wang wrote:
> >
> >
> > 在 2022/2/17 下午4:22, Eugenio Perez Martin 写道:
> > > On Thu, Feb 17, 2022 at 7:02 AM Jason Wang wrote:
> > >> On Wed, Feb 16, 2022 at 11:54 PM Eugenio Perez Martin
> > >>
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Lucas Coutinho
Implement the following PowerISA v3.1 instuctions:
lxvrbx: Load VSX Vector Rightmost Byte Indexed X-form
lxvrhx: Load VSX Vector Rightmost Halfword Indexed X-form
lxvrwx: Load VSX Vector Rightmost Word Indexed X-form
lxv
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Leandro Lupori
Implement instructions plxssp/pstxssp and port lxssp/stxssp to
decode tree.
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 2 +
target/ppc/insn64.decode| 6 ++
target/ppc/transl
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Leandro Lupori
Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode
tree.
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 2 ++
target/ppc/insn64.decode| 10 ++
target/ppc/trans
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 21 +++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode| 11 +++
On Tue, Feb 22, 2022 at 4:56 PM Eugenio Perez Martin
wrote:
>
> On Tue, Feb 22, 2022 at 8:26 AM Jason Wang wrote:
> >
> >
> > 在 2022/2/21 下午4:15, Eugenio Perez Martin 写道:
> > > On Mon, Feb 21, 2022 at 8:44 AM Jason Wang wrote:
> > >>
> > >> 在 2022/2/17 下午8:48, Eugenio Perez Martin 写道:
> > >>> On
On Wed, Feb 23, 2022 at 3:01 AM Eugenio Perez Martin
wrote:
>
> On Tue, Feb 8, 2022 at 9:11 AM Jason Wang wrote:
> >
> >
> > 在 2022/2/2 上午1:08, Eugenio Perez Martin 写道:
> > > On Sun, Jan 30, 2022 at 5:43 AM Jason Wang wrote:
> > >>
> > >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > >>> Initial ver
On Mon, Feb 21, 2022 at 5:30 AM Peter Maydell
wrote:
> On Wed, 16 Feb 2022 at 17:30, Peter Maydell
> wrote:
> >
> > On Tue, 8 Feb 2022 at 18:18, Patrick Venture wrote:
> > >
> > > From: Shengtan Mao
> > >
> > > Reviewed-by: Hao Wu
> > > Reviewed-by: Chris Rauer
> > > Signed-off-by: Shengtan
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode| 3 +++
target/ppc/translat
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
-#define VSX_MAX_MINC(name, max) \
+#define VSX_MAX_MINC(name, op, tp, fld) \
void helper_##name(CPUPPCState *env,
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Also, fixes these instructions not being capitalized.
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 8
target/ppc/helper.h | 8 ---
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 7 +++
target/ppc/helper.h | 6 +++---
target/ppc/insn32.decode| 3 +++
target/
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 4
target/ppc/helper.h | 3 +++
target/ppc/insn32.decode| 3 +++
target/ppc/tr
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and
prepare the helper to be used for quadword comparisons.
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 3
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+tcg_gen_and_i64(tmp, mask, xb);
+tcg_gen_movcond_i64(TCG_COND_EQ, all_true, tmp,
+mask, all_true, zero);
+
+tcg_gen_andc_i64(tmp, mask, xb);
+tcg_gen_movcond_i64(TCG_COND_EQ, all_fa
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Implement the following PowerISA v3.0 instuctions:
xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd]
xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round
to Odd]
xsnma
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+static bool do_xsmadd(DisasContext *ctx, int tgt, int src1, int src2, int src3,
+void (gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
Missing a * before gen_helper. Somewhat surprised this compiled...
+static boo
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+#define XXGENPCV(NAME, SZ) \
+void helper_##NAME(ppc_vsr_t *t, ppc_vsr_t *b, target_ulong imm)\
+{ \
+ppc_vsr_t tmp = { .u64 = { 0, 0 } };
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+tcg_gen_movi_i64(disj, 0);
The init here means there's one more OR generated than necessary. Though perhaps it gets
folded away...
+
+/* Iterate over set bits from the least to the most significant bit */
+while (imm) {
+
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Following the implementation of tcg_gen_gvec_3i, add a four-vector and
immediate operand expansion method.
Signed-off-by: Matheus Ferst
---
include/tcg/tcg-op-gvec.h | 22 ++
tcg/tcg-op-gvec.c | 146 +
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 1 +
target/ppc/insn64.decode| 8
target/ppc/int_helper.c | 20
target/ppc/translate/vsx-
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 21 ---
target/ppc/helper.h | 2 --
target/ppc/insn32.decode| 5
target/ppc/translate/vsx-impl.c.i
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 4 ++
target/ppc/translate/vsx-impl.c.inc | 71 +
target/ppc/translate/vsx-ops.c.inc | 2 -
3 files changed, 36 in
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 6
target/ppc/insn64.decode| 24
target/ppc/translate/vsx-impl.c.inc | 20 ++
target/ppc/translate
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extended ISA string by app
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 5 +--
target/ppc/insn32.decode| 5 +++
target/ppc/int_helper.c | 13 +-
target/ppc/translate/vmx-impl.c.inc | 69 +
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
v4:
- New in v4.
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 49 +
2 files changed, 50 insertions(+)
...
+
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+static void gen_vrlnm_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
+ TCGv_vec vrb)
+{
+TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt);
+
+/* Create the mask */
+mask = do_vrl_mask_vec(vece, vrb);
+
+
On Tue, Feb 15, 2022 at 7:19 PM Anup Patel wrote:
>
> On Wed, Feb 16, 2022 at 5:39 AM Atish Patra wrote:
> >
> > The Linux kernel parses the ISA extensions from "riscv,isa" DT
> > property. It used to parse only the single letter base extensions
> > until now. A generic ISA extension parsing fram
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
v4:
- New in v4.
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 17 +
2 files changed, 14 insertions(+), 4 deletions(-)
Re
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
v4:
- New in v4.
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +
2 files changed, 41 insertions(+)
diff --
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
v4:
- New in v4.
---
target/ppc/insn32.decode| 5 +
target/ppc/translate/vmx-impl.c.inc | 13 +
target/ppc/translate/vmx-ops.c.inc | 6 ++
3 file
Hey again,
On Tue, Feb 22, 2022 at 10:24 PM Jason A. Donenfeld wrote:
> This thread seems to be long dead, but I couldn't figure out what
> happened to the ideas in it. I'm specifically interested in this part:
>
> On Wed, Feb 24, 2021 at 9:48 AM Adrian Catangiu wrote:
> > +static void vmgenid_a
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
Reviewed-by: Alistair Francis
S
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
v4:
- New in v4.
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +
2 files changed, 31 insertions(+), 10 deleti
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
However, it
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 7 +--
1 file changed, 5
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e5ff4c134c86..60b847141db2 100644
--- a/target
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_bits.h | 39 ++
RISC-V International (RVI) has ratified many RISC-V ISA extensions recently[1].
The privileged specification version is also upgraded to v1.12. It means
certain CSRs introduced in v1.12 should only be accessible only if the
priv specification version supported is equal or greater than v1.12.
Doing
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
v4:
- New in v4.
---
target/ppc/insn32.decode| 17
target/ppc/translate/vmx-impl.c.inc | 41 +++--
target/ppc/translate/vmx-ops.c.in
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Suggested-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
v4:
- Optimized implementation (rth)
---
target/ppc/insn32.decode| 5 ++
target/ppc/translate/vmx-impl.c.inc | 135 ++
From: Wilfred Mallawa
Conenct spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa
---
hw/riscv/opentitan.c | 42
include/hw/riscv/opentitan.h | 16 --
2 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/openti
From: Wilfred Mallawa
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa
---
hw/ssi/ibex_spi_host
On 22/2/22 16:23, Peter Maydell wrote:
In curl_open(), the 'out' label assumes that the state->errmsg string
has been set (either by curl_easy_perform() or by manually copying a
string into it); however if curl_init_state() fails we will jump to
that label without setting the string. Add the mis
On 22/2/22 20:40, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
The socket API wrappers were initially introduced in commit
00aa0040 ("Wrap recv to avoid warnings"), but made redundatant with
commit a2d96af4 ("osdep: add wrappers for socket functions") which fixes
the win32 declara
Hi Adrian,
This thread seems to be long dead, but I couldn't figure out what
happened to the ideas in it. I'm specifically interested in this part:
On Wed, Feb 24, 2021 at 9:48 AM Adrian Catangiu wrote:
> +static void vmgenid_acpi_notify(struct acpi_device *device, u32 event)
> +{
> + uuid
On Mon, Feb 21, 2022 at 1:42 PM Alistair Francis wrote:
>
> On Sun, Feb 6, 2022 at 7:19 PM Atish Patra wrote:
> >
> > To allow/disallow the CSR access based on the privilege spec, a new field
> > in the csr_ops is introduced. It also adds the privileged specification
> > version (v1.12) for the C
On Mon, 21 Feb 2022 at 12:00, Thomas Huth wrote:
>
> Hi!
>
> The following changes since commit e670f6d825d4dee248b311197fd4048469d6772b:
>
> Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into
> staging (2022-02-20 15:05:41 +)
>
> are available in the Git repositor
On 2/22/22 14:34, Bernhard Beschow wrote:
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
Reviewed-by: Stefan Berger
---
hw/tpm/tpm_tis_isa.c | 2 +-
1
From: Marc-André Lureau
The socket API wrappers were initially introduced in commit
00aa0040 ("Wrap recv to avoid warnings"), but made redundatant with
commit a2d96af4 ("osdep: add wrappers for socket functions") which fixes
the win32 declarations and thus removed the earlier warnings.
Signed-of
From: Marc-André Lureau
The headers are now all available in MinGW master branch.
(commit 13390dbbf885f and earlier) aiming for 10.0.
Signed-off-by: Marc-André Lureau
---
qga/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qga/meson.build b/qga/meson.build
index
From: Marc-André Lureau
This is a left-over, despite requesting the change before the merge.
Fixes: commit 8821a389 ("configure, meson: replace VSS SDK checks and options
with --enable-vss-sdk")
Signed-off-by: Marc-André Lureau
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletio
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 40abe86767e8..b1d2fcecbdcf 100644
--- a/meson.build
+++ b/meson.build
@@ -3000,7 +3000,7 @@ libqmp = static_library('qmp',
From: Marc-André Lureau
The VssCoordinator & VssAdmin interfaces have been moved to vsadmin.h in
the Windows SDK.
Signed-off-by: Marc-André Lureau
---
meson.build| 3 +++
qga/vss-win32/vss-common.h | 3 ++-
qga/vss-win32/install.cpp | 4
qga/vss-win32/provider.cpp | 4 +++
isa_init_irq() had become a trivial one-line wrapper for isa_get_irq().
The previous commits resolved all usages in favor of isa_get_irq().
isa_init_irq() can therefore be removed.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 5 -
include/hw/isa/isa.h | 1 -
2 files changed, 6
From: Marc-André Lureau
Hi,
A small collection of patches gleaned while working on different things.
Marc-André Lureau (8):
meson: fix generic location of vss headers
qga/vss-win32: check old VSS SDK headers
qga/vss: update informative message about MinGW
meson: drop the .fa library suf
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/ipmi/isa_ipmi_kcs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ipmi/isa_ipmi_kcs
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/ide/isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
in
From: Marc-André Lureau
One less qemu-specific macro. It also helps to make some headers/units
only depend on glib, and thus moved in standalone projects eventually.
Signed-off-by: Marc-André Lureau
---
audio/audio.h | 4 +--
block/qcow2.h |
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/tpm/tpm_tis_isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/tpm/tpm_tis_isa.c b
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/net/ne2000-isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/ne2000-isa.c b/h
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix
From: Marc-André Lureau
It is only needed by char-pty.
Signed-off-by: Marc-André Lureau
---
include/qemu-common.h | 2 -
chardev/char-pty.c| 104 +++
util/qemu-openpty.c | 139 --
chardev/meson.build | 4 +-
util/m
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/block/fdc-isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/fdc-isa.c b/hw/
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/char/serial-isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/char/serial-isa.c b
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/rtc/m48t59-isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/rtc/m48t59-isa.c b/h
From: Marc-André Lureau
The .fa suffix was a temporary hack introduced in commit
1f0a1d8a51 ("build-sys hack: link with whole .fa archives") when the
build system was mixed between meson & makefiles. It is no longer
needed.
Signed-off-by: Marc-André Lureau
---
docs/devel/build-system.rst|
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/input/pckbd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/
Now that the last users of ISADevice::isairq[] have been resolved during the
previous commits, it can be removed for good.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 13 -
include/hw/isa/isa.h | 2 --
2 files changed, 15 deletions(-)
diff --git a/hw/isa/isa-bus.c b/
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/is
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/char/parallel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/char/parallel.c b/hw/
Determine the IRQ number in the same way as for isa-ipmi-bt. This resolves
the last usage of ISADevice::isairq[] which allows it to be removed.
Signed-off-by: Bernhard Beschow
---
hw/ppc/pnv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
ind
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/audio/cs4231a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/audio/cs4231a.c b/hw/
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/audio/gus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/audio/gus.c b/hw/audio/gu
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/ipmi/isa_ipmi_bt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ipmi/isa_ipmi_bt.c
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/rtc/m48t59-isa.c | 9 -
1 file changed, 8 insertions(+), 1 de
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/audio/sb16.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/audio/sb16.c b/hw/audio/
Exposing the IRQ numbers as a QOM properties not only allows them to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/input/pckbd.c | 26 ++
1 file changed, 2
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 2 +-
hw/rtc/mc146818rtc.c | 13
All isabus_dev_print() did was to print up to two IRQ numbers per
device. This is redundant if the IRQ numbers are present as QOM
properties (see e.g. the modified tests/qemu-iotests/172.out).
Now that the last devices relying on isabus_dev_print() had their IRQ
numbers QOM'ified, the contribution
v2:
The newly QOM'ified devices now report an error to the user in their realize
functions if the configured IRQ number is greater than 15.
v1:
The IRQ attributes of ISADevice are hardcoded to support up to two IRQs per
device which creates an artificial limit. By not having the attributes in the
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 32 +
2 files changed, 25 insertions(+), 8 deletions(-)
Reviewed-by: Ric
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
+{
+TCGv_i64 rb, mh, ml, tmp,
+ ones = tcg_constant_i64(-1),
+ zero = tcg_constant_i64(0);
+
+rb = tcg_temp_new_i64();
+mh = tcg_temp_new_i64();
+
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