On 4/8/22 07:15, Peter Maydell wrote:
Factor out the sequence of looking up a CTE from an ICID including
the validity and error checks.
Signed-off-by: Peter Maydell
---
I think process_movi() in particular is now a lot cleaner
to read with all the error-checking factored out.
---
hw/intc/arm_g
On 4/8/22 07:15, Peter Maydell wrote:
The operation of finding an interrupt table entry given a (DeviceID,
EventID) pair is necessary in multiple different ITS commands. The
process requires first using the DeviceID as an index into the device
table to find the DTE, and then useng the EventID as
On 4/8/22 07:15, Peter Maydell wrote:
In the ItsCmdResult enum, we currently distinguish only CMD_STALL
(failure, stall processing of the command queue) and CMD_CONTINUE
(keep processing the queue), and we use the latter both for "there
was a parameter error, go on to the next command" and "the c
On 4/8/22 07:15, Peter Maydell wrote:
+ "%s: Doorbell 0x%x not 1023 and not a valid LPI\n",
A little confusing for hex not decimal.
Otherwise,
Reviewed-by: Richard Henderson
r~
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 03c6707111..def0f1fdc
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/internals.h | 8
target/arm/syndrome.h | 5 +
target/arm/cpu.c | 38 +++
On 4/8/22 07:15, Peter Maydell wrote:
Implement the GICv4 VMAPP command, which writes an entry to the vPE
table.
For GICv4.1 this command has extra fields in the command packet
and additional behaviour. We define the 4.1-only fields with the
FIELD macro, but only implement the GICv4.0 version of
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Signed-off-by: Richard Henderson
---
target/arm/
Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --gi
Check for and defer any pending virtual SError.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 1 +
target/arm/a32.decode | 16 +-
target/arm/t32.decode | 18 +++
target/arm/op_helper.c | 45 ++
target/
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5d4ca7a227..6521f350f9 1
Add only the system registers required to implement zero error
records. This means we need to save state for ERRSELR, but all
values are out of range, so none of the indexed error record
registers need be implemented.
Add the EL2 registers required for injecting virtual SError.
Signed-off-by: Ri
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 96 ++--
target/arm/cpu_tcg.
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 +
target/arm/cpu64.c | 51 +
target/arm/cpu_tcg.c | 121 ++--
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu_tcg.c
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f20fb6d9e1..03c6707111 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -801,6 +801,7 @@ static void
Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 134 ++
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 23879de5fa..9c456ff23a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4026,6 +4026,11 @@ static inline bool isar_feature_a
I'm implementing the non-JTAG portion of FEAT_Debugv8p2, which
is just making sure that CONTEXTIDR_EL2 is present, even if VHE
is not enabled. Then Debugv8p4 is a trivial extension that only
touches the JTAG interface, so turn that on too.
I've got some cleanups to the setting of isar features fo
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 01f8558fca..2f6b02af7e 100644
--- a/tar
This register is present for either VHE or Debugv8p2, and is
RES0 from EL3 when EL2 is not present. Move the definition
out of vhe_reginfo and provide a fallback for missing EL2.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 25 +
1 file changed, 21 insertio
On Thu, Apr 07, 2022 at 03:36:55PM +0200, Kevin Wolf wrote:
> The specification for VHOST_USER_ADD/REM_MEM_REG messages is unclear
> in several points, which has led to clients having incompatible
> implementations. This changes the specification to be more explicit
> about them:
>
> * VHOST_USER_
On 4/8/22 07:15, Peter Maydell wrote:
The GICv4 defines a new in-guest-memory table for the ITS: this is
the vPE table. Implement the new GITS_BASER2 register which the
guest uses to tell the ITS where the vPE table is located, including
the decode of the register fields into the TableDesc struc
On Thu, Apr 07, 2022 at 03:36:57PM +0200, Kevin Wolf wrote:
> The spec clarifies now that QEMU should not send a file descriptor in a
> request to remove a memory region. Change it accordingly.
>
> For libvhost-user, this is a bug fix that makes it compatible with
> rust-vmm's implementation that
On Thu, Apr 07, 2022 at 03:36:56PM +0200, Kevin Wolf wrote:
> Outside of postcopy mode, neither VHOST_USER_ADD_MEM_REG nor
> VHOST_USER_REM_MEM_REG are supposed to send a reply unless explicitly
> requested with the need_reply flag. Their current implementation always
> sends a reply, even if it is
On 4/8/22 07:15, Peter Maydell wrote:
In process_mapti() we check interrupt IDs to see whether they are
in the valid LPI range. Factor this out into its own utility
function, as we're going to want it elsewhere too for GICv4.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 10 +
On 4/8/22 07:15, Peter Maydell wrote:
In a GICv3, it is impossible for the GIC to deliver a VIRQ or VFIQ to
the CPU unless the CPU has EL2, because VIRQ and VFIQ are only
configurable via EL2-only system registers. Moreover, in our
implementation we were only calculating and updating the state o
On 4/8/22 07:15, Peter Maydell wrote:
We use the common function gicv3_idreg() to supply the CoreSight ID
register values for the GICv3 for the copies of these ID registers in
the distributor, redistributor and ITS register frames. This isn't
quite correct, because while most of the register val
On 4/8/22 07:15, Peter Maydell wrote:
Boards using the GICv3 need to configure it with both the total
number of CPUs and also the sizes of all the memory regions which
contain redistributors (one redistributor per CPU). At the moment
the GICv3 checks that the number of CPUs specified is not too
On 4/8/22 07:15, Peter Maydell wrote:
In the GICv3 code we implicitly rely on there being at least one CPU
and thus at least one redistributor and CPU interface. Sanity-check
that the property the board code sets is not zero.
Signed-off-by: Peter Maydell
---
Doing this would be a board code err
On 4/8/22 07:15, Peter Maydell wrote:
In commit b6f96009acc we split do_process_its_cmd() from
process_its_cmd(), but forgot the usual blank line between function
definitions. Add it.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by
assert(dbs->acb) is meant to check the return value of io_func per
documented in commit 6bee44ea34 ("dma: the passed io_func does not
return NULL"). However, there is a chance that after calling
aio_context_release(dbs->ctx); the dma_blk_cb function is called before
the assertion and dbs->acb is se
On Mon, Mar 28, 2022 at 10:17 AM Andy Lutomirski wrote:
>
> On Thu, Mar 10, 2022 at 6:09 AM Chao Peng wrote:
> >
> > This is the v5 of this series which tries to implement the fd-based KVM
> > guest private memory. The patches are based on latest kvm/queue branch
> > commit:
> >
> > d5089416b7f
On 4/8/22 10:13, Frederic Barrat wrote:
This patch skips [de]asserting a LSI interrupt if the device doesn't
have any LSI defined. Doing so would trigger an assert in
pci_irq_handler().
The PCIE root port implementation in qemu requests a LSI (INTA), but a
subclass may want to change that beh
On 4/8/22 10:13, Frederic Barrat wrote:
The phb3/phb4/phb5 root ports inherit from the default PCIE root port
implementation, which requests a LSI interrupt (#INTA). On real
hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch
corrects it so that it matches the hardware.
As a co
17.03.2022 00:28, Eric Blake wrote:
+++ b/qapi/block-export.json
@@ -6,6 +6,7 @@
##
{ 'include': 'sockets.json' }
+{ 'include': 'block-core.json' }
Hmm. Does this extra inclusion negatively impact qemu-storage-daemon,
since that is why we created block-export.json in the first place (to
On 4/6/22 07:08, Bin Meng wrote:
On Tue, Apr 5, 2022 at 10:36 PM Guo Zhi wrote:
There are still some files in the QEMU PPC code base that use TABs for
indentation instead of using spaces.
The TABs should be replaced so that we have a consistent coding style.
If this patch is applied, iss
On 08.04.22 19:56, Sean Christopherson wrote:
> On Thu, Apr 07, 2022, Andy Lutomirski wrote:
>>
>> On Thu, Apr 7, 2022, at 9:05 AM, Sean Christopherson wrote:
>>> On Thu, Mar 10, 2022, Chao Peng wrote:
Since page migration / swapping is not supported yet, MFD_INACCESSIBLE
memory behave li
On Thu, Apr 07, 2022, Andy Lutomirski wrote:
>
> On Thu, Apr 7, 2022, at 9:05 AM, Sean Christopherson wrote:
> > On Thu, Mar 10, 2022, Chao Peng wrote:
> >> Since page migration / swapping is not supported yet, MFD_INACCESSIBLE
> >> memory behave like longterm pinned pages and thus should be accou
On Fri, Apr 08, 2022, Chao Peng wrote:
> On Mon, Mar 28, 2022 at 09:56:33PM +, Sean Christopherson wrote:
> > struct kvm_userspace_memory_region_ext {
> > #ifdef __KERNEL__
>
> Is this #ifndef? As I think anonymous struct is only for kernel?
Doh, yes, I inverted that.
> Thanks,
> Chao
>
> >
On 4/8/2022 1:38 AM, Michael Qiu wrote:
在 2022/4/7 15:35, Jason Wang 写道:
在 2022/4/2 下午1:14, Michael Qiu 写道:
On 2022/4/2 10:38, Jason Wang wrote:
在 2022/4/1 下午7:06, Michael Qiu 写道:
Currently in vhost framwork, vhost_reset_device() is misnamed.
Actually, it should be vhost_reset_owner(
From: Guohuai Shi
Extend the 9p local file system backend driver to support Windows,
including open, read, write, close, rename, remove, etc.
Symbolic link, link, chmod, renameat, unlinkat and extended attribute
are not supported due to limitations on Windows host.
Signed-off-by: Guohuai Shi
S
From: Guohuai Shi
Enable virtfs configuration option for Windows host.
Signed-off-by: Guohuai Shi
Signed-off-by: Bin Meng
---
meson.build | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/meson.build b/meson.build
index 861de93c4f..a609a9e98f 100644
--- a/meson.b
From: Guohuai Shi
Only 'local' file system driver will be supported for Windows host.
'proxy' or 'synth' are not supported.
Signed-off-by: Guohuai Shi
Signed-off-by: Bin Meng
---
fsdev/qemu-fsdev.c | 2 ++
fsdev/meson.build | 1 +
2 files changed, 3 insertions(+)
diff --git a/fsdev/qemu-fs
At present there is no Windows support for 9p file system.
This series adds initial Windows support for 9p file system.
Only 'local' file system driver backend is supported. security_model
should be 'none' due to limitations on Windows host.
Example command line to test:
"-fsdev local,path=c:\
The method is not popular, we prefer use vm.qmp() and then check
success by hand.. But that's not optimal. To simplify movement to
vm.command() support same interface improvements like in vm.qmp() and
rename to shorter vm.cmd().
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
python/qemu/machine
Sometimes the whole execlog is just two much so add the ability to
filter by instruction opcode or address.
[AJB: this shows for example
.qemu-system-aarch64 -display none -serial mon:stdio \
-M virt -cpu max \
-semihosting-config enable=on \
-kernel ./tests/tcg/aarch64-softmmu/memory-s
From: Guohuai Shi
Add uid_t, gid_t and struct statfs definitions, which are currently
missing from Windows headers, but are required when we add 9p file
system support for Windows in later patches.
Signed-off-by: Guohuai Shi
Signed-off-by: Bin Meng
---
fsdev/file-op-9p.h | 33 +++
Hi all!
I always dreamed about getting rid of pattern
result = self.vm.qmp(...)
self.assert_qmp(result, 'return', {})
Here is a suggestion to switch to
self.vm.cmd(...)
pattern instead.
I'm not sure we really want to update so many tests. May be just commit
patch 01, and use new i
Signed-off-by: Alex Bennée
---
accel/tcg/translate-all.c | 2 ++
accel/tcg/trace-events| 1 +
2 files changed, 3 insertions(+)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index e9f1cc179d..b0009177b9 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.
QEMU 7.1 won't support Ubuntu 18.04 anymore, so the last big important
distro that did not have a pre-packaged libslirp has been dismissed.
All other major distros seem to have a libslirp package in their
distribution already - according to repology.org:
Fedora 34: 4.4.0
CentOS 8 (RHEL
These events can be very expensive for the translator so lets add a
tracepoint to help with debugging what might be causing them. Clean up
the comments while we are at it.
Signed-off-by: Alex Bennée
---
accel/tcg/translate-all.c | 15 +++
accel/tcg/trace-events| 1 +
2 files cha
This is a dumb attempt to reduce to the execution time of UEFI booted
kernels and almost certainly not what the final solution should be.
The problem is if we have generated JIT code from running firmware we
can spend a lot of time carefully invalidating every TB in a page when
the kernel that eve
This helps track when pages are tagged for detecting code changes.
Signed-off-by: Alex Bennée
---
accel/tcg/cputlb.c | 14 ++
accel/tcg/trace-events | 3 +++
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 35797cea49.
This will be helpful in debugging problems with tracking SVE memory
accesses via the TCG plugins system.
Signed-off-by: Alex Bennée
Cc: Robert Henry
Cc: Aaron Lindsay
---
tests/tcg/aarch64/Makefile.softmmu-target | 7 +++
tests/tcg/aarch64/system/boot.S | 3 ++-
2 files changed,
From: Richard Henderson
Coverity reports out-of-bound accesses here. This should be a
false positive due to how the index is decoded from MemOpIdx.
Fixes: Coverity CID 1487201
Signed-off-by: Richard Henderson
Reviewed-by: Damien Hedde
Message-Id: <20220401190233.329360-1-richard.hender...@lin
The Fedora 29 kernel is quite old and importantly fails when running
in LPA2 scenarios. As it's not really exercising much of the CPU space
replace it with a custom 5.16.12 kernel with all the architecture
options turned on. There is a minimal buildroot initramfs included in
the kernel which has a
This helps us construct strings elsewhere before echoing to the
monitor. It avoids having to jump through hoops like:
monitor_printf(mon, "%s", s->str);
Signed-off-by: Alex Bennée
---
include/monitor/monitor.h | 1 +
monitor/monitor-internal.h | 1 -
2 files changed, 1 insertion(+), 1 deleti
This gives a little more insight into what is going on as we
invalidate a range of TBs.
Signed-off-by: Alex Bennée
---
accel/tcg/translate-all.c | 9 +
accel/tcg/trace-events| 1 +
2 files changed, 10 insertions(+)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
i
This gets especially confusing if you start plugging in host addresses
from a trace and you wonder why the output keeps changing. Report when
read_memory_func fails instead of blindly disassembling the buffer
contents.
Signed-off-by: Alex Bennée
---
disas.c | 20 ++---
disas/cap
Signed-off-by: Alex Bennée
---
accel/tcg/cputlb.c | 2 +-
accel/tcg/trace-events | 4
trace-events | 4
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2035b2ac0a..35797cea49 100644
--- a/accel/tcg/cputlb.c
+++ b
This was confusing and in the case of qtest was hiding the details of
the qgraph sub-document in the qtest pages.
Signed-off-by: Alex Bennée
---
docs/devel/index-api.rst | 1 -
docs/devel/index-build.rst | 3 +--
docs/devel/index-internals.rst | 1 -
docs/devel/index-process.rst | 1
Hi,
In anticipation of the tree re-opening soon I thought flush the
current state of my maintainer trees. We have a change for testing, a
couple of documentation updates, some refactoring of disassembly
handling and additional tracepoints for diagnosing cputlb issues.
There is also a hack for spee
We document some of this on the wiki but lets move it into our
official developer notes documentation.
Signed-off-by: Alex Bennée
Cc: Paolo Bonzini
---
v2
- fix some trailing ws
---
docs/devel/testing.rst | 38 ++
1 file changed, 38 insertions(+)
diff --g
Rather than assembling our output piecemeal lets use the same approach
as the plugin disas interface to build the disassembly string before
printing it.
Signed-off-by: Alex Bennée
---
disas.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/disas.c b/d
Richard Henderson writes:
> Coverity reports out-of-bound accesses here. This should be a
> false positive due to how the index is decoded from MemOpIdx.
>
> Fixes: Coverity CID 1487201
> Signed-off-by: Richard Henderson
Queued to plugins/next, thanks.
--
Alex Bennée
There is an overflow with the current code where a pmpaddr value of
0x1fff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
ea=0x.
Fix that by simplifying the computation. There is in fact no need for
ctz64() nor special case for -1 to achieve proper results.
Signed-off-by
We don't have a virtio-gpio implementation in QEMU and only
support a vhost-user backend. The QEMU side of the code is minimal so
it should be enough to instantiate the device and pass some vhost-user
messages over the control socket. To do this we hook into the existing
vhost-user-test code and ju
On 4/8/22 05:21, Redha Gouicem wrote:
We are working on support for x86_64 emulation on aarch64, mainly
related to memory ordering issues. We first wanted to know what the
community thinks about our proposal, and its chance of getting merged
one day.
Note that we worked with qemu-user, so there
On Fri, 8 Apr 2022 at 15:59, Itaru Kitayama wrote:
> I'd like to add a64fx cpu to the sbsa-ref board, if there's a quick and dirty
> way of completing that, advice from the maintainers is greatly appreciated.
I have cc'd the sbsa-ref maintainers (as listed in the MAINTAINERS file).
However, I'm
On 07.04.22 15:27, Vladimir Sementsov-Ogievskiy wrote:
Add two simple test-cases: timeout failure with
break-snapshot-on-cbw-error behavior and similar with
break-guest-write-on-cbw-error behavior.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/tests/copy-before-write|
On 07.04.22 15:27, Vladimir Sementsov-Ogievskiy wrote:
Add tests for new option of copy-before-write filter: on-cbw-error.
Note that we use QEMUMachine instead of VM class, because in further
commit we'll want to use throttling which doesn't work with -accel
qtest used by VM.
We also touch pyli
We are working on support for x86_64 emulation on aarch64, mainly
related to memory ordering issues. We first wanted to know what the
community thinks about our proposal, and its chance of getting merged
one day.
Note that we worked with qemu-user, so there may be issues in system
mode that we mis
On Fri, 08 Apr 2022 15:52:25 +0200
Christian Schoenebeck wrote:
> On Sonntag, 27. Februar 2022 23:35:20 CEST Will Cohen wrote:
> > From: Keno Fischer
> >
> > Darwin does not support mknodat. However, to avoid race conditions
> > with later setting the permissions, we must avoid using mknod on
>
Hi,
I'd like to add a64fx cpu to the sbsa-ref board, if there's a quick and dirty
way of completing that, advice from the maintainers is greatly appreciated.
Thanks,
Itaru.
On 4/7/22 08:27, Kirill A. Shutemov wrote:
The fast path does not clear the bits, so you enter the slow path before you
get to clearing the bits. You've lost most of the advantage of the tlb
already.
Sorry for my ignorance, but what do you mean by fast path here?
My understanding is that it i
Add support for the TCG GICv4 to the virt board. For the board,
the GICv4 is very similar to the GICv3, with the only difference
being the size of the redistributor frame. The changes here are thus:
* calculating virt_redist_capacity correctly for GICv4
* changing various places which were "if GI
On Fri, 8 Apr 2022 at 15:15, Peter Maydell wrote:
>
> This patchset implements emulation of GICv4 in our TCG GIC and ITS
> models, and makes the virt board use it where appropriate.
> Tested with a Linux kernel passing through a virtio-blk device
> to an inner Linux VM with KVM/QEMU. (NB that to
Implement the gicv3_redist_vinvall() function (previously left as a
stub). This function handles the work of a VINVALL command: it must
invalidate any cached information associated with a specific vCPU.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_redist.c | 8 +++-
1 file changed, 7
Implement the function gicv3_redist_inv_vlpi(), which was previously
left as a stub. This is the function that does the work of the INV
command for a virtual interrupt.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_redist.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff
In several places in virt.c we calculate the number of redistributors that
fit in a region of our memory map, which is the size of the region
divided by the size of a single redistributor frame. For GICv4, the
redistributor frame is a different size from that for GICv3. Abstract
out the calculation
The guest uses GICR_VPENDBASER to tell the redistributor when it is
scheduling or descheduling a vCPU. When it writes and changes the
VALID bit from 0 to 1, it is scheduling a vCPU, and we must update
our view of the current highest priority pending vLPI from the new
Pending and Configuration tabl
Implement the gicv3_redist_mov_vlpi() function (previously left as a
stub). This function handles the work of a VMOVI command: it marks
the vLPI not-pending on the source and pending on the destination.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_redist.c | 20 ++--
1 fil
Everywhere we need to check which GIC version we're using, we look at
vms->gic_version and use the VIRT_GIC_VERSION_* enum values, except
in create_gic(), which copies vms->gic_version into a local 'int'
variable and makes direct comparisons against values 2 and 3.
For consistency, change this fun
Implement the function gicv3_redist_process_vlpi(), which was left as
just a stub earlier. This function deals with being handed a VLPI by
the ITS. It must set the bit in the pending table. If the vCPU is
currently resident we must recalculate the highest priority pending
vLPI; otherwise we may
Now that we have implemented all the GICv4 requirements, relax the
error-checking on the GIC object's 'revision' property to allow a TCG
GIC to be a GICv4, whilst still constraining the KVM GIC to GICv3.
Our 'revision' property doesn't consider the possibility of wanting
to specify the minor versi
Factor out the common part of gicv3_redist_update_lpi_only() into
a new function update_for_all_lpis(), which does a full rescan
of an LPI Pending table and sets the specified PendingIrq struct
with the highest priority pending enabled LPI it finds.
Signed-off-by: Peter Maydell
---
hw/intc/arm_g
Update the various GIC ID and feature registers for GICv4:
* PIDR2 [7:4] is the GIC architecture revision
* GICD_TYPER.DVIS is 1 to indicate direct vLPI injection support
* GICR_TYPER.VLPIS is 1 to indicate redistributor support for vLPIs
* GITS_TYPER.VIRTUAL is 1 to indicate vLPI support
* GI
Implement the function gicv3_redist_vlpi_pending(), which was
previously left as a stub. This is the function that is called by
the CPU interface when it changes the state of a vLPI. It's similar
to gicv3_redist_process_vlpi(), but we know that the vCPU is
definitely resident on the redistributor
The function gicv3_cpuif_virt_update() currently sets all of vIRQ,
vFIQ and the maintenance interrupt. This implies that it has to be
used quite carefully -- as the comment notes, setting the maintenance
interrupt will typically cause the GIC code to be re-entered
recursively. For handling vLPIs,
We can use our new set_pending_table_bit() utility function
in gicv3_redist_mov_lpi() to clear the bit in the source
pending table, rather than doing the "load, clear bit, store"
ourselves.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_redist.c | 9 +
1 file changed, 1 insertion(+),
Factor out the code which sets a single bit in an LPI pending table.
We're going to need this for handling vLPI tables, not just the
physical LPI table.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_redist.c | 49 +++---
1 file changed, 30 insertions(+), 19 d
The GICv4 extends the redistributor register map -- where GICv3
had two 64KB frames per CPU, GICv4 has four frames. Add support
for the extra frame by using a new gicv3_redist_size() function
in the places in the GIC implementation which currently use
a fixed constant size for the redistributor reg
Currently the functions which update the highest priority pending LPI
information by looking at the LPI Pending and Configuration tables
are hard-coded to use the physical LPI tables addressed by
GICR_PENDBASER and GICR_PROPBASER. To support virtual LPIs we will
need to do essentially the same job
Implement the ITS side of the handling of the INV command for
virtual interrupts; as usual this calls into a redistributor
function which we leave as a stub to fill in later.
Signed-off-by: Peter Maydell
---
hw/intc/gicv3_internal.h | 9 +
hw/intc/arm_gicv3_its.c| 16 +
For GICv4, interrupt table entries read by process_its_cmd() may
indicate virtual LPIs which are to be directly injected into a VM.
Implement the ITS side of the code for handling this. This is
similar to the existing handling of physical LPIs, but instead of
looking up a collection ID in a collec
The maintenance interrupt state depends only on:
* ICH_HCR_EL2
* ICH_LR_EL2
* ICH_VMCR_EL2 fields VENG0 and VENG1
Now we have a separate function that updates only the vIRQ and vFIQ
lines, use that in places that only change state that affects vIRQ
and vFIQ but not the maintenance interrupt.
S
Implement the GICv4 VMOVP command, which updates an entry in the vPE
table to change its rdbase field. This command is unique in the ITS
command set because its effects must be propagated to all the other
ITSes connected to the same GIC as the ITS which executes the VMOVP
command.
The GICv4 spec a
The CPU interface changes to support vLPIs are fairly minor:
in the parts of the code that currently look at the list registers
to determine the highest priority pending virtual interrupt, we
must also look at the highest priority pending vLPI. To do this
we change hppvi_index() to check the vLPI a
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