The original NVDIMM _DSM functions (index 4~6) for label operations have
been deprecated by new ACPI methods _LS{I,R,W}[1][2].
Patch 1 implements the new _LS{I,R,W} methods, on top of old _DSM
implementation.
Patch 2 fixes some typo of logical and/or with bitwise and/or, though
functionally they
On Mon, 11 Apr 2022, Kirill A. Shutemov wrote:
> On Fri, Apr 08, 2022 at 09:02:54PM +0800, Chao Peng wrote:
> > > I think the correct approach is to not do the locking automatically for
> > > SHM_F_INACCESSIBLE,
> > > and instead require userspace to do shmctl(.., SHM_LOCK, ...) if
> > >
On Tue, Apr 5, 2022 at 3:34 AM Ralf Ramsauer
wrote:
>
> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> case, walk_pte will erroneously merge them.
>
> Enforce the split up, by tracking the virtual base address.
>
> Let's say we have the mapping:
> 0x8120 -> 0x89623000
On Fri, Apr 1, 2022 at 10:18 PM Ralf Ramsauer
wrote:
>
> The -bios option is silently ignored if used in combination with -enable-kvm.
> The reason is that the machine starts in S-Mode, and the bios typically runs
> in
> M-Mode.
>
> Better exit in that case to not confuse the user.
>
>
On Tue, Apr 12, 2022 at 9:50 AM Ani Sinha wrote:
>
> On Tue, Mar 8, 2022 at 10:28 PM Michael S. Tsirkin wrote:
> >
> > On Tue, Mar 08, 2022 at 10:15:49PM +0530, Ani Sinha wrote:
> > >
> > > Change log:
> > > v2: rebased the patchset. Laine's response is appended at the end.
> > >
> > > I am
On Tue, Mar 8, 2022 at 10:28 PM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 10:15:49PM +0530, Ani Sinha wrote:
> >
> > Change log:
> > v2: rebased the patchset. Laine's response is appended at the end.
> >
> > I am re-introducing the patchset for which got
> > reverted here few months
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vmodsq: Vector Modulo Signed Quadword
vmoduq: Vector Modulo Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel)
---
target/ppc/helper.h
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Doubleword
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivesd: Vector Divide Extended Signed Doubleword
vdiveud: Vector Divide Extended Unsigned Doubleword
vdivesq: Vector Divide Extended Signed Quadword
On Fri, Apr 1, 2022 at 5:48 PM Ralf Ramsauer
wrote:
>
> The -bios option is silently ignored if used in combination with -enable-kvm.
> The reason is that the machine starts in S-Mode, and the bios typically runs
> in
> M-Mode.
>
> Better exit in that case to not confuse the user.
>
>
On Thu, Jan 27, 2022 at 1:27 PM Patrick Venture wrote:
>
>
> On Thu, Jan 27, 2022 at 10:37 AM Peter Maydell
> wrote:
>
>> On Mon, 10 Jan 2022 at 17:56, Patrick Venture wrote:
>> >
>> > From: Hao Wu
>> >
>> > The PCI Mailbox Module is a high-bandwidth communcation module
>> > between a Nuvoton
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Based on already existing QEMU implementation, created an unsigned 256
bit by 128 bit division needed to implement the vector divide extended
unsigned instruction from PowerISA3.1
Signed-off-by: Lucas
The virt machine has many generic functions that can be used by
other machines. Move these functions to a helper file so that other
machines can use it in the future.
Signed-off-by: Atish Patra
---
hw/riscv/machine_helper.c | 417 ++
hw/riscv/meson.build
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/374
There are still some files in the QEMU PPC code base that use TABs for
indentation instead of using spaces. The TABs should be replaced so that we
have a consistent coding style.
Signed-off-by: Guo Zhi
---
hw/ppc/ppc440_bamboo.c |
The seria-pci device doesn't support MSI. Enable the device to provide
MSI so that any platform with MSI support only can also use
this serial device. MSI can be enabled by enabling the newly introduced
device property. This will be disabled by default preserving the current
behavior of the
The RISC-V virt machine has helped RISC-V software eco system to evolve at a
rapid pace even in absense of the real hardware. It is definitely commendable.
However, the number of devices & commandline options keeps growing as a result
of that as well. That adds flexibility but will also become
The RISC-V virt machine has been growing with many different commmandline
options. It has its limitations in terms of maximum number of harts that
it can support. The commandline options slowly will become bit difficult
to manage. Moreover, it always depends on the virtio framework and lot
of mmio
Hi Drew,
On 4/11/22 8:02 PM, Andrew Jones wrote:
On Mon, Apr 11, 2022 at 10:22:59AM +0100, Peter Maydell wrote:
On Mon, 11 Apr 2022 at 07:59, Gavin Shan wrote:
There are two arrays for each CPU, to store the indexes and values of the
coprocessor registers. Currently, 8 bytes fixed storage
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivesw: Vector Divide Extended Signed Word
vdiveuw: Vector Divide Extended Unsigned Word
Signed-off-by: Lucas Mateus Castro (alqotel)
---
Hi Peter,
On 4/11/22 6:05 PM, Peter Maydell wrote:
On Mon, 11 Apr 2022 at 10:50, Gavin Shan wrote:
On 4/11/22 5:22 PM, Peter Maydell wrote:
So, can you give an example of coprocessor registers which are
not 8 bytes in size? How are they accessed by the guest?
If we need to support them then
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivsq: Vector Divide Signed Quadword
vdivuq: Vector Divide Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel)
---
target/ppc/helper.h
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
On Thu, Mar 24, 2022 at 9:48 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
>
> [1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h
>
> Signed-off-by: Bin Meng
> ---
>
> (no changes since v1)
>
>
On Fri, Apr 1, 2022 at 8:19 PM Ralf Ramsauer
wrote:
>
> The -bios option is silently ignored if used in combination with -enable-kvm.
> The reason is that the machine starts in S-Mode, and the bios typically runs
> in
> M-Mode.
>
> Better exit in that case to not confuse the user.
>
>
Enable the n1 for virt and sbsa board use.
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed, 69 insertions(+)
diff
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy
Update isar fields per ARM DDI0487 H.a.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Add ID_AA64DFR0.HPMN0
---
target/arm/cpu.h | 24
1 file changed, 24 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7ca2463e17..6793336b5e
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Retain m-profile check; improve comments.
---
target/arm/helper.h| 1 +
target/arm/a32.decode | 16 --
target/arm/t32.decode | 18
Enable the a76 for virt and sbsa board use.
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed, 69 insertions(+)
diff
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Signed-off-by: Richard Henderson
---
v2: Honor EAE for reporting VSERR to aa32.
---
target/arm/cpu.h | 2 ++
target/arm/internals.h | 8
target/arm/syndrome.h
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
2
Add only the system registers required to implement zero error
records. This means we need to save state for ERRSELR, but all
values are out of range, so none of the indexed error record
registers need be implemented.
Add the EL2 registers required for injecting virtual SError.
Signed-off-by:
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter Maydell
Signed-off-by:
Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
1 file
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 96
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 +
target/arm/cpu64.c | 50 +-
target/arm/cpu_tcg.c | 114
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Signed-off-by: Richard Henderson
---
v2: New patch.
---
target/arm/internals.h | 6
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 4
1 file changed, 4 insertions(+)
diff
Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.
Signed-off-by: Richard Henderson
---
v2: Create impdef sysregs; only enable
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 23879de5fa..9c456ff23a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4026,6 +4026,11 @@
This register is present for either VHE or Debugv8p2, and is
RES0 from EL3 when EL2 is not present. Move the definition
out of vhe_reginfo and provide a fallback for missing EL2.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 25 +
For v2, combine two previous patch sets and address comments.
Patches lacking review:
03-target-arm-Move-cortex-impdef-sysregs-to-cpu_tcg..patch
04-target-arm-Update-qemu-system-arm-cpu-max-to-cort.patch
06-target-arm-Split-out-arm32_max_features.patch
On Fri, Apr 1, 2022 at 11:00 PM Richard Henderson
wrote:
>
> If an atomic operation fails on RISC-V, we want to generate
> a store/amo fault and not a load fault.
>
> Annotate amo insns, so that we can recognize them after unwinding.
> Transform the implementation access type to store/amo for
On Fri, Apr 1, 2022 at 10:18 PM Ralf Ramsauer
wrote:
>
> The -bios option is silently ignored if used in combination with -enable-kvm.
> The reason is that the machine starts in S-Mode, and the bios typically runs
> in
> M-Mode.
>
> Better exit in that case to not confuse the user.
>
>
On 4/11/22 11:30, Richard Henderson wrote:
cpu->isar.dbgdidr
"If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and
deprecated."
Which we already handle in define_debug_regs by not defining DBGDIDR if this
value is 0.
r~
According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
bus number, this makes the ECAM max size equal to '1 << 28'. This patch
restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
changed in commit 58d5b22bbd5 ("ppc4xx: Add device models found in PPC440
core
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits). Below is the formula taken from Table
7-1 in [1].
"
Memory Address | PCI Express Configuration Space
A[(20+n-1):20] | Bus Number, 1 ≤ n ≤ 8
"
[1] PCI Express® Base Specification Revision 5.0
Hi,
This series attempts to correct a couple of defines inside pcie_host.h.
Best regards,
Francisco Iglesias
Changelog:
v1->v2:
* Went from RFC to patch proposal
* Added more meat on the commit message of patch 1
Francisco Iglesias (2):
include/hw/pci/pcie_host: Correct
Hi Michael,
On [2022 Apr 11] Mon 17:12:47, Michael S. Tsirkin wrote:
> On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote:
> > According to [1] address bits 27 - 20 are mapped to the bus number (the
> > TLPs bus number field is 8 bits).
> >
> > [1] PCI Express® Base Specification
On 4/11/22 09:18, Peter Maydell wrote:
+ ESB 0011 0010 0001
+]
Why don't we decode bits [11:8] here? I see it's the same
as YIELD/WFE/WFI, but I'm not sure why we're not decoding
those bits in those insns either...
See page F4-7074 in H.a, where bits
On 11/4/22 11:47, jianchunfu wrote:
Using macro g_new() to handling potential memory allocation failures
in dirtyrate.
Signed-off-by: jianchunfu
---
migration/dirtyrate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c
On 4/11/22 09:32, Peter Maydell wrote:
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Signed-off-by: Richard Henderson
@@ -10041,6 +10048,20 @@ static void
On 4/11/22 08:49, Peter Maydell wrote:
+{ .name = "ERRSELR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 1,
+ .access = PL1_RW, .accessfn = access_terr,
+ .fieldoffset = offsetof(CPUARMState, cp15.errselr_el1) },
By my reading of the
On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote:
> According to [1] address bits 27 - 20 are mapped to the bus number (the
> TLPs bus number field is 8 bits).
>
> [1] PCI Express® Base Specification Revision 5.0 Version 1.0
>
> Signed-off-by: Francisco Iglesias
> ---
>
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias
---
include/hw/pci/pcie_host.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
* Claudio Fontana (cfont...@suse.de) wrote:
> On 4/7/22 3:57 PM, Claudio Fontana wrote:
> > On 4/7/22 3:53 PM, Dr. David Alan Gilbert wrote:
> >> * Claudio Fontana (cfont...@suse.de) wrote:
> >>> On 4/5/22 10:35 AM, Dr. David Alan Gilbert wrote:
> * Claudio Fontana (cfont...@suse.de) wrote:
>
On 4/11/22 11:09, Peter Maydell wrote:
+cpu->isar.id_aa64pfr0 = 0x11001012ull;
This has the GIC field clear. On the one hand this is true
also of all our other CPU implementations. On the other hand
if we wire up a GICv3 in the board code then we will be
presenting the GIC CPU
On 4/7/22 3:57 PM, Claudio Fontana wrote:
> On 4/7/22 3:53 PM, Dr. David Alan Gilbert wrote:
>> * Claudio Fontana (cfont...@suse.de) wrote:
>>> On 4/5/22 10:35 AM, Dr. David Alan Gilbert wrote:
* Claudio Fontana (cfont...@suse.de) wrote:
> On 3/28/22 10:31 AM, Daniel P. Berrangé wrote:
On Sun, 10 Apr 2022 at 07:15, Richard Henderson
wrote:
>
> Enable the n1 for virt and sbsa board use.
>
> Signed-off-by: Richard Henderson
> ---
Comments on previous patch apply here too, by and large.
thanks
-- PMM
On Sun, 10 Apr 2022 at 07:13, Richard Henderson
wrote:
>
> Enable the a76 for virt and sbsa board use.
>
> Signed-off-by: Richard Henderson
> ---
> hw/arm/sbsa-ref.c | 1 +
> hw/arm/virt.c | 1 +
> target/arm/cpu64.c | 64 ++
> 3 files
On 4/11/22 02:47, jianchunfu wrote:
Using macro g_new() to handling potential memory allocation failures
in dirtyrate.
Signed-off-by: jianchunfu
---
migration/dirtyrate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On Mon, 11 Apr 2022 at 14:09, Peter Maydell wrote:
>
> On Sat, 9 Apr 2022 at 01:18, Richard Henderson
> wrote:
> >
> > The only portion of FEAT_Debugv8p2 that is relevant to QEMU
> > is CONTEXTIDR_EL2, which is also conditionally implemented
> > with FEAT_VHE. The rest of the debug extension
On Sun, 10 Apr 2022 at 07:03, Richard Henderson
wrote:
>
> There is no branch prediction in TCG, therefore there is no
> need to actually include the context number into the predictor.
> Therefore all we need to do is add the state for SCXTNUM_ELx.
>
> Signed-off-by: Richard Henderson
> ---
>
On Mon, 11 Apr 2022 at 17:56, Paolo Bonzini wrote:
> Yeah, I actually wrote the memcpy() invocation because I was going to
> look at AVX later this year, which of course you couldn't know. :)
> What I came up after stealing parts of your nice comment is the
> following:
>
> /*
> * Copy the
Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
include/hw/misc/npcm7xx_gcr.h | 30 ++
1 file changed, 30 insertions(+)
diff
On Sun, 10 Apr 2022 at 07:07, Richard Henderson
wrote:
>
> This extension concerns not merging memory access, which TCG does
> not implement. Thus we can trivially enable this feature.
> Add a comment to handle_hint for the DGH instruction, but no code.
>
> Signed-off-by: Richard Henderson
>
This patch uses the defined fields to describe PWRON STRAPs for
better readability.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
Currently, the PWRON STRAP values in NPCM7XX boards are magic
numbers. Similar to the aspeed ones in hw/arm/aspeed.c, we
define bit fields constants for them and use these fields instead
of the magic numbers in the current implementation. The code
should behave exactly the same as the existing
On Sun, 10 Apr 2022 at 07:07, Richard Henderson
wrote:
>
> This extension concerns cache speculation, which TCG does
> not implement. Thus we can trivially enable this feature.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 1 +
> 2 files
On 4/11/22 17:18, Peter Maydell wrote:
Looking a bit more closely, this won't work on big-endian
hosts, because there we want to copy across the last 16
bytes of the struct, not the first 16. So I think we need
some more macro magic:
#if SHIFT == 0
#define COPY_REG(DEST, SRC) (DEST) = (SRC)
Sure, I will send a v2 patch.
Thanks,
Guo
- Original Message -
From: "Daniel Henrique Barboza"
To: "Thomas Huth" , "Bin Meng"
Cc: "Guo Zhi" , "Cédric Le Goater" ,
"David Gibson" , "Greg Kurz" ,
"qemu-ppc" , "qemu-devel@nongnu.org Developers"
, "Peter Maydell" , "open
list:RISC-V"
On Sun, 10 Apr 2022 at 06:58, Richard Henderson
wrote:
>
> Update isar fields per ARM DDI0487 H.a.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 23 +++
> 1 file changed, 23 insertions(+)
> @@ -2067,7 +2087,9 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
>
On Sun, 10 Apr 2022 at 06:58, Richard Henderson
wrote:
>
> This extension concerns branch speculation, which TCG does
> not implement. Thus we can trivially enable this feature.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 1 +
Reviewed-by:
On Sat, 9 Apr 2022 at 01:23, Richard Henderson
wrote:
>
> This feature is AArch64 only, and applies to physical SErrors,
> which QEMU does not implement, thus the feature is a nop.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Virtual SError exceptions are raised by setting HCR_EL2.VSE,
> and are routed to EL1 just like other virtual exceptions.
>
> Signed-off-by: Richard Henderson
> @@ -10041,6 +10048,20 @@ static void arm_cpu_do_interrupt_aarch32(CPUState
>
On Sat, 9 Apr 2022 at 01:14, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 1 +
> 2 files changed, 2 insertions(+)
Reviewed-by: Peter Maydell
thanks
-- PMM
On 4/11/22 04:23, Thomas Huth wrote:
On 11/04/2022 08.57, Bin Meng wrote:
On Mon, Apr 11, 2022 at 2:45 PM Thomas Huth wrote:
On 08/04/2022 21.19, Daniel Henrique Barboza wrote:
On 4/6/22 07:08, Bin Meng wrote:
On Tue, Apr 5, 2022 at 10:36 PM Guo Zhi wrote:
There are still some
On 4/11/22 10:47, Anthony PERARD wrote:
From: Anthony PERARD
At the moment, there doesn't seems to be any way to know that QEMU
made modification to the command buffer. This is potentially an issue
on Xen while migrating a guest, as modification to the buffer after
the migration as started
On 4/11/22 08:37, Peter Maydell wrote:
+/* aarch64_a57_initfn, advertising none of the aarch64 features */
+cpu->dtb_compatible = "arm,cortex-a57";
+set_feature(>env, ARM_FEATURE_V8);
+set_feature(>env, ARM_FEATURE_NEON);
+set_feature(>env, ARM_FEATURE_GENERIC_TIMER);
+
On 3/29/2022 7:03 AM, Fam Zheng wrote:
> On 2021-08-06 14:43, Steve Sistare wrote:
>> Preserve vfio INTX state across cpr restart. Preserve VFIOINTx fields as
>> follows:
>> pin : Recover this from the vfio config in kernel space
>> interrupt : Preserve its eventfd descriptor across exec.
>>
On Sat, 9 Apr 2022 at 01:18, Richard Henderson
wrote:
>
> Check for and defer any pending virtual SError.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 1 +
> target/arm/a32.decode | 16 +-
> target/arm/t32.decode | 18 +++
>
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Virtual SError exceptions are raised by setting HCR_EL2.VSE,
> and are routed to EL1 just like other virtual exceptions.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 2 ++
> target/arm/internals.h | 8
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Enable writes to the TERR and TEA bits when RAS is enabled.
> These bits are otherwise RES0.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Peter Maydell
On Sat, 9 Apr 2022 at 01:14, Richard Henderson
wrote:
>
> Add only the system registers required to implement zero error
> records. This means we need to save state for ERRSELR, but all
> values are out of range, so none of the indexed error record
> registers need be implemented.
>
> Add the
On Mon, Apr 11, 2022 at 04:00:57PM +0100, Stefan Hajnoczi wrote:
> The GLib documentation says "a NULL-terminated array of GOptionEntrys"
> so we'd better make sure there is a terminator that lets
> g_option_context_add_main_entries() know when the end of the array has
> been reached.
>
>
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Instead of starting with cortex-a15 and adding v8 features to
> a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
> This fixes the long-standing to-do where we only enabled v8
> features for user-only.
>
> Signed-off-by:
> -Original Message-
> From: Anton Johansson
> Sent: Wednesday, February 9, 2022 11:03 AM
> To: qemu-devel@nongnu.org
> Cc: a...@rev.ng; Taylor Simpson ; Brian Cain
> ; Michael Lambert ;
> bab...@rev.ng; ni...@rev.ng; richard.hender...@linaro.org
> Subject: [PATCH v8 10/12]
On Thu, Apr 07, 2022 at 04:05:36PM +, Sean Christopherson wrote:
> Hmm, shmem_writepage() already handles SHM_F_INACCESSIBLE by rejecting the
> swap, so
> maybe it's just the page migration path that needs to be updated?
My early version prevented migration with -ENOTSUPP for
Richard Henderson writes:
> On 4/9/22 20:58, jianchunfu wrote:
>> Handling potential memory allocation failures in dirtyrate.
>> Signed-off-by: jianchunfu
>> ---
>> migration/dirtyrate.c | 8
>> 1 file changed, 8 insertions(+)
>> diff --git a/migration/dirtyrate.c
On Fri, Apr 08, 2022 at 09:02:54PM +0800, Chao Peng wrote:
> > I think the correct approach is to not do the locking automatically for
> > SHM_F_INACCESSIBLE,
> > and instead require userspace to do shmctl(.., SHM_LOCK, ...) if userspace
> > knows the
> > consumers don't support migrate/swap.
On Thu, Mar 10, 2022 at 10:08:59PM +0800, Chao Peng wrote:
> From: "Kirill A. Shutemov"
>
> Introduce a new memfd_create() flag indicating the content of the
> created memfd is inaccessible from userspace through ordinary MMU
> access (e.g., read/write/mmap). However, the file content can be
>
On Thu, Mar 10, 2022 at 10:09:01PM +0800, Chao Peng wrote:
> diff --git a/mm/shmem.c b/mm/shmem.c
> index 9b31a7056009..7b43e274c9a2 100644
> --- a/mm/shmem.c
> +++ b/mm/shmem.c
> @@ -903,6 +903,28 @@ static struct folio *shmem_get_partial_folio(struct
> inode *inode, pgoff_t index)
>
Itaru Kitayama writes:
> Good point; however per the SBSA specification, DEN0029F, there's the
> PE architecture requirement at
> each level from 1 to 7, so now I am wondering whether supporting
> cortex-a57 and a72 are good enough to
> set up a fully SBSA level 7 compliant "board" in QMEU.
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