On Sat, May 7, 2022 at 2:46 PM Paolo Bonzini wrote:
>
> On 5/7/22 07:05, Jason Wang wrote:
> >> If it was generated by something in the tree, it should not be committed
> >> to git. Doesn't look like it is.
> > Andrew may know more.
> >
> > I remember it was generated by libbpf.
>
> What is the s
On 5/7/22 07:05, Jason Wang wrote:
If it was generated by something in the tree, it should not be committed
to git. Doesn't look like it is.
Andrew may know more.
I remember it was generated by libbpf.
What is the source?
Paolo
Use the new support for string option parsing.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 14 --
meson.build | 27 ---
meson_options.txt | 4
scripts/meson-buildoptions.s
The following changes since commit 13220a46e27ef95159651acd5e408b6aac9dbf3e:
Merge tag 'vfio-updates-20220506.1' of
https://gitlab.com/alex.williamson/qemu into staging (2022-05-06 16:18:14 -0500)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
-machine graphics=off is the usual way to tell the firmware or the OS that the
user wants a serial console. The pseries machine however does not support
this, and never adds the stdout-path node to the device tree if a VGA device
is provided. This is in addition to the other magic behavior of VGA
On 5/6/22 00:10, Daniel Henrique Barboza wrote:
Removing the negation seems to do what you want:
- if (!spapr->want_stdout_path && stdout_path) {
+ if (spapr->want_stdout_path && stdout_path) {
Yes, of course. Sorry!
Paolo
On Sat, May 7, 2022 at 10:03 AM Zhang, Chen wrote:
>
>
>
> > -Original Message-
> > From: Zhang, Chen
> > Sent: Wednesday, April 27, 2022 5:26 PM
> > To: Jason Wang ; Paolo Bonzini
> >
> > Cc: Li Zhijian ; qemu-dev > de...@nongnu.org>; Like Xu
> > Subject: RE: [PATCH V2 1/4] softmmu/run
On Fri, May 6, 2022 at 8:26 PM Markus Armbruster wrote:
>
> ebpf/rss.bpf.skeleton.h contains
>
> /* THIS FILE IS AUTOGENERATED! */
>
> If it was generated by something in the tree, it should not be committed
> to git. Doesn't look like it is.
Andrew may know more.
I remember it was generate
When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
setting up the hello packet (just as with "-incoming". On the latest version
of libusbredir, usbredirparser_unserialize() will return error if the parser
is not "pristine."
Signed-off-by: Joelle van Dyne
---
hw/usb/redirec
On 5/6/22 15:46, Alex Williamson wrote:
Switching to gitlab for pull requests to take advantage of the CI.
Sorry for the delay in some of these. Thanks,
Alex
The following changes since commit 31abf61c4929a91275fe32f1fafe6e6b3e840b2a:
Merge tag 'pull-ppc-20220505' of https://gitlab.com/dan
virtio_queue_host_notifier_read() tends to read pending event
left behind on ioeventfd in the vhost_net_stop() path, and
attempts to handle outstanding kicks from userspace vq handler.
However, in the ctrl_vq handler, virtio_net_handle_mq() has a
recursive call into virtio_net_set_status(), which m
The vhost_vdpa_one_time_request() branch in
vhost_vdpa_set_backend_cap() incorrectly sends down
ioctls on vhost_dev with non-zero index. This may
end up with multiple VHOST_SET_BACKEND_FEATURES
ioctl calls sent down on the vhost-vdpa fd that is
shared between all these vhost_dev's.
To fix it, send
vhost_net_start() missed a corresponding stop_one() upon error from
vhost_set_vring_enable(). While at it, make the error handling for
err_start more robust. No real issue was found due to this though.
Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
---
hw/net/vhost_net.c | 4 +++-
1 file change
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >=
dev->vq_index && idx < dev->vq_index + dev->nvqs' failed.
0 0x7f8ce3ff3387 in
... such that no memory leaks on dangling net clients in case of
error.
Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 1e9fe47..df1e69e 100644
--- a/net/vhost-vd
Hi,
This patch series attempt to fix a few issues in vhost-vdpa multiqueue
functionality.
Patch #1 and #2 are the formal submission for RFC patch as in:
https://lore.kernel.org/qemu-devel/c3e931ee-1a1b-9c2f-2f59-cb4395c23...@oracle.com/
Patch #3 through #6 are obviously small bug fixes. Please
The name vhost_vdpa_one_time_request() was confusing. No
matter whatever it returns, its typical occurrence had
always been at requests that only need to be applied once.
And the name didn't suggest what it actually checks for.
Change it to vhost_vdpa_first_dev() with polarity flipped
for better re
When the control virtqueue feature is absent or not negotiated,
vhost_net_start() still tries to set up vhost_dev and install
vhost notifiers for the control virtqueue, which results in
erroneous ioctl calls with incorrect queue index sending down
to driver. Do that only when needed.
Fixes: 22288f
Implement zero copy send on nocomp_send_write(), by making use of QIOChannel
writev + flags & flush interface.
Change multifd_send_sync_main() so flush_zero_copy() can be called
after each iteration in order to make sure all dirty pages are sent before
a new iteration is started. It will also flus
> -Original Message-
> From: Zhang, Chen
> Sent: Wednesday, April 27, 2022 5:26 PM
> To: Jason Wang ; Paolo Bonzini
>
> Cc: Li Zhijian ; qemu-dev de...@nongnu.org>; Like Xu
> Subject: RE: [PATCH V2 1/4] softmmu/runstate.c: add RunStateTransition
> support form COLO to PRELAUNCH
>
>
>
Since d48c3a0445 ("multifd: Use a single writev on the send side"),
sending the header packet and the memory pages happens in the same
writev, which can potentially make the migration faster.
Using channel-socket as example, this works well with the default copying
mechanism of sendmsg(), but with
A lot of places check parameters.tls_creds in order to evaluate if TLS is
in use, and sometimes call migrate_get_current() just for that test.
Add new helper function migrate_use_tls() in order to simplify testing
for TLS usage.
Signed-off-by: Leonardo Bras
Reviewed-by: Juan Quintela
Reviewed-b
For CONFIG_LINUX, implement the new zero copy flag and the optional callback
io_flush on QIOChannelSocket, but enables it only when MSG_ZEROCOPY
feature is available in the host kernel, which is checked on
qio_channel_socket_connect_sync()
qio_channel_socket_flush() was implemented by counting how
Add property that allows zero-copy migration of memory pages
on the sending side, and also includes a helper function
migrate_use_zero_copy_send() to check if it's enabled.
No code is introduced to actually do the migration, but it allow
future implementations to enable/disable this feature.
On n
Even though multifd_send_sync_main() currently emits error_reports, it's
callers don't really check it before continuing.
Change multifd_send_sync_main() to return -1 on error and 0 on success.
Also change all it's callers to make use of this change and possibly fail
earlier.
(This change is impo
Add flags to io_writev and introduce io_flush as optional callback to
QIOChannelClass, allowing the implementation of zero copy writes by
subclasses.
How to use them:
- Write data using qio_channel_writev*(...,QIO_CHANNEL_WRITE_FLAG_ZERO_COPY),
- Wait write completion with qio_channel_flush().
No
This patch series intends to enable MSG_ZEROCOPY in QIOChannel, and make
use of it for multifd migration performance improvement, by reducing cpu
usage.
Patch #1 creates new callbacks for QIOChannel, allowing the implementation
of zero copy writing.
Patch #2 implements io_writev flags and io_flus
On 5/2/22 06:43, Mark Cave-Ayland wrote:
On 30/04/2022 00:31, Murilo Opsfelder Araujo wrote:
When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:
/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158):
undefined reference to `hmp_info_via'
clang-13:
31abf61c4929a91275fe32f1fafe6e6b3e840b2a:
Merge tag 'pull-ppc-20220505' of https://gitlab.com/danielhb/qemu into
staging (2022-05-05 13:52:22 -0500)
are available in the Git repository at:
https://github.com/OSLL/qemu-xtensa.git tags/20220506-xtensa-1
for you to fetch cha
://github.com/OSLL/qemu-xtensa.git tags/20220506-xtensa
for you to fetch changes up to 5e1d80a3fc16d5dbe7d677af6ba4df94d68c75d2:
tests/tcg/xtensa: fix vectors and checks in timer test (2022-04-27 10:15:23
-0700)
target/xtensa
VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.
Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction ex
From: Yi Liu
Rename VFIOGuestIOMMU iommu field into iommu_mr. Then it becomes clearer
it is an IOMMU memory region.
no functional change intended
Signed-off-by: Yi Liu
Link: https://lore.kernel.org/r/20220502094223.36384-4-yi.l@intel.com
Signed-off-by: Alex Williamson
---
hw/vfio/common.
From: Eric Auger
Using a VFIODevice handle local variable to improve the code readability.
no functional change intended
Signed-off-by: Eric Auger
Signed-off-by: Yi Liu
Link: https://lore.kernel.org/r/20220502094223.36384-3-yi.l@intel.com
Signed-off-by: Alex Williamson
---
hw/vfio/pci.c
From: Eric Auger
The CRB command buffer currently is a RAM MemoryRegion and given
its base address alignment, it causes an error report on
vfio_listener_region_add(). This region could have been a RAM device
region, easing the detection of such safe situation but this option
was not well received
From: Xiang Chen
It uses [offset, offset + size - 1] to indicate that the length of range is
size in most places in vfio trace code (such as
trace_vfio_region_region_mmap()) execpt trace_vfio_region_sparse_mmap_entry().
So change it for trace_vfio_region_sparse_mmap_entry(), but if size is zero,
From: Eric Auger
In a subsequent patch, VFIO will need to recognize if
a memory region owner is a TPM CRB device. Hence VFIO
needs to use TPM_IS_CRB() even if CONFIG_TPM is unset. So
let's add a stub function.
Signed-off-by: Eric Auger
Suggested-by: Cornelia Huck
Reviewed-by: Stefan Berger
Li
From: Longpeng(Mike)
Use vfio_msi_disable_common to simplify the error handling
in vfio_msi_enable.
Signed-off-by: Longpeng(Mike)
Link: https://lore.kernel.org/r/20220326060226.1892-4-longpe...@huawei.com
Signed-off-by: Alex Williamson
---
hw/vfio/pci.c | 16 ++--
1 file changed
From: Eric Auger
"%m" format specifier is not interpreted by the trace infrastructure
and thus "%m" is output instead of the actual errno string. Fix it by
outputting strerror(errno).
Signed-off-by: Eric Auger
Signed-off-by: Yi Liu
Link: https://lore.kernel.org/r/20220502094223.36384-2-yi.l...
From: Longpeng(Mike)
In migration resume phase, all unmasked msix vectors need to be
setup when loading the VF state. However, the setup operation would
take longer if the VM has more VFs and each VF has more unmasked
vectors.
The hot spot is kvm_irqchip_commit_routes, it'll scan and update
all
From: Longpeng(Mike)
Move re-enabling INTX out, and the callers should decide to
re-enable it or not.
Signed-off-by: Longpeng(Mike)
Link: https://lore.kernel.org/r/20220326060226.1892-3-longpe...@huawei.com
Signed-off-by: Alex Williamson
---
hw/vfio/pci.c | 17 +++--
1 file chan
From: Longpeng(Mike)
Commit ecebe53fe993 ("vfio: Avoid disabling and enabling vectors
repeatedly in VFIO migration") avoids inefficiently disabling and
enabling vectors repeatedly and lets the unmasked vectors be enabled
one by one.
But we want to batch multiple routes and defer the commit, and
From: Longpeng(Mike)
It's unnecessary to test against the specific return value of
VFIO_DEVICE_SET_IRQS, since any positive return is an error
indicating the number of vectors we should retry with.
Signed-off-by: Longpeng(Mike)
Link: https://lore.kernel.org/r/20220326060226.1892-2-longpe...@hua
Switching to gitlab for pull requests to take advantage of the CI.
Sorry for the delay in some of these. Thanks,
Alex
The following changes since commit 31abf61c4929a91275fe32f1fafe6e6b3e840b2a:
Merge tag 'pull-ppc-20220505' of https://gitlab.com/danielhb/qemu into
staging (2022-05-05 13:52:
On Fri, May 6, 2022 at 4:00 AM Peter Maydell wrote:
>
> On Fri, 6 May 2022 at 09:18, Daniel P. Berrangé wrote:
> >
> > On Fri, May 06, 2022 at 06:34:47AM +1000, Alistair Francis wrote:
> > > Even if we didn't worry about backwards compatibility the current virt
> > > machine would still be what m
/20220506-xtensa
for you to fetch changes up to 5e1d80a3fc16d5dbe7d677af6ba4df94d68c75d2:
tests/tcg/xtensa: fix vectors and checks in timer test (2022-04-27 10:15:23
-0700)
target/xtensa updates for v7.1:
- expand test coverage to
Adding fby35 to the list of Aspeed boards in the QEMU documentation, per
Cedric's request[1]. This is intended to be merged with the patch adding the
machine definition[2].
[1]
https://lore.kernel.org/qemu-devel/97674ac7-17c5-06cf-6bd0-0e7acc37a...@kaod.org/
[2] https://lore.kernel.org/qemu-devel
Add fby35 to the list of Aspeed boards.
Signed-off-by: Peter Delevoryas
---
docs/system/arm/aspeed.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 60ed94f187..fa98549c11 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/syste
Hello Paolo, folks, I gave it a try (on top of the f9fc8932) and it's better
than the f9fc8932, better than the previous patch by Stefan, but still I'm not
reaching the performance of d7482ffe97 (before the f9fc8932 commit):
f9f| 0.0 | -2.8 | 0.6
stefan | -3.1 | -1.2 | -2.2
paolo | 5.3 |
On 5/5/22 13:39, Peter Maydell wrote:
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst
Enable the n1 for virt and sbsa board use.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed,
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/syste
On 5/5/22 13:39, Peter Maydell wrote:
Factor out the part of combine_cacheattrs() that is specific to
handling HCR_EL2.FWB == 0. This is the part where we combine the
memory type and cacheability attributes.
The "force Outer Shareable for Device or Normal Inner-NC Outer-NC"
logic remains in com
On 5/5/22 13:39, Peter Maydell wrote:
Implement the handling of FEAT_S2FWB; the meat of this is in the new
combined_attrs_fwb() function which combines S1 and S2 attributes
when HCR_EL2.FWB is set.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 5 +++
target/arm/helper.c | 84 +++
Enable the a76 for virt and sbsa board use.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed,
On 5/5/22 13:39, Peter Maydell wrote:
In the original Arm v8 two-stage translation, both stage 1 and stage
2 specify memory attributes (memory type, cacheability,
shareability); these are then combined to produce the overall memory
attributes for the whole stage 1+2 access. In QEMU we implement
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 37c5e42bc0.
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst; clear CSV2_FRAC; use
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
in
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/a
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
2 files
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Retain m-profile check; improve comments.
---
target/arm/helper.h| 1 +
target/arm/a32.decode | 16 --
target/arm/t32.decode | 18
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 100 +---
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Honor EAE for reporting VSERR to aa32.
---
target/arm/cpu.h | 2 ++
target/arm/internals.h | 8 +
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Hende
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 +
target/arm/cpu64.c | 50 +-
target/arm/cpu_tcg.c | 114 +++
Add only the system registers required to implement zero error
records. This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.
Add the EL2 registers required for injecting virtual SError.
Reviewed-by: Pe
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 4
1 file changed, 4 insertions(+)
diff -
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Rely on EL3-no-EL2 squashing during registration.
---
target/arm/helper.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/hel
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.
This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are
Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Create impdef sysr
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: New patch.
---
target/arm/i
Changes for v6:
* Expand the commit message for "Drop EL3 no EL2 fallbacks" (pmm)
All patches are reviewed.
r~
Richard Henderson (24):
target/arm: Handle cpreg registration for missing EL
target/arm: Drop EL3 no EL2 fallbacks
target/arm: Merge zcr reginfo
target/arm: Adjust definitio
More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.
Per rule RJFFP, mark the 4 aarch32 hypervisor access re
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 55 ++---
1 file change
On 5/6/22 09:49, Peter Maydell wrote:
On Fri, 6 May 2022 at 15:41, Thomas Huth wrote:
* Remove redundant/obsolete x86 and arm disassemblers (Capstone is better)
* Limit some Xen-related code to builds where Xen is really available
Thomas Huth writes:
> STEXI and ETEXI is not used anymore since we switched to Sphinx.
> Replace them in the example with SRST and ERST, too.
>
> Signed-off-by: Thomas Huth
> ---
> docs/devel/writing-monitor-commands.rst | 11 ---
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> di
> On May 5, 2022, at 11:30 PM, Cédric Le Goater wrote:
>
> On 5/4/22 18:34, Peter Delevoryas wrote:
>>> On May 4, 2022, at 12:39 AM, Cédric Le Goater wrote:
>>>
>>> On 5/4/22 00:59, Peter Delevoryas wrote:
Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace
i2
On Fri, May 06, 2022 at 11:53:22AM +0400, Marc-André Lureau wrote:
> Hi
>
> On Fri, May 6, 2022 at 1:46 AM Dongwon Kim wrote:
>
> > It only needs to update the scanouts containing the rect area
> > coming with the resource-flush request from the guest.
> >
> >
> Cc: Gerd Hoffmann
> > Cc: Vivek
On Fri, May 06, 2022 at 03:42:15PM +0200, Hanna Reitz wrote:
> When stdout is not a terminal, the buffer may not be flushed at each end
> of line, so we should flush after each test is done. This is especially
> apparent when run by check-block, in two ways:
>
> First, when running make check-blo
On Fri, May 06, 2022 at 05:34:21PM +0100, Daniel P. Berrangé wrote:
> On Tue, May 03, 2022 at 04:33:48PM -0700, Dongwon Kim wrote:
> > I saw windows, especially, third and fourth ones are 1/4 size of
> > the first when detached regardless of resolutions.
> >
> > And the position is also pretty ran
Hello Jonathan,
On 5/6/22 16:07, Jonathan Cameron wrote:
On Thu, 31 Mar 2022 18:57:33 +0200
Klaus Jensen wrote:
From: Klaus Jensen
Hi all,
This RFC series adds I2C "slave mode" support for the Aspeed I2C
controller as well as the necessary infrastructure in the i2c core to
support this.
B
On Tue, May 03, 2022 at 04:33:48PM -0700, Dongwon Kim wrote:
> I saw windows, especially, third and fourth ones are 1/4 size of
> the first when detached regardless of resolutions.
>
> And the position is also pretty random and detached windows are usually
> placed somewhere on the previous window
On Fri, 6 May 2022 at 17:21, Peter Maydell wrote:
>
> Make the GICv3 set its number of bits of physical priority from the
> implementation-specific value provided in the CPU state struct, in
> the same way we already do for virtual priority bits. Because this
> would be a migration compatibility
assert(dbs->acb) is meant to check the return value of io_func per
documented in commit 6bee44ea34 ("dma: the passed io_func does not
return NULL"). However, there is a chance that after calling
aio_context_release(dbs->ctx); the dma_blk_cb function is called before
the assertion and dbs->acb is se
On Fri, 6 May 2022 at 17:10, Paolo Bonzini wrote:
>
> On 5/6/22 17:47, Peter Maydell wrote:
> >>if (!vga_model && !default_vga) {
> >>vga_interface_type = VGA_DEVICE;
> >> + vga_interface_created = true;
> >>}
> >>if (!has_defaults || machine_class->no_
We previously open-coded the expression for the number of virtual APR
registers and the assertion that it was not going to cause us to
overflow the cs->ich_apr[] array. Factor this out into a new
ich_num_aprs() function, for consistency with the icc_num_aprs()
function we just added for the physic
Make the GICv3 set its number of bits of physical priority from the
implementation-specific value provided in the CPU state struct, in
the same way we already do for virtual priority bits. Because this
would be a migration compatibility break, we provide a property
force-8-bit-prio which is enable
The GIC_MIN_BPR constant defines the minimum BPR value that the TCG
emulated GICv3 supports. We're currently using this also as the
value we reset the KVM GICv3 ICC_BPR registers to, but this is only
right by accident.
We want to make the emulated GICv3 use a configurable number of
priority bits,
The GICv3 code has always supported a configurable number of virtual
priority and preemption bits, but our implementation currently
hardcodes the number of physical priority bits at 8. This is not
what most hardware implementations provide; for instance the
Cortex-A53 provides only 5 bits of physi
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was prev
This patchset fills in an odd inconsistency in our GICv3 emulation
that I noticed while I was doing the GICv4 work. At the moment we
allow the CPU to specify the number of bits of virtual priority
(via the ARMCPU::gic_vpribits field), but we always use 8 bits of
physical priority, even though to my
On 5/6/22 17:47, Peter Maydell wrote:
if (!vga_model && !default_vga) {
vga_interface_type = VGA_DEVICE;
+ vga_interface_created = true;
}
if (!has_defaults || machine_class->no_serial) {
default_serial = 0;
Can you explain why that's right? q
On Fri, 6 May 2022 at 16:43, Paolo Bonzini wrote:
>
> On 5/6/22 16:48, Peter Maydell wrote:
> >> I'm just in progress of preparing a pull request with misc patches, I can
> >> also throw it in there if nobody minds.
> > Paolo mentioned on IRC yesterday that there was some detail he thought
> > it
On 5/6/22 16:48, Peter Maydell wrote:
I'm just in progress of preparing a pull request with misc patches, I can
also throw it in there if nobody minds.
Paolo mentioned on IRC yesterday that there was some detail he thought
it wasn't handling right with VGA_DEVICE, but I didn't really understand
Storage key controlled protection is currently not honored when
emulating instructions.
If available, enable key protection for the MEM_OP ioctl, thereby
enabling it for the s390_cpu_virt_mem_* functions, when using kvm.
As a result, the emulation of the following instructions honors storage
keys:
Since a full update of the linux headers pulls in changes in vfio.h that
break compilation, pull in only the required changes for storage key
support.
Signed-off-by: Janis Schoetterl-Glausch
---
linux-headers/linux/kvm.h | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --g
Make use of the storage key support of the MEMOP ioctl, if available,
in order to support storage key checking during emulation.
I did not update all the headers, since that broke the build,
not sure what the best way of dealing with that is.
Janis Schoetterl-Glausch (2):
Pull in MEMOP changes
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