On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvbf16ger2: VSX Vector bfloat16 GER (rank-2 update)
xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Negative accumulate
xvbf1
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update)
pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
+static inline float32 float32_neg(float32 a)
+{
+if (((a & 0x7f80) == 0x7f80) && (a & 0x007f)) {
+return a;
+} else {
+return float32_chs(a);
+}
+}
This is wrong -- even NaNs get their signs changed.
N
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Neg
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
return true;
+
+}
+static bool do_ger_XX3(DisasContext *ctx, arg_XX3 *a,
Watch the whitespace.
+{
+arg_MMIRR_XX3 m;
+m.xa = a->xa;
+m.xb = a->xb;
+m.xt = a->xt;
+m.pmsk = 0xFF;
+m.ymsk = 0xF;
+m.xmsk = 0xF;
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 10c6d7ae43..348a898950 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -238,6 +238,7 @@ typedef union _ppc_vsr_t {
typedef ppc_vsr_t ppc_avr_t;
typedef ppc_vsr_t ppc_fprp_t;
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xxmfacc: VSX Move From Accumulator
xxmtacc: VSX Move To Accumulator
xxsetaccz: VSX Set Accumulator to Zero
The PowerISA 3.1 mentions that for the curren
On 5/4/22 04:25, Mark Cave-Ayland wrote:
There is no need for a separate function to set the machine class properties
separately from the others.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/machine.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
R
On 5/4/22 04:26, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/machine.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/machine.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/4/22 04:25, Mark Cave-Ayland wrote:
This file is now just a simple wrapper that includes hppa_hardware.h so remove
the file completely, and update its single user in machine.c to include
hppa_hardware.h directly.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Now that the board configuration is in one place, the define is only needed when
wiring up the board in machine.c.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.h | 2 --
hw/hppa/machine.c | 3 +++
2 files changed, 3 ins
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Now that there are no longer any devices in hw/hppa the trace-events file is
empty and can be removed.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/trace-events | 1 -
meson.build | 1 -
2 files changed, 2 deletions(-)
On 5/4/22 04:25, Mark Cave-Ayland wrote:
The functions and definitions in this file are not used anywhere within the
generic hppa machine.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.h | 6
hw/hppa/meson.build | 2 +-
hw/hppa/pci.c| 65 --
On 5/4/22 04:25, Mark Cave-Ayland wrote:
The memory region only has one user which is for ensuring accesses to the ISA
bus memory do not fault.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.h | 1 -
hw/hppa/machine.c | 23 +++
hw/hppa/pci.c
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Move the LASI device implementation from hw/hppa to hw/misc so that it is
located with all the other miscellaneous devices.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
MAINTAINERS | 2 ++
hw/hppa/Kconfig
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Instead of generating the offset based upon the physical address of the
register, add constants for each of the device registers to lasi.h and
update lasi.c to use them.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c | 28 ++
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.h | 3 ---
hw/hppa/lasi.h | 4
hw/hppa/machine.c | 2 ++
hw/hppa/pci.c | 3 +++
4 files changed, 9 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henders
On 5/4/22 04:25, Mark Cave-Ayland wrote:
This is to allow us to decouple the LASI device from the board logic. If it is
decided later that this value needs to be configurable then it can easily be
converted to a qdev property.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Move the simplified lasi_initfn() back to machine.c whilst also renaming it
back to its original lasi_init() name.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.h | 2 --
hw/hppa/lasi.c | 10 --
hw/hppa/machi
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Now that all of the LASI devices are mapped by the board, this parameter is no
longer required.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.h | 2 +-
hw/hppa/lasi.c | 2 +-
hw/hppa/machine.c | 2 +-
3 files change
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c| 5 -
hw/hppa/machine.c | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c| 8
hw/hppa/machine.c | 7 +++
2 files changed, 7 insertions(+), 8 deletions(-)
In that it is code movement,
Reviewed-by: Richard Henderson
+if (seri
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c| 6 --
hw/hppa/machine.c | 6 ++
2 files changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c| 7 ---
hw/hppa/machine.c | 5 +
2 files changed, 5 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/hppa_sys.h | 3 ++-
hw/hppa/lasi.c | 4 ++--
hw/hppa/machine.c | 3 ++-
3 files changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/4/22 04:25, Mark Cave-Ayland wrote:
The existing code checks for serial_hd(1) but sets the LASI serial port chardev
to serial_hd(0). Use serial_hd(1) for the LASI serial port and also set the
serial port endian to DEVICE_BIG_ENDIAN (which also matches the endian of the
existing serial port).
On 5/4/22 04:25, Mark Cave-Ayland wrote:
The existing code checks for serial_hd(1) but sets the LASI serial port chardev
to serial_hd(0). Use serial_hd(1) for the LASI serial port and also set the
serial port endian to DEVICE_BIG_ENDIAN (which also matches the endian of the
existing serial port).
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/3/22 17:51, Ilya Leoshkevich wrote:
Commit 31330e6cecfd ("linux-user/s390x: Implement setup_sigtramp")
removed an unused field from rt_sigframe, disturbing offsets of other
fields and breaking unwinding from signal handlers (e.g. libgcc's
s390_fallback_frame() relies on this struct having a
On 04.05.22 00:51, Ilya Leoshkevich wrote:
> Commit 31330e6cecfd ("linux-user/s390x: Implement setup_sigtramp")
> removed an unused field from rt_sigframe, disturbing offsets of other
> fields and breaking unwinding from signal handlers (e.g. libgcc's
> s390_fallback_frame() relies on this struct h
On 4/29/22 05:07, Xiaojuan Yang wrote:
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c| 66 +++--
include/hw/loongarch/virt.h | 9 +
target/loongarch/cpu.h | 2 ++
3 files changed, 75 insertions(+), 2 deletion
On 4/29/22 05:07, Xiaojuan Yang wrote:
+/*
+ * Shift bits and filed mask
+ */
+#define TOY_MON_MASK 0x3f
+#define TOY_DAY_MASK 0x1f
+#define TOY_HOUR_MASK 0x1f
+#define TOY_MIN_MASK 0x3f
+#define TOY_SEC_MASK 0x3f
+#define TOY_MSEC_MASK 0xf
+
+#define TOY_MON_SHIFT 26
+#define TOY_DAY_
The attribute is always being set to TYPE_PNV_PHB_ROOT_PORT.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4_pec.c | 4 +---
include/hw/pci-host/pnv_phb4.h | 1 -
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_p
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb3.c | 59 +-
i
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is that
pnv-phb4-root-port has the pnv_phb4_root_port_
Add a simple helper to avoid hardcoding strcmp() comparisons all around
pnv_phb.c.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 40 +++-
1 file changed, 31 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pn
On Fri, May 06, 2022 at 10:57:54PM -0300, Leonardo Bras wrote:
> diff --git a/io/channel-socket.c b/io/channel-socket.c
> index 05c425abb8..f03a068f25 100644
> --- a/io/channel-socket.c
> +++ b/io/channel-socket.c
> @@ -25,9 +25,18 @@
> #include "io/channel-watch.h"
> #include "trace.h"
> #inclu
Given that powernv9 and powernv10 uses the same pnv-phb backend, the logic to
allow user created pnv-phbs for powernv10 is already in place. This
patch just flips the switch.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 2 +-
hw/ppc/pnv.c | 2 ++
2 files changed,
This patch reintroduces the powernv8 bits of the code what was removed
in commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices",
using the pnv-phb device instead of the now late pnv-phb4 device,
allowing us to enable user creatable pnv-phb devices for the powernv9
machine.
Signed-off
The unified pnv-phb-root-port can be used instead. THe
pnv-phb4-root-port device isn't exposed to the user in any official QEMU
release so there's no ABI breakage in removing it.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 100 -
hw
The PnvPHB device is able to replace the PnvPHB4 device in all
instances, while also being usable by the PHB3 logic.
The PnvPHB4 device wasn't user creatable in any official QEMU release,
so we can remove it without breaking ABI.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c |
The unified PnvPHB model is able to replace PnvPHB3 in all PHB3 related
code. Let's do that while also removing the PnvPHB3 device entirely.
The device wasn't user creatable in any QEMU release so there's no ABI
concerns in doing so.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb
This patch reintroduces the powernv8 bits of the code what was removed
in commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices",
using the pnv-phb device instead of the now late pnv-phb3 device,
allowing us to enable user creatable pnv-phb devices for the powernv8
machine.
Signed-off
The 'version' attribute of the PnvPHB was never used. Instead of
removing it, let's make use of it by setting the PHB version the PnvPHB
device is currently running.
This distinction will be used next patch.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 11 +
This device works as a generic pnv-phb that redirects the control flow
to one of the implemented PHB versions (PHB3 and PHB4 at this moment).
The control redirection happens in the instance_init() and realize()
callbacks, where we check which powernv machine we're running and
execute the PnvPHB3 c
Another redundancy between PnvPHB3 and PnvPHB4 that we should take care
before merging all together in an unified model is the regs[] array.
Rename the regs[] array used by the PHB3 code to 'regs3'.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb3.c | 54 +
The last common attribute that has a different meaning/semantic between
PnvPHB3 and PnvPHB4 devices is the 'dma_spaces' QLIST.
Rename the PHB3 version to 'v3_dma_spaces'. The reason why we chose that
instead of 'dma3_spaces' or similar is to avoid any misunderstanding
about this being related to D
This patch adds the pnv_phb.h header with the declarations we're going
to use in this soon to be added device.
It consists of an union between all attributes of PnvPHB3 and PnvPHB4
devices. This will allow for the same PnvPHB device to be used for PHB3
and PHB4 code.
Some struct definitions from
We're going to merge all the existing pnv-phb models into a single
pnv-phb model. Users will be able to add phbs by using the same pnv-phb
device, regardless of which powernv machine is being used, and
internally we'll handle which PHB version the device needs to have.
The unified pnv-phb model ne
Hi,
Since the 7.0.0 release cycle we have a desire to use the powernv
emulation with libvirt. To do that we need to enable user creatable
pnv-phb devices to allow more user customization an to avoid spamming
multiple default devices in the domain XML. In the middle of the
previous cycle we experim
> On May 6, 2022, at 1:44 AM, Markus Armbruster wrote:
>
> Jag Raman writes:
>
>>> On May 5, 2022, at 10:42 AM, Markus Armbruster wrote:
>>>
>>> Jag Raman writes:
>>>
> On May 5, 2022, at 3:44 AM, Markus Armbruster wrote:
>
> Jag Raman writes:
>
>>> On May 4, 2022,
On 4/29/22 05:07, Xiaojuan Yang wrote:
+int ipmap_mask = 0xff << ipmap_offset;
...
+int cpu_mask = 0xff << ipmap_offset;
These two masks are redundant with
+ipnum = ((s->ipmap[ipmap_index] & ipmap_mask) >> ipmap_offset) & 0xf;
...
+cpu = ((s->coremap[cpu_index] & cpu_mask)
On 7. May 2022, at 15:42, Chris Howard wrote:
>
> Hi, I’m writing a simple debugger in assembly code for the Raspberry Pi 3B
> (in aarch64).
>
> I’m using QEMU 7.0.0. Everything is running in EL1. (I have MDE and KDE set
> in MDSCR_EL1).
>
> I’m coming across Unexpected Behaviour when playing
On 2022/05/06 1:13, Richard Henderson wrote:
On 5/4/22 22:12, m...@sfc.wide.ad.jp wrote:
From: Keisuke Iida
The maximum IPA size('inputsize') is constrained by the implemented
PA size that is
specified by ID_AA64MMFR0_EL1.PARange. Please reference Arm
Architecture Reference
Manual for A-pro
From: yilingjin
The throttle_thread_scheduled flag is set to 1 in cpu_throttle_timer_tick()
when throttle_percentage isn't 0, and will reset back to 0 after sleeping
in cpu_throttle_thread(). Given that throttle_timer may tick with a slight
delay,
the throttle_percentage may reset to 0 before sc
Hi, I’m writing a simple debugger in assembly code for the Raspberry Pi 3B (in
aarch64).
I’m using QEMU 7.0.0. Everything is running in EL1. (I have MDE and KDE set in
MDSCR_EL1).
I’m coming across Unexpected Behaviour when playing with single-stepping:
It appears that single-stepping is enabl
On 5/7/22 00:50, Paolo Bonzini wrote:
The following changes since commit 13220a46e27ef95159651acd5e408b6aac9dbf3e:
Merge tag 'vfio-updates-20220506.1' of
https://gitlab.com/alex.williamson/qemu into staging (2022-05-06 16:18:14 -0500)
are available in the Git repository at:
https://gitl
On 5/6/22 11:21, Peter Maydell wrote:
@@ -145,11 +153,8 @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs)
* in the ICH Active Priority Registers.
*/
int i;
-int aprmax = 1 << (cs->vprebits - 5);
-assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
-
-for
On 5/6/22 11:21, Peter Maydell wrote:
This patchset fills in an odd inconsistency in our GICv3 emulation
that I noticed while I was doing the GICv4 work. At the moment we
allow the CPU to specify the number of bits of virtual priority
(via the ARMCPU::gic_vpribits field), but we always use 8 bits
On 5/6/22 08:49, Markus Armbruster wrote:
Markus Armbruster (4):
Clean up header guards that don't match their file name
Clean up ill-advised or unusual header guards
Normalize header guard symbol definition
Clean up decorations and whitespace around header guards
Reviewed-by: Richa
On 5/6/22 17:43, Max Filippov wrote:
Hello,
please pull the following updates for the target/xtensa.
Changes since v1:
- rebase series to the current master
- drop big-endian tests enabling patch (cannot test it because of the
test infrastructure change)
- add cache testing opcodes patch
Th
Peter,
I’ll talk with Shuichiro this coming Monday (here most of us on vacation),
and get back to you.
Itaru.
On Sat, May 7, 2022 at 1:34 Peter Maydell wrote:
> On Fri, 6 May 2022 at 17:21, Peter Maydell
> wrote:
> >
> > Make the GICv3 set its number of bits of physical priority from the
> > i
Support smart AEN on controller side, if the guest side enables this
feature, after injecting smart critical warning, also raise AER.
This can be tested by:
virsh qemu-monitor-command vm '{ "execute": "qom-set", "arguments":
{ "path": "/machine/peripheral/nvme0",
"property": "smart_critical_wa
According to NVM Express v1.4, Section 5.21.1.11 (Asynchronous Event
Configuration), introduce bit 0 ~ bit 5.
Signed-off-by: zhenwei pi
---
include/block/nvme.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 3737351cc8
Hi,
In this series, firstly introduce smart related bits of aen cfg, then
support this in oaes.
Linux guest does not support this currently, I also send a series to
enable smart AEN:
https://lore.kernel.org/lkml/20220507065026.260306-1-pizhen...@bytedance.com/T/#t
Test the two series together, wo
On Sat, May 7, 2022 at 2:58 PM Paolo Bonzini wrote:
>
> On 5/7/22 08:53, Jason Wang wrote:
> > On Sat, May 7, 2022 at 2:46 PM Paolo Bonzini wrote:
> >>
> >> On 5/7/22 07:05, Jason Wang wrote:
> If it was generated by something in the tree, it should not be committed
> to git. Doesn't l
On 5/7/22 08:53, Jason Wang wrote:
On Sat, May 7, 2022 at 2:46 PM Paolo Bonzini wrote:
On 5/7/22 07:05, Jason Wang wrote:
If it was generated by something in the tree, it should not be committed
to git. Doesn't look like it is.
Andrew may know more.
I remember it was generated by libbpf.
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