[PATCH v2 2/7] target/arm: Use FIELD definitions for CPACR, CPTR_ELx

We had a few CPTR_* bits defined, but missed quite a few. Complete all of the fields up to ARMv9.2. Use FIELD_EX64 instead of manual extract32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h| 44 +++- hw/arm/boot.c |

[PATCH v2 4/7] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller

This function is used only once, and will need modification for Streaming SVE mode. Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 --- target/arm/helper.c| 30 +++--- 2 files changed, 11 insertions(+), 30 deletions(-) diff --git

[PATCH v2 5/7] target/arm: Use uint32_t instead of bitmap for sve vq's

The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing

Re: [PATCH 3/3] capstone: Remove the capstone submodule

On 5/16/22 07:58, Thomas Huth wrote: Now that we allow compiling with Capstone v3.05 again, all our supported build hosts should provide at least this version of the disassembler library, so we do not need to ship this as a submodule anymore. Signed-off-by: Thomas Huth --- configure

[PATCH v2 0/7] target/arm: SME prep patches

Changes for v2: * Fixed the errors PMM noticed in patch 2. * Cleanups for SVE vector length selection. * Cleanups for SVE exception el selection. * Add el_is_in_host -- I'm not sure this one will really help, but it's certainly appearing more and more in the pseudocode. r~ Richard

Re: [PATCH 2/3] capstone: Allow version 3.0.5 again

On 5/16/22 07:58, Thomas Huth wrote: According to https://lore.kernel.org/qemu-devel/20200921174118.39352-1-richard.hender...@linaro.org/ there was an issue with Capstone 3 from Ubuntu 18. Now that we removed support for Ubuntu 18.04, that issue should hopefully not bite us anymore.

Re: [PATCH 1/3] tests/vm: Add capstone to the NetBSD and OpenBSD VMs

On 5/16/22 07:58, Thomas Huth wrote: The Capstone library that is shipped with NetBSD and OpenBSD works fine when compiling QEMU, so let's enable this in our build-test VMs to get a little bit more build-test coverage. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson r~

Re: [PATCH 2/3] capstone: Allow version 3.0.5 again

On 5/16/22 12:22, Thomas Huth wrote: So it seems like really only the capstone 3.0.4 from Ubuntu 18.04 is broken, while this compiles fine with the capstone 3.0.5 from Ubuntu 20.04. I think my patches should be ok to apply now that we dropped support for Ubuntu 18.04. Yes, I think so.

Re: [PATCH] hw/riscv: virt: Avoid double FDT platform node

On Fri, May 13, 2022 at 5:12 AM Dylan Reid wrote: > > When starting the virt machine with `-machine virt,aia=aplic-imsic`, > both the imsic and aplic init code will add platform fdt nodes by > calling `platform_bus_add_all_fdt_nodes`. This leads to an error at > startup: > ``` >

Re: [PATCH 2/2] target/riscv: Run extension checks for all CPUs

On Tue, May 17, 2022 at 3:02 PM Weiwei Li wrote: > > > 在 2022/5/17 下午12:11, Alistair Francis 写道: > > From: Alistair Francis > > > > Instead of just running the extension checks for the base CPUs, instead > > run them for all CPUs. > > > > Signed-off-by: Alistair Francis > > --- > >

Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V

On Sat, May 7, 2022 at 6:30 AM Atish Kumar Patra wrote: > > On Fri, May 6, 2022 at 4:00 AM Peter Maydell wrote: > > > > On Fri, 6 May 2022 at 09:18, Daniel P. Berrangé wrote: > > > > > > On Fri, May 06, 2022 at 06:34:47AM +1000, Alistair Francis wrote: > > > > Even if we didn't worry about

Re: [PATCH 2/2] target/riscv: Run extension checks for all CPUs

在 2022/5/17 下午12:11, Alistair Francis 写道: From: Alistair Francis Instead of just running the extension checks for the base CPUs, instead run them for all CPUs. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 161 ++--- 1 file changed, 80

Re: [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default

在 2022/5/17 下午12:16, Alistair Francis 写道: On Tue, May 17, 2022 at 12:21 PM Weiwei Li wrote: - properties for zb* extensions are enabled by default which will make sifive/ibex cpu types implicitly support zb* extensions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---

Re: [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default

On Tue, May 17, 2022 at 12:21 PM Weiwei Li wrote: > > - properties for zb* extensions are enabled by default which will make > sifive/ibex cpu types implicitly support zb* extensions > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/cpu.c | 24

[PATCH 2/2] target/riscv: Run extension checks for all CPUs

From: Alistair Francis Instead of just running the extension checks for the base CPUs, instead run them for all CPUs. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 161 ++--- 1 file changed, 80 insertions(+), 81 deletions(-) diff --git

[PATCH 1/2] target/riscv: Don't expose the CPU properties on names CPUs

From: Alistair Francis There are currently two types of RISC-V CPUs: - Generic CPUs (base or any) that allow complete custimisation - "Named" CPUs that match existing hardware Users can use the base CPUs to custimise the extensions that they want, for example -cpu rv64,v=true. We originally

[PATCH 0/2] target/riscv: Cleanup exposed CPU properties

From: Alistair Francis The RISC-V CPUs have been incorrectly enabling features in the named vendor CPUs that aren't enabled in hardware. This patchset changes this so that named vendor CPUs are not runtime configurable. I was torn for the best approach here. The other idea I had was to disable

Re: [PATCH RESEND 0/2] Resolve some redundant property accessors

On Wed, Mar 2, 2022 at 8:54 AM Bernhard Beschow wrote: > > No changes. Just also CC'ed to qemu-trivial. > > The QOM API already provides appropriate accessors, so reuse them. > > Testing done: > > :$ make check > Ok: 570 > Expected Fail: 0 > Fail: 0 >

Re: QEMU 6.2.0: Segfault while calling address_space_init from emulated device

Ok digging deeper, there was a compiler warning about a missing prototype of get_system_memory but I never thought it would lead to this sort of an issue. The fix now is pretty simple to include the header where get_system_memory is defined.

Re: QEMU 6.2.0: Segfault while calling address_space_init from emulated device

I was able to get it to work with a workaround. After doing some gdb debugging it shows that the system_memory global was being populated before the m2m_scaler device was being initialized. Printing system_meory vs mr (argumet) to the crashing function shows the pointer value to be truncated.

Re: About restoring the state in vhost-vdpa device

在 2022/5/17 04:29, Parav Pandit 写道: From: Eugenio Perez Martin Sent: Monday, May 16, 2022 4:51 AM On Fri, May 13, 2022 at 8:25 PM Parav Pandit wrote: Hi Gautam, Please fix your email client to have right response format. Otherwise, it will be confusing for the rest and us to follow the

Re: [PULL v2 00/86] virtio,pc,pci: fixes,cleanups,features

On 5/16/22 13:49, Michael S. Tsirkin wrote: Changes from pull v1: dropped introspection patches from the pull The following changes since commit 9de5f2b40860c5f8295e73fea9922df6f0b8d89a: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-05-12 10:52:15

[PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default

- properties for zb* extensions are enabled by default which will make sifive/ibex cpu types implicitly support zb* extensions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 24 1 file changed, 24 insertions(+) diff --git

[PATCH v2 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

- setting ext_g will implicitly set ext_i Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..b12f69c584 100644 ---

Re: [PATCH 0/5] target/riscv: Enhanced ISA extension checks

On Fri, May 13, 2022 at 7:46 PM Tsukasa OI wrote: > > Hello, > > This is another patchset for RISC-V ISA extension / feature handling. > > Aside from coding style fix / refactoring patch (PATCH 1 and 5), this > patchset contains two changes: > > > > 1. "G" extension handling > > 1.A. "G"

Re: QEMU 6.2.0: Segfault while calling address_space_init from emulated device

Hi All, I still need help, any help would be greatly appreciated. Turned on address sanitizers (config option --enable-sanitizers). It pointed to a heap overflow in xilinx code. SUMMARY: AddressSanitizer: heap-buffer-overflow ../git/hw/dma/xlnx_csu_dma.c:722 in xlnx_csu_dma_class_init So

Re: [PATCH v2 0/2] hw/riscv: Make CPU config error handling generous

On Sat, May 14, 2022 at 4:29 PM Tsukasa OI wrote: > > c.f. > > > This patchset is functionally equivalent to v1 but fixes commit titles. > > > > > Tsukasa OI (2): > hw/riscv: Make CPU config error handling generous

Re: [PATCH v2 07/74] semihosting: Split out guestfd.c

On 5/16/22 08:14, Peter Maydell wrote: diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index d0c603c54e..db552f1839 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -2,4 +2,5 @@ TARGET_ARCH=aarch64

Re: [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks

On Sun, May 15, 2022 at 12:56 PM Tsukasa OI wrote: > > We should separate "check" and "configure" steps as possible. > This commit separates both steps except vector/Zfinx-related checks. > > Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 31

Re: [PATCH 2/2] target/riscv: disable zb* extensions by default

在 2022/5/17 上午8:54, Alistair Francis 写道: On Tue, May 17, 2022 at 10:33 AM Alistair Francis wrote: On Mon, May 16, 2022 at 1:34 PM Weiwei Li wrote: - enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions Agh, this is a pain. Can you

Re: [PATCH v2 05/74] semihosting: Add target_strlen for softmmu-uaccess.h

On 5/16/22 08:11, Peter Maydell wrote: +chunk = -(addr | TARGET_PAGE_MASK); 'chunk' is unsigned but we're assigning it a negative number here... I assume this is doing some clever bit-twiddling trick but it isn't very obvious. Number of bytes left in page -- I'll rename the variable.

Re: [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

在 2022/5/17 上午8:23, Alistair Francis 写道: On Mon, May 16, 2022 at 1:36 PM Weiwei Li wrote: - setting ext_g will implicitly set ext_i Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- slirp | 2 +- target/riscv/cpu.c | 23 --- 2 files changed,

Re: [PATCH 2/2] target/riscv: disable zb* extensions by default

On Tue, May 17, 2022 at 10:33 AM Alistair Francis wrote: > > On Mon, May 16, 2022 at 1:34 PM Weiwei Li wrote: > > > > - enable zb* extensions by default will make cpu types(such as sifive-u34) > > implicitly support zb* extensions > > Agh, this is a pain. > > Can you enable these by default

Re: [PATCH v2 4/5] target/riscv: FP extension requirements

On Sun, May 15, 2022 at 12:56 PM Tsukasa OI wrote: > > QEMU allowed inconsistent configurations that made floating point > arithmetic effectively unusable. > > This commit adds certain checks for consistent FP arithmetic: > > - F requires Zicsr > - Zfinx requires Zicsr > - Zfh/Zfhmin

Re: [PATCH v2 3/5] target/riscv: Change "G" expansion

On Sun, May 15, 2022 at 12:56 PM Tsukasa OI wrote: > > On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei". > Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to > be (virtually) enabled as well, it should be safe to change its expansion. > >

Re: [PATCH 2/5] target/riscv: Disable "G" by default

On Fri, May 13, 2022 at 7:46 PM Tsukasa OI wrote: > > Because "G" virtual extension expands to "IMAFD", we cannot separately > disable extensions like "F" or "D" without disabling "G". Because all > "IMAFD" are enabled by default, it's harmless to disable "G" by default. > > Signed-off-by:

Re: [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion

On Sun, May 15, 2022 at 12:56 PM Tsukasa OI wrote: > > Because ext_? members are boolean variables, operator `&&' should be > used instead of `&'. > > Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2

Re: [PATCH v2 2/2] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

On Sat, May 14, 2022 at 4:30 PM Tsukasa OI wrote: > > If specified CPU configuration is not valid, not just it prints error > message, it aborts and generates core dumps (depends on the operating > system). This kind of error handling should be used only when a serious > runtime error occurs. >

Re: [PATCH v2 1/2] hw/riscv: Make CPU config error handling generous (virt/spike)

On Sat, May 14, 2022 at 4:29 PM Tsukasa OI wrote: > > If specified CPU configuration is not valid, not just it prints error > message, it aborts and generates core dumps (depends on the operating > system). This kind of error handling should be used only when a serious > runtime error occurs. >

Re: [PATCH 2/2] target/riscv: disable zb* extensions by default

On Mon, May 16, 2022 at 1:34 PM Weiwei Li wrote: > > - enable zb* extensions by default will make cpu types(such as sifive-u34) > implicitly support zb* extensions Agh, this is a pain. Can you enable these by default for the base machines then? That way they will be enabled for the virt

Re: [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

On Mon, May 16, 2022 at 1:36 PM Weiwei Li wrote: > > - setting ext_g will implicitly set ext_i > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > slirp | 2 +- > target/riscv/cpu.c | 23 --- > 2 files changed, 13 insertions(+), 12

Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match

On Thu, May 12, 2022 at 12:52 AM Anup Patel wrote: > > We should disable extensions in riscv_cpu_realize() if minimum required > priv spec version is not satisfied. This also ensures that machines with > priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter > extensions. > >

Re: [PULL 00/23] Misc QEMU patches for 2022-05-16

On 5/16/22 08:55, Paolo Bonzini wrote: The following changes since commit 48de9b0916ef60d5a6bd6ca9288832deff8ee1ee: Merge tag 'linux-headers-v5.18-rc6' of https://gitlab.com/alex.williamson/qemu into staging (2022-05-13 09:45:17 -0700) are available in the Git repository at:

Re: [PATCH v2 0/2] target/riscv: ISA string conversion fix and enhancement

On Tue, May 10, 2022 at 9:29 PM Tsukasa OI wrote: > > Hello, > > There is two issues related to RISC-V ISA extension string > I want to be fixed before QEMU 7.1 release. > > This is PATCH v2. > > For details, see cover letter of PATCH v1. >

Re: [PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode

On Thu, May 12, 2022 at 12:49 AM Anup Patel wrote: > > Currently, QEMU does not set hstatus.GVA bit for traps taken from > HS-mode into HS-mode which breaks the Xvisor nested MMU test suite > on QEMU. This was working previously. > > This patch updates riscv_cpu_do_interrupt() to fix the above

Re: [PATCH] hw/riscv: virt: Avoid double FDT platform node

On Fri, May 13, 2022 at 5:12 AM Dylan Reid wrote: > > When starting the virt machine with `-machine virt,aia=aplic-imsic`, > both the imsic and aplic init code will add platform fdt nodes by > calling `platform_bus_add_all_fdt_nodes`. This leads to an error at > startup: > ``` >

Re: [PATCH v2 2/2] target/riscv: Add short-isa-string option

On Tue, May 10, 2022 at 9:29 PM Tsukasa OI wrote: > > Because some operating systems don't correctly parse long ISA extension > string, this commit adds short-isa-string boolean option to disable > generating long ISA extension strings on Device Tree. > > For instance, enabling Zfinx and Zdinx

Re: [PATCH v2 1/2] target/riscv: Move Zhinx* extensions on ISA string

On Tue, May 10, 2022 at 9:29 PM Tsukasa OI wrote: > > This commit moves ISA string conversion for Zhinx and Zhinxmin extensions. > Because extension category ordering of "H" is going to be after "V", > their ordering is going to be valid (on canonical order). > > Signed-off-by: Tsukasa OI

Re: [PATCH 4/9] vfio/migration: Skip pre-copy if dirty page tracking is not supported

On Mon, May 16, 2022 at 02:22:00PM -0600, Alex Williamson wrote: > On Mon, 16 May 2022 13:22:14 +0200 > Juan Quintela wrote: > > > Avihai Horon wrote: > > > Currently, if IOMMU of a VFIO container doesn't support dirty page > > > tracking, migration is blocked completely. This is because a

Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp

On Sat, May 14, 2022 at 8:15 AM Atish Patra wrote: > > timecmp update function should be invoked with hartid for which > timecmp is being updated. The following patch passes the incorrect > hartid to the update function. > > Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register >

Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp

On Sat, May 14, 2022 at 8:15 AM Atish Patra wrote: > > timecmp update function should be invoked with hartid for which > timecmp is being updated. The following patch passes the incorrect > hartid to the update function. > > Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register >

[PATCH] nbd: Drop dead code spotted by Coverity

CID 1488362 points out that the second 'rc >= 0' check is now dead code. Reported-by: Peter Maydell Fixes: 172f5f1a40(nbd: remove peppering of nbd_client_connected) Signed-off-by: Eric Blake --- block/nbd.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/block/nbd.c

[PULL v2 85/86] virtio-net: don't handle mq request in userspace handler for vhost-vdpa

From: Si-Wei Liu virtio_queue_host_notifier_read() tends to read pending event left behind on ioeventfd in the vhost_net_stop() path, and attempts to handle outstanding kicks from userspace vq handler. However, in the ctrl_vq handler, virtio_net_handle_mq() has a recursive call into

[PULL v2 81/86] vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa

From: Si-Wei Liu ... such that no memory leaks on dangling net clients in case of error. Signed-off-by: Si-Wei Liu Acked-by: Jason Wang Message-Id: <1651890498-24478-4-git-send-email-si-wei@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin ---

[PULL v2 86/86] vhost-user-scsi: avoid unlink(NULL) with fd passing

From: Stefan Hajnoczi Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend Program conventions for vhost-user-scsi") introduced fd-passing support as part of implementing the vhost-user backend program conventions. When fd passing is used the UNIX domain socket path is NULL and

[PULL v2 77/86] hw/i386: Make pic a property of common x86 base machine type

From: Xiaoyao Li Legacy PIC (8259) cannot be supported for TDX guests since TDX module doesn't allow directly interrupt injection. Using posted interrupts for the PIC is not a viable option as the guest BIOS/kernel will not do EOI for PIC IRQs, i.e. will leave the vIRR bit set. Make PIC the

[PULL v2 84/86] vhost-vdpa: change name and polarity for vhost_vdpa_one_time_request()

From: Si-Wei Liu The name vhost_vdpa_one_time_request() was confusing. No matter whatever it returns, its typical occurrence had always been at requests that only need to be applied once. And the name didn't suggest what it actually checks for. Change it to vhost_vdpa_first_dev() with polarity

[PULL v2 80/86] virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa

From: Si-Wei Liu With MQ enabled vdpa device and non-MQ supporting guest e.g. booting vdpa with mq=on over OVMF of single vqp, below assert failure is seen: ../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >= dev->vq_index && idx < dev->vq_index + dev->nvqs' failed. 0

[PULL v2 82/86] vhost-net: fix improper cleanup in vhost_net_start

From: Si-Wei Liu vhost_net_start() missed a corresponding stop_one() upon error from vhost_set_vring_enable(). While at it, make the error handling for err_start more robust. No real issue was found due to this though. Signed-off-by: Si-Wei Liu Acked-by: Jason Wang Message-Id:

[PULL v2 70/86] virtio: drop name parameter for virtio_init()

From: Jonah Palmer This patch drops the name parameter for the virtio_init function. The pair between the numeric device ID and the string device ID (name) of a virtio device already exists, but not in a way that lets us map between them. This patch lets us do this and removes the need for the

[PULL v2 78/86] hw/i386/amd_iommu: Fix IOMMU event log encoding errors

From: Wei Huang Coverity issues several UNINIT warnings against amd_iommu.c [1]. This patch fixes them by clearing evt before encoding. On top of it, this patch changes the event log size to 16 bytes per IOMMU specification, and fixes the event log entry format in amdvi_encode_event(). [1] CID

[PULL v2 74/86] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK

From: Francisco Iglesias According to [1] address bits 27 - 20 are mapped to the bus number (the TLPs bus number field is 8 bits). Below is the formula taken from Table 7-1 in [1]. " Memory Address | PCI Express Configuration Space A[(20+n-1):20] | Bus Number, 1 ≤ n ≤ 8 " [1] PCI Express® Base

[PULL v2 76/86] hw/i386: Make pit a property of common x86 base machine type

From: Xiaoyao Li Both pc and microvm have pit property individually. Let's just make it the property of common x86 base machine type. Signed-off-by: Xiaoyao Li Reviewed-by: Sergio Lopez Message-Id: <20220310122811.807794-2-xiaoyao...@intel.com> Reviewed-by: Michael S. Tsirkin Signed-off-by:

[PULL v2 69/86] virtio/vhost-user: dynamically assign VhostUserHostNotifiers

From: Alex Bennée At a couple of hundred bytes per notifier allocating one for every potential queue is very wasteful as most devices only have a few queues. Instead of having this handled statically dynamically assign them and track in a GPtrArray. [AJB: it's hard to trigger the vhost

[PULL v2 73/86] docs/vhost-user: Clarifications for VHOST_USER_ADD/REM_MEM_REG

From: Kevin Wolf The specification for VHOST_USER_ADD/REM_MEM_REG messages is unclear in several points, which has led to clients having incompatible implementations. This changes the specification to be more explicit about them: * VHOST_USER_ADD_MEM_REG is not specified as receiving a file

[PULL v2 64/86] vhost-user.rst: add clarifying language about protocol negotiation

From: Alex Bennée Make the language about feature negotiation explicitly clear about the handling of the VHOST_USER_F_PROTOCOL_FEATURES feature bit. Try and avoid the sort of bug introduced in vhost.rs REPLY_ACK processing: https://github.com/rust-vmm/vhost/pull/24 Signed-off-by: Alex Bennée

[PULL v2 75/86] include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX

From: Francisco Iglesias According to 7.2.2 in [1] bit 27 is the last bit that can be part of the bus number, this makes the ECAM max size equal to '1 << 28'. This patch restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was changed in commit 58d5b22bbd5 ("ppc4xx: Add device

[PULL v2 71/86] virtio: add vhost support for virtio devices

From: Jonah Palmer This patch adds a get_vhost() callback function for VirtIODevices that returns the device's corresponding vhost_dev structure, if the vhost device is running. This patch also adds a vhost_started flag for VirtIODevices. Previously, a VirtIODevice wouldn't be able to tell if

[PULL v2 67/86] include/hw: start documenting the vhost API

From: Alex Bennée While trying to get my head around the nest of interactions for vhost devices I though I could start by documenting the key API functions. This patch documents the main API hooks for creating and starting a vhost device as well as how the configuration changes are handled.

[PULL v2 59/86] virtio-pci: add notification trace points

From: Alex Bennée Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200925125147.26943-6-alex.ben...@linaro.org> Signed-off-by: Alex Bennée Message-Id: <20220321153037.3622127-3-alex.ben...@linaro.org> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S.

[PULL v2 65/86] libvhost-user: expose vu_request_to_string

From: Alex Bennée This is useful for more human readable debug messages in vhost-user programs. Signed-off-by: Alex Bennée Message-Id: <20220321153037.3622127-9-alex.ben...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin ---

[PULL v2 57/86] vhost_net: Print feature masks in hex

From: Ilya Maximets "0x2" is much more readable than "8589934592". The change saves one step (conversion) while debugging. Signed-off-by: Ilya Maximets Message-Id: <20220318140440.596019-1-i.maxim...@ovn.org> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[PULL v2 72/86] vhost-user: more master/slave things

we switched to front-end/back-end, but newer patches reintroduced old language. Fix this up. Signed-off-by: Michael S. Tsirkin --- docs/interop/vhost-user.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst index

Re: [PULL 00/17] migration queue

On 5/16/22 08:37, Dr. David Alan Gilbert (git) wrote: From: "Dr. David Alan Gilbert" The following changes since commit 10c2a0c5e7d48e590d945c017b5b8af5b4c89a3c: Merge tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu into staging (2022-05-15 16:56:27 -0700) are

[PULL v2 68/86] hw/virtio/vhost-user: don't suppress F_CONFIG when supported

From: Alex Bennée Previously we would silently suppress VHOST_USER_PROTOCOL_F_CONFIG during the protocol negotiation if the QEMU stub hadn't implemented the vhost_dev_config_notifier. However this isn't the only way we can handle config messages, the existing vdc->get/set_config can do this as

[PULL v2 58/86] hw/virtio: move virtio-pci.h into shared include space

From: Alex Bennée This allows other device classes that will be exposed via PCI to be able to do so in the appropriate hw/ directory. I resisted the temptation to re-order headers to be more aesthetically pleasing. Signed-off-by: Alex Bennée Message-Id:

[PULL v2 47/86] hw/virtio: Replace g_memdup() by g_memdup2()

From: Philippe Mathieu-Daudé Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize

[PULL v2 66/86] docs/devel: start documenting writing VirtIO devices

From: Alex Bennée While writing my own VirtIO devices I've gotten confused with how things are structured and what sort of shared infrastructure there is. If we can document how everything is supposed to work we can then maybe start cleaning up inconsistencies in the code. Signed-off-by: Alex

[PULL v2 60/86] hw/virtio: add vhost_user_[read|write] trace points

From: Alex Bennée These are useful when trying to debug the initial vhost-user negotiation, especially when it hard to get logging from the low level library on the other side. Signed-off-by: Alex Bennée Message-Id: <20220321153037.3622127-4-alex.ben...@linaro.org> Reviewed-by: Michael S.

[PULL v2 42/86] docs/cxl: Add initial Compute eXpress Link (CXL) documentation.

From: Jonathan Cameron Provide an introduction to the main components of a CXL system, with detailed explanation of memory interleaving, example command lines and kernel configuration. This was a challenging document to write due to the need to extract only that subset of CXL information which

[PULL v2 63/86] docs: vhost-user: replace master/slave with front-end/back-end

From: Paolo Bonzini This matches the nomenclature that is generally used. Also commonly used is client/server, but it is not as clear because sometimes the front-end exposes a passive (server) socket that the back-end connects to. Signed-off-by: Paolo Bonzini Message-Id:

[PULL v2 54/86] intel-iommu: block output address in interrupt address range

From: Jason Wang According to vtd spec v3.3 3.14: """ Software must not program paging-structure entries to remap any address to the interrupt address range. Untranslated requests and translation requests that result in an address in the interrupt range will be blocked with condition code LGN.4

[PULL v2 83/86] vhost-vdpa: backend feature should set only once

From: Si-Wei Liu The vhost_vdpa_one_time_request() branch in vhost_vdpa_set_backend_cap() incorrectly sends down ioctls on vhost_dev with non-zero index. This may end up with multiple VHOST_SET_BACKEND_FEATURES ioctl calls sent down on the vhost-vdpa fd that is shared between all these

[PULL v2 41/86] qtest/cxl: Add more complex test cases with CFMWs

From: Ben Widawsky Add CXL Fixed Memory Windows to the CXL tests. Signed-off-by: Ben Widawsky Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-40-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[PULL v2 45/86] vdpa: Fix bad index calculus at vhost_vdpa_get_vring_base

From: Eugenio Pérez Fixes: 6d0b222666 ("vdpa: Adapt vhost_vdpa_get_vring_base to SVQ") Acked-by: Jason Wang Signed-off-by: Eugenio Pérez Message-Id: <20220512175747.142058-4-epere...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/vhost-vdpa.c |

[PULL v2 39/86] qtests/bios-tables-test: Add a test for CXL emulation.

From: Jonathan Cameron The DSDT includes several CXL specific elements and the CEDT table is only present if we enable CXL. The test exercises all current functionality with several CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC entries in DSDT. Signed-off-by: Jonathan Cameron

[PULL v2 79/86] virtio-net: setup vhost_dev and notifiers for cvq only when feature is negotiated

From: Si-Wei Liu When the control virtqueue feature is absent or not negotiated, vhost_net_start() still tries to set up vhost_dev and install vhost notifiers for the control virtqueue, which results in erroneous ioctl calls with incorrect queue index sending down to driver. Do that only when

[PULL v2 61/86] docs: vhost-user: clean up request/reply description

From: Paolo Bonzini It is not necessary to mention which side is sending/receiving each payload; it is more interesting to say which is the request and which is the reply. This also matches what vhost-user-gpu.rst already does. While at it, ensure that all messages list both the request and

[PULL v2 40/86] tests/acpi: Add tables for CXL emulation.

From: Jonathan Cameron Tables that differ from normal Q35 tables when running the CXL test. Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-39-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin ---

[PULL v2 53/86] intel-iommu: remove VTD_FR_RESERVED_ERR

From: Jason Wang This fault reason is not used and is duplicated with SPT.2 condition code. So let's remove it. Signed-off-by: Jason Wang Message-Id: <20220210092815.45174-1-jasow...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Peter Xu ---

[PULL v2 35/86] cxl/cxl-host: Add memops for CFMWS region.

From: Jonathan Cameron These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional

[PULL v2 62/86] docs: vhost-user: rewrite section on ring state machine

From: Paolo Bonzini This section is using the word "back-end" to refer to the "slave's back-end", and talking about the "client" for what the rest of the document calls the "slave". Rework it to free the use of the term "back-end", which in the next patch will replace "slave". Signed-off-by:

[PULL v2 51/86] intel_iommu: Only allow interrupt remapping to be enabled if it's supported

From: David Woodhouse We should probably check if we were meant to be exposing IR, before letting the guest turn the IRE bit on. Signed-off-by: David Woodhouse Reviewed-by: Peter Xu Acked-by: Jason Wang Message-Id: <20220314142544.150555-3-dw...@infradead.org> Reviewed-by: Michael S. Tsirkin

[PULL v2 33/86] CXL/cxl_component: Add cxl_get_hb_cstate()

From: Jonathan Cameron Accessor to get hold of the cxl state for a CXL host bridge without exposing the internals of the implementation. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20220429144110.25167-32-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin

[PULL v2 37/86] i386/pc: Enable CXL fixed memory windows

From: Jonathan Cameron Add the CFMWs memory regions to the memorymap and adjust the PCI window to avoid hitting the same memory. Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-36-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[PULL v2 56/86] intel-iommu: update iq_dw during post load

From: Jason Wang We need to update iq_dw according to the DMA_IRQ_REG during post load. Otherwise we may get wrong IOTLB invalidation descriptor after migration. Fixes: fb43cf739e ("intel_iommu: scalable mode emulation") Signed-off-by: Jason Wang Message-Id:

[PULL v2 36/86] hw/cxl/component Add a dumb HDM decoder handler

From: Ben Widawsky Add a trivial handler for now to cover the root bridge where we could do some error checking in future. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-35-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin

[PULL v2 52/86] intel_iommu: Fix irqchip / X2APIC configuration checks

From: David Woodhouse We don't need to check kvm_enable_x2apic(). It's perfectly OK to support interrupt remapping even if we can't address CPUs above 254. Kind of pointless, but still functional. The check on kvm_enable_x2apic() needs to happen *anyway* in order to allow CPUs above 254 even

[PULL v2 29/86] hw/cxl/host: Add support for CXL Fixed Memory Windows.

From: Jonathan Cameron The concept of these is introduced in [1] in terms of the description the CEDT ACPI table. The principal is more general. Unlike once traffic hits the CXL root bridges, the host system memory address routing is implementation defined and effectively static once observable

[PULL v2 32/86] pci/pcie_port: Add pci_find_port_by_pn()

From: Jonathan Cameron Simple function to search a PCIBus to find a port by it's port number. CXL interleave decoding uses the port number as a target so it is necessary to locate the port when doing interleave decoding. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id:

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