On 5/20/22 12:26 PM, Chao Gao wrote:
On Fri, May 20, 2022 at 10:30:40AM +0700, Suthikulpanit, Suravee wrote:
Hi All,
Currently, we don't have a good way to check whether APICV is active on a VM.
Normally, For AMD SVM AVIC, users either have to check for trace point, or using
"perf kvm stat
On Fri, May 20, 2022 at 10:30:40AM +0700, Suthikulpanit, Suravee wrote:
>Hi All,
>
>Currently, we don't have a good way to check whether APICV is active on a VM.
>Normally, For AMD SVM AVIC, users either have to check for trace point, or
>using
>"perf kvm stat live" to catch AVIC-related #VMEXIT.
As PCI_EXP_LNKCAP is never masked when loading, this patch does affect
cross version migration. It seems we need machine type compat to deal
with that. What do you suggest, Michael?
On 5/20/22 12:49 AM, Michael S. Tsirkin wrote:
On Thu, May 19, 2022 at 10:45:59PM +0800, Wenliang Wang wrote:
Hi All,
Currently, we don't have a good way to check whether APICV is active on a VM.
Normally, For AMD SVM AVIC, users either have to check for trace point, or using
"perf kvm stat live" to catch AVIC-related #VMEXIT.
For KVM, I would like to propose introducing a new IOCTL interface (i.e.
Add a new 'guest-get-diskstats' command for report disk io statistics
for Linux guests. This can be useful for getting io flow or handling
IO fault, no need to enter guests.
Signed-off-by: luzhipeng
Reviewed-by: Marc-André Lureau
---
Changes v4->v5: fix Typo and adjust fileds order in
Excerpts from Richard Henderson's message of May 20, 2022 4:31 am:
> On 5/19/22 07:11, Nicholas Piggin wrote:
>> dcache writeback and icache invalidate is not required when icache is
>> coherent, a shorter fixed-length sequence can be used which just has to
>> flush and re-fetch instructions that
On Mon, May 16, 2022, 12:53 PM Daniel Henrique Barboza <
danielhb...@gmail.com> wrote:
> pSeries guests set a handful of machine capabilities on by default, all
> of them related to security mitigations, that aren't always available in
> the host.
>
> This means that, as is today, running avocado
On Thu, May 19, 2022, 4:25 AM Daniel P. Berrangé
wrote:
> On Thu, May 19, 2022 at 09:54:56AM +0200, Kevin Wolf wrote:
> > Am 18.05.2022 um 20:21 hat John Snow geschrieben:
> > > To wire it up to "make check" by *default*, I believe I need to expand
> the
> > > configure script to poll for
On Thu, May 19, 2022 at 4:23 PM Icenowy Zheng wrote:
> 在 2020-11-18星期三的 00:39 +0100，Linus Walleij写道：
> > It was brought to my attention that this bug from 2018 was
> > still unresolved: 32 bit emulators like QEMU were given
> > 64 bit hashes when running 32 bit emulation on 64 bit systems.
>
>
On Thu, May 19, 2022 at 08:34:06PM +0530, Anup Patel wrote:
> On Fri, May 13, 2022 at 1:34 AM Dylan Reid wrote:
> >
> > When starting the virt machine with `-machine virt,aia=aplic-imsic`,
> > both the imsic and aplic init code will add platform fdt nodes by
> > calling
-hppa into staging (2022-05-18 09:32:15 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220519
for you to fetch changes up to fab8ad39fb75a0d9f097db67b2a33754e88e:
target/arm: Use FIELD definitions for CPACR
From: Matheus Ferst
Move vmsumshm and vmsumshs to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument of vmsumshm.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 4 ++--
target/ppc/insn32.decode
From: Matheus Ferst
fsel doesn't change FPSCR and CR1 is handled by gen_set_cr1_from_fpscr,
so helper_fsel doesn't need the env argument and can be declared with
TCG_CALL_NO_RWG_SE. We also take this opportunity to move the insn to
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by:
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/translate/vmx-impl.c.inc | 32 +
1 file changed, 5 insertions(+), 27 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
From: Matheus Ferst
Move vmsumuhm and vmsumuhs to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument of vmsumuhm.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 4 ++--
target/ppc/insn32.decode
From: Matheus Ferst
Helpers of VSX instructions without cpu_env as an argument cannot access
globals.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/ppc/helper.h
From: Matheus Ferst
Move xxextractuw and xxinsertw to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 4 +-
target/ppc/insn32.decode| 9
From: Matheus Ferst
Move vmsumubm and vmsummbm to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 4 ++--
target/ppc/insn32.decode| 3 +++
From: Matheus Ferst
Helpers of BCD instructions only access the VSRs supplied by the
TCGv_ptr arguments, no globals are accessed.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 30 +++---
1 file changed, 15 insertions(+), 15
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index aa6773c4a5..718ab6bc7b 100644
--- a/target/ppc/helper.h
+++
From: Matheus Ferst
Move xscvspdpn to decodetree, drop helper_xscvspdpn and use
helper_todouble directly.
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 5 -
target/ppc/helper.h | 1 -
target/ppc/insn32.decode| 1 +
From: Matheus Ferst
Move xvxsigsp to decodetree, declare helper_xvxsigsp with
TCG_CALL_NO_RWG, and drop the unused env argument.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 2 +-
target/ppc/helper.h | 2 +-
From: Matheus Ferst
Helpers of vector instructions without cpu_env as an argument cannot
access globals.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 162 ++--
1 file changed, 81 insertions(+), 81 deletions(-)
From: Matheus Ferst
In our "PowerISA Vector/VSX instruction batch" patch series, rth noted[1]
that helpers that only access vector registers should be declared with
DEF_HELPER_FLAGS_* and TCG_CALL_NO_RWG. We fixed helpers in that series,
but there are older helpers that could use the same
This isolates shadow cvq in its own group.
Signed-off-by: Eugenio Pérez
---
qapi/net.json| 8 ++-
net/vhost-vdpa.c | 134 ---
2 files changed, 133 insertions(+), 9 deletions(-)
diff --git a/qapi/net.json b/qapi/net.json
index
To know the device features is needed for CVQ SVQ, so SVQ knows if it
can handle all commands or not. Extract from
vhost_vdpa_get_max_queue_pairs so we can reuse it.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 30 --
1 file changed, 20 insertions(+), 10
Finally offering the possibility to enable SVQ from the command line.
Signed-off-by: Eugenio Pérez
---
qapi/net.json| 9 -
net/vhost-vdpa.c | 38 +++---
2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/qapi/net.json b/qapi/net.json
To restore the device in the destination of a live migration we send the
commands through control virtqueue. For a device to read CVQ it must
have received DRIVER_OK status bit.
However this open a window where the device could start receiving
packets in rx queue 0 before it receive the RSS
Now that different vqs can have different ASIDs its easier to track them
using reference counters.
QEMU's glib version still does not have them so we've copied g_rc_box,
so the implementation can be converted to glib's one when the minimum
version is raised.
Signed-off-by: Eugenio Pérez
---
It allows the Shadow Control VirtQueue to wait the device to use the commands
that restore the net device state after a live migration.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 1 +
hw/virtio/vhost-shadow-virtqueue.c | 57 +++---
2 files
Signed-off-by: Eugenio Pérez
---
include/standard-headers/linux/vhost_types.h | 11 -
linux-headers/linux/vhost.h | 25
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/include/standard-headers/linux/vhost_types.h
As a first step we only enable CVQ first than others. Future patches add
state restore.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 61
1 file changed, 61 insertions(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index
We can configure ASID per group, but we still use asid 0 for every vdpa
device. Multiple asid support for cvq will be introduced in next
patches
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost.h | 1 +
hw/net/vhost_net.c| 1 +
hw/virtio/vhost-vdpa.c| 71
This allows SVQ to add metadata to the different queue elements.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 8 --
hw/virtio/vhost-shadow-virtqueue.c | 46 --
2 files changed, 31 insertions(+), 23 deletions(-)
diff --git
It allows to run commands at SVQ start.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 4
hw/virtio/vhost-vdpa.c | 14 ++
2 files changed, 18 insertions(+)
diff --git a/hw/virtio/vhost-shadow-virtqueue.h
b/hw/virtio/vhost-shadow-virtqueue.h
CVQ needs to be in its own group, not shared with any data vq. Enable
the checking of it here, before introducing address space id concepts.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost.h | 2 +
hw/net/vhost_net.c| 4 +-
hw/virtio/vhost-vdpa.c| 79
This allows qemu to inject buffers to the device without guest's notice.
This will be use to inject net CVQ messages to restore status in the
destination.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 5 +++
hw/virtio/vhost-shadow-virtqueue.c | 72
It's done for both in and out descriptors so it's better placed here.
Acked-by: Jason Wang
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.c | 38 +-
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/hw/virtio/vhost-shadow-virtqueue.c
The callback allows SVQ users to know the VirtQueue requests and
responses. QEMU can use this to synchronize virtio device model state,
allowing to migrate it with minimum changes to the migration code.
In the case of networking, this will be used to inspect control
virtqueue messages.
Just a simple wrapper so we can find DMAMap entries based on iova
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-iova-tree.h | 2 ++
hw/virtio/vhost-iova-tree.c | 14 ++
2 files changed, 16 insertions(+)
diff --git a/hw/virtio/vhost-iova-tree.h b/hw/virtio/vhost-iova-tree.h
Net Shadow Control VirtQueue will use them to map buffers outside of the
guest's address space.
These are needed for other features like indirect descriptors. They can be used
to map SVQ vrings: It is currently done outside of
vhost-shadow-virtqueue.c and that is a duplication.
Signed-off-by:
Enable SVQ to not to forward the descriptor translating its address to
qemu's IOVA but copying to a region outside of the guest.
Virtio-net control VQ will use this mode, so we don't need to send all
the guest's memory every time there is a change, but only on messages.
Reversely, CVQ will only
So SVQ can allocate elements by calling it.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/virtio.h | 1 +
hw/virtio/virtio.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index db1c0ddf6b..5ca29e8757
Introduce the control virtqueue support for vDPA shadow virtqueue. This
is needed for advanced networking features like multiqueue.
To demonstrate command handling, VIRTIO_NET_F_CTRL_MACADDR and
VIRTIO_NET_CTRL_MQ are implemented. If vDPA device is started with SVQ
support and virtio-net driver
This allows external vhost-net devices to modify the state of the
VirtIO device model once vhost-vdpa device has acknowledge the control
commands.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/virtio-net.h | 4 ++
hw/net/virtio-net.c| 84 --
2
Control virtqueue is used by networking device for accepting various
commands from the driver. It's a must to support multiqueue and other
configurations.
Shadow VirtQueue (SVQ) already makes possible migration of virtqueue
states, effectively intercepting them so qemu can track what regions of
On Tue, May 17, 2022 at 03:53:52PM +0200, Paolo Bonzini wrote:
> On 5/16/22 19:38, Raphael Norwitz wrote:
> > [1] Keep using the SCSI translation in QEMU but back vDisks with a
> > vhost-user-scsi or vhost-user-blk backend device.
> > [2] Implement SATA and IDE emulation with vfio-user (likely
On Tue, May 17, 2022 at 04:29:17PM +0100, Stefan Hajnoczi wrote:
> On Mon, May 16, 2022 at 05:38:31PM +, Raphael Norwitz wrote:
> > Hey Stefan,
> >
> > We've been thinking about ways to accelerate other disk types such as
> > SATA and IDE rather than translating to SCSI and using QEMU's iSCSI
On 5/19/22 07:11, Nicholas Piggin wrote:
dcache writeback and icache invalidate is not required when icache is
coherent, a shorter fixed-length sequence can be used which just has to
flush and re-fetch instructions that were in-flight.
Signed-off-by: Nicholas Piggin
---
I haven't been able to
On Wed, May 18, 2022 at 3:46 AM Peter Maydell wrote:
>
> On Wed, 18 May 2022 at 09:25, Daniel P. Berrangé wrote:
> > The fact that RISC-V ecosystem is so young & has relatively few
> > users, and even fewer expecting long term stability, is precisely
> > why we should just modify the existing
On Mon, 16 May 2022 16:46:29 -0400
"Michael S. Tsirkin" wrote:
> On Mon, May 16, 2022 at 11:26:03AM -0400, Igor Mammedov wrote:
> > .. and clean up not longer needed conditionals in DSTD build code
> > pvpanic-isa AML will be fetched and included when ISA bridge will
> > build its own AML code
From: Richard Henderson
This feature adds a new register, HCRX_EL2, which controls
many of the newer AArch64 features. So far the register is
effectively RES0, because none of the new features are done.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU
From: Florian Lugou
As per the description of the HCR_EL2.APK field in the ARMv8 ARM,
Pointer Authentication keys accesses should only be trapped to Secure
EL2 if it is enabled.
Signed-off-by: Florian Lugou
Reviewed-by: Richard Henderson
Message-id:
From: Richard Henderson
We had a few CPTR_* bits defined, but missed quite a few.
Complete all of the fields up to ARMv9.2.
Use FIELD_EX64 instead of manual extract32.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220517054850.177016-3-richard.hender...@linaro.org
Make the GICv3 set its number of bits of physical priority from the
implementation-specific value provided in the CPU state struct, in
the same way we already do for virtual priority bits. Because this
would be a migration compatibility break, we provide a property
force-8-bit-prio which is
In the virt board with secure=on we put two nodes in the dtb
for flash devices: one for the secure-only flash, and one
for the non-secure flash. We get the reg properties for these
correct, but in the DT node name, which by convention includes
the base address of devices, we used the wrong
We previously open-coded the expression for the number of virtual APR
registers and the assertion that it was not going to cause us to
overflow the cs->ich_apr[] array. Factor this out into a new
ich_num_aprs() function, for consistency with the icc_num_aprs()
function we just added for the
In commit 88ce6c6ee85d we switched from directly fishing the number
of breakpoints and watchpoints out of the ID register fields to
abstracting out functions to do this job, but we forgot to delete the
now-obsolete comment in define_debug_regs() about the relation
between the ID field value and
From: Chris Howard
Give all the debug registers their correct names including the
index, rather than having multiple registers all with the
same name string, which is confusing when viewed over the
gdbstub interface.
Signed-off-by: CHRIS HOWARD
Reviewed-by: Richard Henderson
Message-id:
The GICv3 code has always supported a configurable number of virtual
priority and preemption bits, but our implementation currently
hardcodes the number of physical priority bits at 8. This is not
what most hardware implementations provide; for instance the
Cortex-A53 provides only 5 bits of
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was
The GIC_MIN_BPR constant defines the minimum BPR value that the TCG
emulated GICv3 supports. We're currently using this also as the
value we reset the KVM GICv3 ICC_BPR registers to, but this is only
right by accident.
We want to make the emulated GICv3 use a configurable number of
priority
The traditional ptimer behaviour includes a collection of weird edge
case behaviours. In 2016 we improved the ptimer implementation to
fix these and generally make the behaviour more flexible, with
ptimers opting in to the new behaviour by passing an appropriate set
of policy flags to
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
From: Philippe Mathieu-Daudé
Except hw/core/irq.c which implements the forward-declared opaque
qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not
using the typedef. Fix this single exception.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bernhard Beschow
Message-id:
The unsupported_encoding() macro logs a LOG_UNIMP message and then
generates code to raise the usual exception for an unallocated
encoding. Back when we were still implementing the A64 decoder this
was helpful for flagging up when guest code was using something we
hadn't yet implemented. Now we
Factor out the part of combine_cacheattrs() that is specific to
handling HCR_EL2.FWB == 0. This is the part where we combine the
memory type and cacheability attributes.
The "force Outer Shareable for Device or Normal Inner-NC Outer-NC"
logic remains in combine_cacheattrs() because it holds
The virt board generates a gpio-keys node in the dtb, but it
incorrectly gives this node #size-cells and #address-cells
properties. If you dump the dtb with 'machine dumpdtb=file.dtb'
and run it through dtc, dtc will warn about this:
Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary
Implement the handling of FEAT_S2FWB; the meat of this is in the new
combined_attrs_fwb() function which combines S1 and S2 attributes
when HCR_EL2.FWB is set.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20220505183950.2781801-4-peter.mayd...@linaro.org
---
In the original Arm v8 two-stage translation, both stage 1 and stage
2 specify memory attributes (memory type, cacheability,
shareability); these are then combined to produce the overall memory
attributes for the whole stage 1+2 access. In QEMU we implement this
by having get_phys_addr() fill in
We allow a GICv3 to be connected to any CPU, but we don't do anything
to handle the case where the CPU type doesn't in hardware have a
GICv3 CPU interface and so the various GIC configuration fields
(gic_num_lrs, vprebits, vpribits) are not specified.
The current behaviour is that we will add the
The Armv8.4 feature FEAT_IDST specifies that exceptions generated by
read accesses to the feature ID space should report a syndrome code
of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED).
The feature ID space is defined to be:
op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7},
)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220519
for you to fetch changes up to fab8ad39fb75a0d9f097db67b2a33754e88e:
target/arm: Use FIELD definitions for CPACR, CPTR_ELx (2022-05-19 18:34:10
+0100
On 5/19/22 09:48, Viktor Prutyanov wrote:
+if (ehdr->e_ident[EI_CLASS] != ELFCLASS64 ||
+ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
+eprintf("Invalid ELF class or byte order, must be 64-bit LE\n");
+return false;
+}
You could check EI_VERSION == EV_CURRENT
Hi
Before I send a v4 and hopefully final version, could somebody review
those patches:
- include: move qemu_*_exec_dir() to cutils
- osdep: export qemu_open_cloexec()
- qga: replace qemu_open_old() with qemu_open_cloexec()
- test/qga: use G_TEST_DIR to locate os-release test file
(Paolo
pcie_cap_fill_slot_lnk() wrongly set PCI_EXP_LNKCAP when slot speed
and width is not set, causing strange downstream port link cap
(Speed unknown, Width x0) and pcie devices native hotplug error on Linux:
[3.545654] pcieport :02:00.0: pciehp: link training error: status 0x2000
[
On Thu, May 19, 2022 at 10:45:59PM +0800, Wenliang Wang wrote:
> pcie_cap_fill_slot_lnk() wrongly set PCI_EXP_LNKCAP when slot speed
> and width is not set, causing strange downstream port link cap
> (Speed unknown, Width x0) and pcie devices native hotplug error on Linux:
>
> [3.545654]
Add ELF header checking to prevent processing input file which is not
QEMU guest memory dump or even not ELF.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1013
Signed-off-by: Viktor Prutyanov
---
contrib/elf2dmp/qemu_elf.c | 38 ++
1 file changed,
On 5/19/22 03:40, Peter Maydell wrote:
Not all the code that looks at the sve vector length
goes through sve_zcr_len_for_el(), though. In particular,
this is setting up ZCR_EL1 for usermode, and all
the code under linux-user/ that wants to know the vector
length does it with "env->vfp.zcr_el[1]
We have "-sdl" and "-curses", but no "-gtk" and no "-cocoa" ...
these old-style options are rather confusing than helpful nowadays.
Now that the deprecation period is over, let's remove them, so we
get a cleaner interface (where "-display" is the only way to select
the user interface).
Dropping these deprecated parameters simplifies further refactoring
(e.g. QAPIfication is easier without underscores in the name).
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
Signed-off-by: Thomas Huth
---
docs/about/deprecated.rst | 16 -
The "-display sdl" option still uses a hand-crafted parser for its
parameters since some of them used underscores which is disliked in QAPI.
Now that they've been deprecated and the deprecation period is over, we
can remove the problematic parameters and switch to use the QAPI parser
instead.
This is the v6 of this series which tries to implement the fd-based KVM
guest private memory. The patches are based on latest kvm/queue branch
commit:
2764011106d0 (kvm/queue) KVM: VMX: Include MKTME KeyID bits in
shadow_zero_check
and Sean's below patch:
KVM: x86/mmu: Add RET_PF_CONTINUE
Signed-off-by: Chao Peng
---
man2/memfd_create.2 | 13 +
1 file changed, 13 insertions(+)
diff --git a/man2/memfd_create.2 b/man2/memfd_create.2
index 89e9c4136..2698222ae 100644
--- a/man2/memfd_create.2
+++ b/man2/memfd_create.2
@@ -101,6 +101,19 @@ meaning that no other seals can
Register private memslot to fd-based memory backing store and handle the
memfile notifiers to zap the existing mappings.
Currently the register is happened at memslot creating time and the
initial support does not include page migration/swap.
KVM_MEM_PRIVATE is not exposed by default,
This new KVM exit allows userspace to handle memory-related errors. It
indicates an error happens in KVM at guest memory range [gpa, gpa+size).
The flags includes additional information for userspace to handle the
error. Currently bit 0 is defined as 'private memory' where '1'
indicates error
Introduce a new memfd_create() flag indicating the content of the
created memfd is inaccessible from userspace through ordinary MMU
access (e.g., read/write/mmap). However, the file content can be
accessed via a different mechanism (e.g. KVM MMU) indirectly.
It provides semantics required for KVM
Extend the memslot definition to provide guest private memory through a
file descriptor(fd) instead of userspace_addr(hva). Such guest private
memory(fd) may never be mapped into userspace so no userspace_addr(hva)
can be used. Instead add another two new fields
(private_fd/private_offset), plus
The core and the vblend registers size are wrong, they should respectively be
0x3B0 and 0x1E0 according to:
https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html.
Let's fix that and use macros when creating the mmio region.
Fixes: 58ac482a66d ("introduce
From: "Kirill A. Shutemov"
Implement shmem as a memfile_notifier backing store. Essentially it
interacts with the memfile_notifier feature flags for userspace
access/page migration/page reclaiming and implements the necessary
memfile_backing_store callbacks.
Signed-off-by: Kirill A. Shutemov
The "-display sdl" option still uses a hand-crafted parser for its
parameters since we didn't want to drag an interface we considered
somewhat flawed into the QAPI schema. Since the flaws are gone now,
it's time to QAPIfy.
This introduces the new "DisplaySDL" QAPI struct that is used to hold
the
This patch introduces memfile_notifier facility so existing memory file
subsystems (e.g. tmpfs/hugetlbfs) can provide memory pages to allow a
third kernel component to make use of memory bookmarked in the memory
file and gets notified when the pages in the memory file become
allocated/invalidated.
From: Sai Pavan Boddu
Add a periodic timer which raises vblank at a frequency of 30Hz.
Signed-off-by: Sai Pavan Boddu
Signed-off-by: Edgar E. Iglesias
Changes by fkonrad:
- Switched to transaction-based ptimer API.
- Added the DP_INT_VBLNK_START macro.
Signed-off-by: Frederic Konrad
---
Hi,
This patch set fixes some issues with the DisplayPort for the ZCU102:
The first patch fixes the wrong register size and thus the risk of register
overflow.
The three other one add a vblank interrupt required by the linux driver:
- When using the VNC graphic backend and leaving it
From: Sai Pavan Boddu
Fix interrupt disable logic. Mask value 1 indicates that interrupts are
disabled.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Frederic Konrad
---
hw/display/xlnx_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
When the display port has been initially implemented the device driver wasn't
using interrupts. Now that the display port driver waits for vblank interrupt
it has been noticed that the irq mapping is wrong. So use the value from the
linux device tree and the ultrascale+ reference manual.
rom_set_order_override() and rom_reset_order_override() were called
in qemu_create_cli_devices() to set the rom_order_override value
once and for all when creating the devices added on CLI.
Unfortunately this won't work with qapi commands.
Move the calls inside device_add so that it will be done
A page fault can carry the information of whether the access if private
or not for KVM_MEM_PRIVATE memslot, this can be filled by architecture
code(like TDX code). To handle page faut for such access, KVM maps the
page only when this private property matches host's view on this page
which can be
phase_get() returns the current phase, we'll use it in next
commit.
Signed-off-by: Damien Hedde
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 19 +++
hw/core/qdev.c | 5 +
2 files changed, 24 insertions(+)
diff --git a/include/hw/qdev-core.h
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