On Jun 2 08:49, Cédric Le Goater wrote:
> On 6/1/22 23:08, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > Build a single string instead of having several parameters on the trace
> > event.
> >
> > Suggested-by: Cédric Le Goater
> > Signed-off-by: Klaus Jensen
> > ---
> > hw/i2c/aspeed_i
On 6/1/22 23:08, Klaus Jensen wrote:
From: Klaus Jensen
Build a single string instead of having several parameters on the trace
event.
Suggested-by: Cédric Le Goater
Signed-off-by: Klaus Jensen
---
hw/i2c/aspeed_i2c.c | 55 +++--
hw/i2c/trace-events
On 31/05/2022 20.35, Gautam Agrawal wrote:
Add a test to check for overflow conditions in s390x.
This patch is based on the following patches :
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5a2e67a691501
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=fc6e0d0f2db51
Signed-off-by: Gautam Ag
Hi Stefan,
Stefan Hajnoczi 于2022年6月1日周三 19:43写道：
>
> On Wed, 1 Jun 2022 at 06:47, Damien Le Moal
> wrote:
> >
> > On 6/1/22 11:57, Sam Li wrote:
> > > Hi Stefan,
> > >
> > > Stefan Hajnoczi 于2022年5月30日周一 19:19写道：
> > >
> > >
> > >>
> > >> On Mon, 30 May 2022 at 06:09, Sam Li wrote:
> > >>>
> >
On Thu, Jun 2, 2022, 02:04 Tong Zhang wrote:
>
> Hi Stefan,
>
> On Wed, Jun 1, 2022 at 6:56 AM Stefan Hajnoczi wrote:
> >
> > > > This patch makes sense to me. Can you rephrase your concern?
> > >
> > > The locking is around dbs->io_func().
> > >
> > > aio_context_acquire(dbs->ctx);
> > > dbs->ac
Hi, Alex,
> From: Alex Williamson
> Sent: Thursday, June 2, 2022 2:01 AM
>
> On Wed, 1 Jun 2022 17:09:25 +
> "Dong, Eddie" wrote:
>
> > > -Original Message-
> > > From: Qemu-devel > > bounces+eddie.dong=intel@nongnu.org> On Behalf Of Alex
> Williamson
> > > On Tue, 24 May 2022
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, June 1, 2022 3:10 PM
> To: Peter Delevoryas
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; zhdan...@fb.com; Troy
> Lee ; Jamin Lin ;
> Steven Lee ; k.jen...@samsung.com; Joe
> Komlodi ; Joel Stanley ; Andrew
>
On Thu, 2 Jun 2022 at 01:17, Richard Henderson
wrote:
>
> The masking in tcg_out_shl was incorrect, producing an
> illegal instruction, rather than merely unspecified results
> for the out-of-range shift.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1051
> Signed-off-by: Richard Hen
Unlike i386, m68k get_thread_area has no arguments.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
linux-user/strace.list | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index 278596acd1..72e17b1acf 100644
--- a/linux-us
Errors are not all negative numbers: use is_error.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/strace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 9fa681dea9..7d882526da 100644
--- a
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index fa704e0c25..cc3bd4dd2b 100644
--- a/target/m68k/translate.c
+++ b/t
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 83c2f73063..fa704e0c25 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
TPF stands for "trap false", and is a long-form nop for ColdFire.
Re-use the immediate consumption code from trapcc; the insn will
already expand to a nop because of the TCG_COND_NEVER test
within do_trapcc.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Signed-off-by: Richard H
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
v6: Use more exact masks for trapcc, to fix overlap with scc.
---
target/m68k/cpu.h | 2 ++
linux-user/m68k/cpu_loop.c | 1 +
target/m68k/cpu.c | 1 +
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), CHK, CHK2 (and others)
are supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
Create a raise_exception_format2 function to centralize recording
of the trapping pc in mm
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Trace (and others) is
supposed to record the next insn in PC and the address
of the trapping instruction in ADDRESS.
Create gen_raise_exception_format2 to record the trapping
pc in env->mmu.ar. Update m68k_inter
According to the M68040 Users Manual, section 8.4.1, Four word
stack frame (format 0), includes Illegal Instruction. Use the
correct frame format, which does not use the ADDR argument.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 5 -
1 file ch
The only value this variable holds is now env->pc.
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m
These are raised by guest instructions, and should not
fall through into the default abort case.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c
index 56417f7401..12e5d
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc,
and the signals and addresses that we expect from them.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
tests/tcg/m68k/trap.c | 129 +
tests/tcg/m68k/Makefile.target
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Zero Div (and others)
is supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
While the N, Z and V flags are documented to be undefine on DIV0,
the C flag is documented a
Add parenthesis around & vs &&.
Remove assignment to sr in function call argument -- note that
sr is unused after the call, so the assignment was never needed,
only the result of the & expression.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivi
Replace an if ladder with a switch for clarity.
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 49 +
1 file changed, 30 insertions(+), 19 deletions(-)
diff --git a/target/m6
Also mark raise_exception_ra and raise_exception, lest we
generate a warning about helper_raise_exception returning.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/helper.h| 2 +-
target/m68k/op_helper.c | 5 +++--
2 files c
Rather than adjust the PC in all of the consumers, raise
the exception with the correct PC in the first place.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 1 -
target/m68k/op_helper.c| 9 -
target/m68k/translate.c| 2 +-
3 files
Changes for v6:
* Use exact masks for registering trapcc and ftrapcc.
These insn overlap illegal scc and fscc operands,
so we need to be exact about the registration.
r~
Richard Henderson (17):
target/m68k: Raise the TRAPn exception with the correct pc
target/m68k: Switch over exc
On Wed, May 25, 2022 at 7:55 PM Tsukasa OI wrote:
>
> This commit adds a deprecation note of capitalized property names of
> RISC-V CPU to documentation.
>
> Signed-off-by: Tsukasa OI
> ---
> docs/about/deprecated.rst | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/docs/a
On Tue, May 31, 2022 at 12:59 AM Philippe Mathieu-Daudé via
wrote:
>
> Hi Peter,
>
> On 28/4/22 01:07, Peter Collingbourne wrote:
> > Currently the loader uses int as the return type for various APIs
> > that deal with file sizes, which leads to an error if the file
> > size is >=2GB, as it ends u
On Thu, May 26, 2022 at 1:27 AM Tsukasa OI wrote:
>
> On 2022/05/25 21:10, Víctor Colombo wrote:
> > On 25/05/2022 06:54, Tsukasa OI wrote:
> >> Many CPU properties for RISC-V are in lowercase except those with
> >> "capitalized" (or CamelCase) names:
> >>
> >> - Counters
> >> - Zifencei
> >>
The masking in tcg_out_shl was incorrect, producing an
illegal instruction, rather than merely unspecified results
for the out-of-range shift.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1051
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
1 file changed, 1
On Fri, Nov 12, 2021 at 12:12 AM Jamie Iles wrote:
>
> Various loader functions return an int which limits images to 2GB which
> is fine for things like a BIOS/kernel image, but if we want to be able
> to load memory images or large ramdisks then any file over 2GB would
> silently fail to load.
>
On Wed, Jun 1, 2022 at 11:36 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Since commit ad40be27 "target/riscv: Support start kernel directly by
> KVM" we have been overflowing the addr_config on "M,MS..."
> configurations, as reported
> https://gitlab.com/qemu-project/qemu/-/issues/
Hi Stefan,
On Wed, Jun 1, 2022 at 6:56 AM Stefan Hajnoczi wrote:
>
> > > This patch makes sense to me. Can you rephrase your concern?
> >
> > The locking is around dbs->io_func().
> >
> > aio_context_acquire(dbs->ctx);
> > dbs->acb = dbs->io_func()
> > aio_context_release(dbs->ctx);
> >
> >
> > S
On 6/1/2022 3:54 PM, Gerd Hoffmann wrote:
On Wed, Jun 01, 2022 at 03:20:46PM +0800, Xiaoyao Li wrote:
On 5/24/2022 2:57 PM, Gerd Hoffmann wrote:
Hi,
Maybe it's a bit more work to add VM-scope initialization support to
qemu.
If just introducing VM-scope initialization to QEMU, it would be
On Thu, Jun 2, 2022 at 3:32 AM wrote:
>
> From: Sai Pavan Boddu
>
> Fix interrupt disable logic. Mask value 1 indicates that interrupts are
> disabled.
>
> Signed-off-by: Sai Pavan Boddu
> Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Frederic Konrad
Acked-by: Alistair Francis
Alistair
>
On Thu, Jun 2, 2022 at 3:29 AM wrote:
>
> From: Sai Pavan Boddu
>
> Add a periodic timer which raises vblank at a frequency of 30Hz.
>
> Signed-off-by: Sai Pavan Boddu
> Signed-off-by: Edgar E. Iglesias
> Changes by fkonrad:
> - Switched to transaction-based ptimer API.
> - Added the DP_INT
We wanted the VPSRAQ variant with the scalar vector shift operand,
not the variant with an immediate operand.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1022
Fixes: 47b331b2a8da ("tcg/i386: Implement avx512 scalar shift")
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.in
From: Christoph Muellner
This patch adds support for the Zawrs ISA extension.
Given the current (incomplete) implementation of reservation sets
there seems to be no way to provide a full emulation of the WRS
instruction (wake on reservation set invalidation or timeout or
interrupt). Therefore, we
This patch adds support for the Zawrs ISA extension.
Given the current (incomplete) implementation of reservation sets
there seems to be no way to provide a full emulation of the WRS
instruction (wake on reservation set invalidation or timeout or
interrupt). Therefore, we just pretend that an inter
On Wed, Jun 01, 2022 at 11:08:29PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Add an asynchronous version of i2c_send() that requires the slave to
> explicitly acknowledge on the bus with i2c_ack().
>
> The current master must use the new i2c_start_send_async() to indicate
> that it wan
On Wed, Jun 01, 2022 at 11:08:28PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Allow slaves to master the bus by registering a bottom halve. If the bus
> is busy, the bottom halve is queued up. When a slave has succesfully
^ half
> mastered the bus, the bottom halve
Am 30. Mai 2022 19:58:37 UTC schrieb Mark Cave-Ayland
:
>On 29/05/2022 19:05, Bernhard Beschow wrote:
>
>> On Sun, May 29, 2022 at 11:25 AM Mark Cave-Ayland <
>> mark.cave-ayl...@ilande.co.uk> wrote:
>>
>>> On 28/05/2022 20:20, Bernhard Beschow wrote:
>>>
Just like the real hardware, create
Am 30. Mai 2022 11:38:30 UTC schrieb "Philippe Mathieu-Daudé" :
>On 28/5/22 21:20, Bernhard Beschow wrote:
>> Found-by: Peter Maydell
>
>I suppose you refer to this thread:
>https://lore.kernel.org/qemu-devel/CAFEAcA_y69=iXMH75dHeNkxMa038Z7Xk63GW9fdcAFHJSWS=s...@mail.gmail.com/
Yes, correct.
>I'
Am 30. Mai 2022 13:19:33 UTC schrieb "Philippe Mathieu-Daudé" :
>On 29/5/22 20:09, Bernhard Beschow wrote:
>> On Sun, May 29, 2022 at 11:05 AM Mark Cave-Ayland
>> mailto:mark.cave-ayl...@ilande.co.uk>> wrote:
>>
>> On 28/05/2022 20:20, Bernhard Beschow wrote:
>>
>> > TYPE_PIIX3_PCI_DEVI
On Thu, Jun 2, 2022 at 3:26 AM wrote:
>
> From: Frederic Konrad
>
> The core and the vblend registers size are wrong, they should respectively be
> 0x3B0 and 0x1E0 according to:
>
> https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html.
>
> Let's fix that and u
On 6/1/22 11:05, Alex Bennée wrote:
The following changes since commit 7077fcb9b68f058809c9dd9fd1dacae1881e886c:
Merge tag 'vmbus-maint-20220530' of https://github.com/maciejsszmigiero/qemu
into staging (2022-05-30 12:40:36 -0700)
are available in the Git repository at:
https://github.c
From: Klaus Jensen
Add an asynchronous version of i2c_send() that requires the slave to
explicitly acknowledge on the bus with i2c_ack().
The current master must use the new i2c_start_send_async() to indicate
that it wants to do an asynchronous transfer. This allows the i2c core
to check if the
On Thu, Jun 2, 2022 at 3:29 AM wrote:
>
> From: Frederic Konrad
>
> When the display port has been initially implemented the device driver wasn't
> using interrupts. Now that the display port driver waits for vblank interrupt
> it has been noticed that the irq mapping is wrong. So use the value
From: Klaus Jensen
Add an example I2C device to demonstrate how a slave may master the bus
and send data asynchronously to another slave.
The device will echo whatever it is sent to the device identified by the
first byte received.
Signed-off-by: Klaus Jensen
---
hw/misc/i2c-echo.c | 162 +++
From: Klaus Jensen
Allow slaves to master the bus by registering a bottom halve. If the bus
is busy, the bottom halve is queued up. When a slave has succesfully
mastered the bus, the bottom halve is scheduled.
Signed-off-by: Klaus Jensen
---
hw/i2c/core.c| 34 ++
From: Klaus Jensen
Build a single string instead of having several parameters on the trace
event.
Suggested-by: Cédric Le Goater
Signed-off-by: Klaus Jensen
---
hw/i2c/aspeed_i2c.c | 55 +++--
hw/i2c/trace-events | 2 +-
2 files changed, 44 insertions(
From: Klaus Jensen
Add support for writing and reading the device address register in old
register mode.
Signed-off-by: Klaus Jensen
---
hw/i2c/aspeed_i2c.c | 5 +++--
include/hw/i2c/aspeed_i2c.h | 8
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/aspee
From: Klaus Jensen
Add slave mode functionality for the Aspeed I2C controller in old
register mode. This is implemented by realizing an I2C slave device
owned by the I2C controller and attached to its own bus.
The I2C slave device only implements asynchronous sends on the bus, so
slaves not supp
From: Klaus Jensen
Hi all,
This RFC series adds I2C "slave mode" support for the Aspeed I2C
controller as well as the necessary infrastructure in the i2c core to
support this.
v2 changes
~~
I finally got around to working on this again. I'm sorry for not
bringing a v2 to the table earli
On 4/11/22 10:47, Anthony PERARD via wrote:
From: Anthony PERARD
At the moment, there doesn't seems to be any way to know that QEMU
made modification to the command buffer. This is potentially an issue
on Xen while migrating a guest, as modification to the buffer after
the migration as start
From: Xiangyi Meng
count should be the second parameter of x86_cpu_get_supported_cpuid.
If not, when guest is querying 0x12H related CPUID leafs, any of the
four registers will possibly be zero, incurring some strange behaviors, like,
virtual SGX is enabled by the user but the guest OS reports SG
On Jun 1, 2022, at 2:30 PM, Alex Williamson
mailto:alex.william...@redhat.com>> wrote:
On Wed, 1 Jun 2022 18:01:39 +
Jag Raman mailto:jag.ra...@oracle.com>> wrote:
On Jun 1, 2022, at 1:26 PM, Alex Williamson
mailto:alex.william...@redhat.com>> wrote:
On Wed, 1 Jun 2022 17:00:54 +
Jag
From: Paolo Bonzini
In preparation for handling more binaries than just cc, handle
the case of "probe_target_compiler $cpu" directly in the function,
setting the target_* variables based on the ones that are used to
build QEMU. The clang check also needs to be moved after this
fallback.
Signed-
From: Paolo Bonzini
Ensure that the pc-bios/optionrom and pc-bios/s390-ccw directory
exist at the time when we'll write out the compiler configuration
for them.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Message-Id: <20220517092616.1272238-13-pbonz...@redhat.com>
Signed-off-by
From: Paolo Bonzini
TCG tests need both QEMU and firmware to be built, so do "ninja all" before
trying to run them.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Message-Id: <20220517092616.1272238-5-pbonz...@redhat.com>
Signed-off-by: Alex Bennée
Message-Id: <20220527153603.887
On Wed, 1 Jun 2022 18:01:39 +
Jag Raman wrote:
> > On Jun 1, 2022, at 1:26 PM, Alex Williamson
> > wrote:
> >
> > On Wed, 1 Jun 2022 17:00:54 +
> > Jag Raman wrote:
> >>
> >> Hi Alex,
> >>
> >> Just to add some more detail, the emulated PCI device in QEMU presently
> >> maintains
From: Daniel P. Berrangé
This folds the static checks into using the base job
template rules, introducing one new variable
- QEMU_JOB_ONLY_FORKS - a job that should never run
on an upstream pipeline. The information it reports
is only applicable to contributors in a pre-submission
scen
From: Paolo Bonzini
The arm compiler can be used for armeb, and the sparc64 compiler
can be used for sparc.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Message-Id: <20220517092616.1272238-9-pbonz...@redhat.com>
Signed-off-by: Alex Bennée
Message-Id: <20220527153603.887929-20-a
There where some broken links so fix those up with proper references
to the devel docs. I also did a little light copy-editing to reflect
the current state and broke up a paragraph to reduce the "wall of
text" effect.
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Message-Id: <202205
From: Paolo Bonzini
Firmware builds require paths to all the binutils; it is not enough to
use only cc, or even as/ld as in the case of tests/tcg/tricore.
Adjust the cross-compiler configurator to detect also ar, nm, objcopy,
ranlib and strip.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo
From: Daniel P. Berrangé
This folds the Cirrus job rules into the base job
template, introducing two new variables
- QEMU_JOB_CIRRUS - identifies the job as making
use of Cirrus CI via cirrus-run
- QEMU_JOB_OPTIONAL - identifies the job as one
that is not run by default, primarily d
From: Daniel P. Berrangé
To preserve CI shared runner credits we don't want to run
pipelines on every push.
This sets up the config so that pipelines are never created
for contributors by default. To override this the QEMU_CI
variable can be set to a non-zero value. If set to 1, the
pipeline wil
From: Paolo Bonzini
While container-based cross compilers are not supported, this already makes
it possible to build x86 optionroms on any machine that has an installation
of GCC and binutils for 32- or 64-bit x86.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Message-Id: <202205
From: Paolo Bonzini
While container-based cross compilers are not supported, this already
makes it possible to build vof on any machine that has an installation
of GCC and binutils for 32- or 64-bit PowerPC.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Message-Id: <2022051709261
From: Paolo Bonzini
While container-based cross compilers are not supported, this already makes
it possible to build s390-ccw on any machine that has s390x GCC and binutils
installed.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Message-Id: <20220517092616.1272238-14-pbonz...@re
From: Paolo Bonzini
tests/tcg/configure.sh has a complicated story.
In the beginning its code ran as part of the creation of config-target.mak
files, and that is where it placed the information on the target compiler.
However, probing for the buildability of TCG tests required multiple
inclusion
From: Daniel P. Berrangé
Currently job rules are spread across the various templates
and jobs, making it hard to understand exactly what runs in
what scenario. This leads to inconsistency in the rules and
increased maint burden.
The intent is that we introduce a common '.base_job_template'
which
The one minor wrinkle we need to account for is the netmap support
still requires building from source. We also include cscope and GNU
global as they are used in one of the builds.
Signed-off-by: Alex Bennée
Cc: Philippe Mathieu-Daudé
Cc: Luigi Rizzo
Cc: Giuseppe Lettieri
Cc: Vincenzo Maffione
From: Paolo Bonzini
The only compiler variable that is still needed is $(CC), for
contrib/plugins/Makefile. All firmware builds have their own
config-host.mak file.
Signed-off-by: Paolo Bonzini
Message-Id: <20220517092616.1272238-17-pbonz...@redhat.com>
Signed-off-by: Alex Bennée
Message-Id:
From: Paolo Bonzini
Fix an incorrect "@@:" and move "-d keepdepfile" to the NINJAFLAGS variable.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Message-Id: <20220517092616.1272238-3-pbonz...@redhat.com>
Signed-off-by: Alex Bennée
Message-Id: <20220527153603.887929-14-alex.ben...@
From: Daniel P. Berrangé
This converts the main build and container jobs to use the
base job rules, defining the following new variables
- QEMU_JOB_SKIPPED - jobs that are known to be currently
broken and should not be run. Can still be manually
launched if desired.
- QEMU_JOB_AVOCADO -
From: Paolo Bonzini
We do not want v8plus for pure sparc32, as the difference with the V8 ABI
are only meaningful on 64-bit CPUs suh as ultrasparc; supersparc is the
best CPU to use for 32-bit.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Message-Id: <20220517092616.1272238-7-pb
Use lcitool to update debian-mips64el-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220527153603.887929-10-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml
index 1a533e6fc0..41
Use lcitool to update debian-ppc64el-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220527153603.887929-11-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml
index 411dc06bf8..147
From: Paolo Bonzini
Let any make target specify ninja goals that needs to be built for it
(though selecting the goals is _not_ recursive on depending targets)
instead of having a custom mechanism only for "make check" and "make
bench".
Signed-off-by: Paolo Bonzini
Message-Id: <20220517092616.12
From: Paolo Bonzini
Just hardcode $(CC) -E, it should be enough.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Message-Id: <20220517092616.1272238-2-pbonz...@redhat.com>
Signed-off-by: Alex Bennée
Message-Id: <20220527153603.887929-13-alex.ben...@linaro.org>
diff --git a/config
3 space indentation snuck into the initial commit. Clean it up before
we let it get established. I've also:
- removed unused os import
- added double lines between functions
- added some comments and grouped and sorted the generation stanzas
My lint tool is also recommending using f-strings
Use lcitool to update debian-armel-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220527153603.887929-8-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml
index 4d1830f3fc..caef7d
Use lcitool to update debian-mipsel-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220527153603.887929-9-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml
index caef7decf4..1a533
From: Thomas Huth
The "riscv64-debian-cross-container" job does not depend on any other
container job from the first stage, so we can move it to the first
stage, too.
The "riscv64-debian-test-cross-container" job needs the debian11
container, so we should add a proper "needs:" statement here.
S
From: Paolo Bonzini
Also in preparation for handling more binaries from the cross binutils,
support an option --cross-prefix-ARCH. All cross_cc_* defaults are
replaced with cross_prefix_*; the cross_cc_* fallbacks are extended
to the cross-compilation prefix, but the compiler fallbacks remain
as
The recent refactoring of configure.sh dropped a number of variables
we relied on for printing out information. Make it simpler.
Fixes: eebf199c09 (tests/tcg: invoke Makefile.target directly from QEMU's
makefile)
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20220527153
Use lcitool to update debian-armhf-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220527153603.887929-7-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml
index ac15fce9b6..4d1830
From: Paolo Bonzini
This is useful because pc-bios/meson.build already has a list of all ROM
files, and thus does not need to use wildcards. The problems with
wildcards are mentioned above the definition of the LINKS variable,
but then the recommendation is disattended.
Reviewed-by: Richard Hen
The following changes since commit 7077fcb9b68f058809c9dd9fd1dacae1881e886c:
Merge tag 'vmbus-maint-20220530' of https://github.com/maciejsszmigiero/qemu
into staging (2022-05-30 12:40:36 -0700)
are available in the Git repository at:
https://github.com/stsquad/qemu.git tags/pull-testing-ne
From: Marc-André Lureau
This allows the gitlab UI to show the test results in different ways,
see doc:
https://docs.gitlab.com/ee/ci/unit_test_reports.html#how-it-works
Previous we only reports avocado test results (.avocado_test_job_template),
with this change, the qemu/meson tests are also
From: Thomas Huth
The cross-i386-tci job uses the fedora-i386-cross image, so we should make sure
that the corresponding job that builds it (the i386-fedora-cross-container job)
has finished before we start the TCI job.
Signed-off-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <202
> On Jun 1, 2022, at 1:26 PM, Alex Williamson
> wrote:
>
> On Wed, 1 Jun 2022 17:00:54 +
> Jag Raman wrote:
>>
>> Hi Alex,
>>
>> Just to add some more detail, the emulated PCI device in QEMU presently
>> maintains a MSIx table (PCIDevice->msix_table) and Pending Bit Array. In the
>> pre
On Wed, 1 Jun 2022 17:09:25 +
"Dong, Eddie" wrote:
> > -Original Message-
> > From: Qemu-devel > bounces+eddie.dong=intel@nongnu.org> On Behalf Of Alex Williamson
> > On Tue, 24 May 2022 14:18:35 +0800
> > Lei Rao wrote:
> > > This proposal adopts a plugin mechanism (an exampl
On Wed, 1 Jun 2022 17:00:54 +
Jag Raman wrote:
>
> Hi Alex,
>
> Just to add some more detail, the emulated PCI device in QEMU presently
> maintains a MSIx table (PCIDevice->msix_table) and Pending Bit Array. In the
> present VFIO PCI device implementation, QEMU leverages the same
> MSIx tabl
From: Sai Pavan Boddu
Fix interrupt disable logic. Mask value 1 indicates that interrupts are
disabled.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Frederic Konrad
---
hw/display/xlnx_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw
From: Frederic Konrad
When the display port has been initially implemented the device driver wasn't
using interrupts. Now that the display port driver waits for vblank interrupt
it has been noticed that the irq mapping is wrong. So use the value from the
linux device tree and the ultrascale+ re
From: Sai Pavan Boddu
Add a periodic timer which raises vblank at a frequency of 30Hz.
Signed-off-by: Sai Pavan Boddu
Signed-off-by: Edgar E. Iglesias
Changes by fkonrad:
- Switched to transaction-based ptimer API.
- Added the DP_INT_VBLNK_START macro.
Signed-off-by: Frederic Konrad
---
From: Frederic Konrad
The core and the vblend registers size are wrong, they should respectively be
0x3B0 and 0x1E0 according to:
https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html.
Let's fix that and use macros when creating the mmio region.
Fixes: 58ac48
From: Frederic Konrad
Hi,
This patch set fixes some issues with the DisplayPort for the ZCU102:
The first patch fixes the wrong register size and thus the risk of register
overflow.
The three other one add a vblank interrupt required by the linux driver:
- When using the VNC graphic backend
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