On 08/06/2022 18.06, Daniel P. Berrangé wrote:
The GitLab variable comparisons don't have shell like semantics where
an unset variable compares equal to empty string. We need to explicitly
test against 'null' to detect an unset variable.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/base
On 09/06/2022 05.13, Iris Chen wrote:
Signed-off-by: Iris Chen
---
Include the tests in a separate patch. Using qtest_set_irq_in() as per review.
tests/qtest/aspeed_smc-test.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test
Hi Josh :
I have gone ahead and upgraded the acpica. Changes need to be reviewed
and bits need to be tested more. However, here are the changes:
In the acpica submodule:
https://github.com/biosbits/acpica/pull/1
in the main top level bits repo:
https://github.com/ani-sinha/bits/compare/master...
On Wed, Jun 8, 2022 at 4:14 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> There are currently two types of RISC-V CPUs:
> - Generic CPUs (base or any) that allow complete custimisation
> - "Named" CPUs that match existing hardware
>
> Users can use the base CPUs to custimise the ext
This patch adds RISC-V Zihintpause support. The extension is set to be enabled
by default and opcode has been added to insn32.decode.
Added trans_pause for TCG to mainly to break reservation and exit the TB.
The change can also be found in:
https://github.com/dlu42/qemu/tree/zihintpause_support_v
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner
Signed-off-by: Dao Lu
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++-
t
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 3 +
target/riscv/cpu_helper.c | 231 +
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v5 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required hyperviso
The riscv_cpu_realize() sets priv spec version to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.
Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.
To fix this issue, we set latest priv
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which is always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the
CSR ops.")
Signed-off-by: Anup Patel
Reviewed
On Wed, Jun 8, 2022 at 10:23 PM Richard Henderson
wrote:
>
> On 6/8/22 09:14, Anup Patel wrote:
> > +struct isa_ext_data isa_edata_arr[] = {
>
> static const?
Using const is fine but we can't use "static const" because
the "struct isa_ext_data" has a pointer to ext_xyz which
is different for
Signed-off-by: Iris Chen
---
Include the tests in a separate patch. Using qtest_set_irq_in() as per review.
tests/qtest/aspeed_smc-test.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index c
From: Iris Chen
Signed-off-by: Iris Chen
---
Addressed all comments from V1. The biggest change: removed
object_class_property_add.
hw/block/m25p80.c | 37 +++
tests/qtest/aspeed_smc-test.c | 2 ++
2 files changed, 39 insertions(+)
diff --git a/hw
Add linux-user emulation introduction
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/README | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/README b/target/loongarch/README
index 4dcd0f1682.
This patch adds loongarch64 linux-user default configs file.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
configs/targets/loongarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 configs/targets/loongarch64-linux-user.ma
We should disable '__BITS_PER_LONG' at [1] before run gensyscalls.sh
[1] arch/loongarch/include/uapi/asm/bitsperlong.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/loongarch64/syscall_nr.h | 312 ++
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c| 54 +
linux-user/loongarch64/target_elf.h | 12 +++
2 files changed, 66 insertions(+)
create mode 1
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
- target_resource.h
- target_structs.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/loongarch64/sockbits.h | 11 ++
Some functions and member of the structure are different with softmmu-mode
So we need adjust them to support user-mode.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/cpu.c| 22 ++--
target/loongarch/cpu.h| 6 ++
Hi All,
This series add support linux-user emulation.
As the LoongArch kernel had merged into 5.19-rc1,
you can see the latest kernel at https://kernel.org
Need review patches:
0002-linux-user-Add-LoongArch-signal-support.patch
0008-target-loongarch-Adjust-functions-and-structure-to-s.patch
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
linux-user/loongarch64/cpu_loop.c | 93 +
linux-user/loongarch64/target_cpu.h | 34 +++
2 files changed, 127 insertions(+)
create mode 100644 linux-user/loongarch64/cpu
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
scripts/qemu-binfmt-conf.sh | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 9cb723f443..1f4e2cd19d 100755
--- a/script
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/signal.c| 194 +
linux-user/loongarch64/target_signal.h | 13 ++
2 files changed, 207 insertions(+)
create mode 100644 linux-user/loongarch64/signal.c
create mode 100644 linux-user/
ioport access is required for VESA BIOS Extensions (VBE). Since ioport
access is not forwarded over PCI(e) bridges, graphics adapters must be
attached directly to the Root Complex in order for the BIOS to provide
VBE modes. I'm very grateful to Gerd Hoffmann for explaining this on
the SeaBIOS mai
> On Jun 9, 2022, at 4:55 AM, Klaus Jensen wrote:
>
> On Jun 8 09:36, Jinhao Fan wrote:
>> Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3)
>> and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13
>> in NVMe Spec 1.3). For queues created before the Door
On Thu, Jun 9, 2022 at 12:20 AM Anup Patel wrote:
>
> We should disable extensions in riscv_cpu_realize() if minimum required
> priv spec version is not satisfied. This also ensures that machines with
> priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
> extensions.
>
> Fixes
On Thu, Jun 9, 2022 at 12:15 AM Anup Patel wrote:
>
> The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
> implementation that don't want to implement can simply have a dummy
> mcountinhibit which always zero.
which is always
>
> Fixes: a4b2fa433125 ("target/riscv: Introduce p
On Thu, Jun 9, 2022 at 12:15 AM Anup Patel wrote:
>
> The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
typo: version
> when "env->priv_ver == 0" (i.e. default v1.10) because the enum
> value of priv spec v1.10 is zero.
>
> Due to above issue, the sifive_u machine will see priv s
When running with accel=kvm, the extensions are actually told by
KVM, so let's skip the parsing logic from properties for KVM.
Signed-off-by: Bin Meng
---
target/riscv/cpu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
env->misa_ext_mask might be set to the same value of env->misa_ext
in riscv_cpu_realize() based on given properties, but it may differ
from what KVM tells us.
Let's set the correct env->misa_ext_mask in kvm_arch_init_vcpu().
Signed-off-by: Bin Meng
---
target/riscv/kvm.c | 2 +-
1 file changed
env->misa_mxl was already set in the RISC-V cpu init routine, and
validated at the beginning of riscv_cpu_realize(). There is no need
to do a redundant initialization later.
Signed-off-by: Bin Meng
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target
Hi, Michael
QEMU side was reviewed by Gonglei a week ago. To avoid this to be
ignored, PING!
On 5/31/22 20:08, Gonglei (Arei) wrote:
-Original Message-
From: zhenwei pi [mailto:pizhen...@bytedance.com]
Sent: Tuesday, May 31, 2022 9:48 AM
To: Gonglei (Arei)
Cc: qemu-devel@nongnu.or
The edk2 commit 4de8d61bcec ("OvmfPkg: rework TPM configuration") switched
the x86_64 build from using TPM_ENABLE to TPM2_ENABLE and TPM1_ENABLE to
be similar to the ARM build. Adapt the QEMU edk2 Makefile to build with
TPM2_ENABLE. QEMU v7.0.0 had lost the TPM 2 support in edk2 and this
restores i
在 2022/6/9 7:10, Michael S. Tsirkin 写道:
On Sat, May 14, 2022 at 12:11:07PM +0800, Longpeng(Mike) wrote:
From: Longpeng
Supports vdpa-dev-pci, we can use the device as follow:
-device vhost-vdpa-device-pci,vhostdev=/dev/vhost-vdpa-X
Reviewed-by: Stefano Garzarella
Signed-off-by: Longpeng
From: Alistair Francis
When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().
This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.
Resolves: https://gitla
On Sat, May 14, 2022 at 12:11:07PM +0800, Longpeng(Mike) wrote:
> From: Longpeng
>
> Supports vdpa-dev-pci, we can use the device as follow:
>
> -device vhost-vdpa-device-pci,vhostdev=/dev/vhost-vdpa-X
>
> Reviewed-by: Stefano Garzarella
> Signed-off-by: Longpeng
Build fails:
FAILED: libqe
Le 08/06/2022 à 21:05, Richard Henderson a écrit :
On 6/8/22 11:08, Laurent Vivier wrote:
Le 08/06/2022 à 16:53, Richard Henderson a écrit :
On 6/8/22 02:36, Laurent Vivier wrote:
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
Based-on: <20220607204557.658541-1-richard.hender...@linaro.or
On Mon, Jun 06, 2022 at 10:51:23AM -0300, Daniel Henrique Barboza wrote:
> Michael,
>
>
> I'll queue this patch with the commit msg proposed by Zoltan as follows:
>
>
> Author: Michael S. Tsirkin
> Date: Thu May 26 18:43:43 2022 -0400
>
> ppc: fix boot with sam460ex
> Recent changes
Implement do_bsd_{read,pread,readv,preadv}. Connect them to the system
call table.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 79 +++
bsd-user/freebsd/os-syscall.c | 28 +
2 file
Implement write, writev, pwrite and pwritev and connect them to the
system call dispatch routine.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 84 +++
bsd-user/freebsd/os-syscall.c | 22 ++
lock_iovec will lock an I/O vec and the memory to which it refers and
create a iovec in the host space that refers to it, with full error
unwinding. Add helper_iovec_unlock to unlock the partially locked iovec
in case there's an error. The code will be used in iovec_unlock when
that is committed.
Implement the exit system call. Bring in bsd-proc.h to contain all the
process system call implementation and helper routines.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/bsd-proc.h | 43 +++
Releases the references to the iovec created by lock_iovec.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-syscall.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/freebsd/os-syscall.c b/bsd-user/freebsd/os-syscall.c
index 67851937a8f..52093d479d8 100644
--- a/b
This series of patches continues the effort to get system calls working
upstream. This series was cleaved off a prior series to give me time to rework
based on the feedback from the first time I posted these.
o bsd-user/freebsd/os-syscall.c: lock_iovec
I rewored to use g_try_new, as well as
Add in the tracing and this system call not implemented boilerplate. Do
this by moving the guts of do_freebsd_syscall to freebsd_syscall. Put
the tracing in the wrapper function. Since freebsd_syscall is a
singleton static function, it will almost certainly be inlined. Fix
comments that referred to
Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
part of the flushing mechanism got missing: incrementing zero_copy_queued.
Without that, the flushing interface becomes a no-op, and there is no
guarantee the buffer is really sent.
This can go as bad as causing a corruption
During implementation of MSG_ZEROCOPY feature, a lot of #ifdefs were
introduced, particularly at qio_channel_socket_writev().
Rewrite some of those changes so it's easier to read.
...
Signed-off-by: Leonardo Bras
---
io/chan
On Wed, Jun 8, 2022 at 5:55 PM Peter Xu wrote:
>
> On Wed, Jun 08, 2022 at 04:26:10PM -0400, Peter Xu wrote:
> > On Wed, Jun 08, 2022 at 03:18:09PM -0300, Leonardo Bras wrote:
> > > Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
> > > part of the flushing mechanism got mi
On Jun 8 09:36, Jinhao Fan wrote:
> Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3)
> and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13
> in NVMe Spec 1.3). For queues created before the Doorbell Buffer Config
> command, the nvme_dbbuf_config function
On Wed, Jun 08, 2022 at 04:26:10PM -0400, Peter Xu wrote:
> On Wed, Jun 08, 2022 at 03:18:09PM -0300, Leonardo Bras wrote:
> > Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
> > part of the flushing mechanism got missing: incrementing zero_copy_queued.
> >
> > Without tha
Hello Daniel,
On Wed, Jun 8, 2022 at 3:46 PM Daniel P. Berrangé wrote:
>
> On Wed, Jun 08, 2022 at 03:18:09PM -0300, Leonardo Bras wrote:
> > Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
> > part of the flushing mechanism got missing: incrementing zero_copy_queued.
> >
On 6/8/22 12:05, Richard Henderson wrote:
But what is the use case of semihosting on m68k?
Is there a kernel implementation available for that?
Not that I'm aware of. Do you want to remove it entirely instead?
Leaving it as-is should not be an option...
Oh, duh. The "kernel" implementation
On Wed, Jun 08, 2022 at 03:18:09PM -0300, Leonardo Bras wrote:
> Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
> part of the flushing mechanism got missing: incrementing zero_copy_queued.
>
> Without that, the flushing interface becomes a no-op, and there is no
> garante
On Wed, Jun 08, 2022 at 03:14:36PM -0300, Leonardo Bras Soares Passos wrote:
> On Wed, Jun 8, 2022 at 8:41 AM Peter Xu wrote:
> >
> > On Wed, Jun 08, 2022 at 02:37:28AM -0300, Leonardo Bras Soares Passos wrote:
> > > (1) is not an option, as the interface currently uses ret=1 to make
> > > sure MS
On Wed, Jun 08, 2022 at 07:46:43PM +0100, Daniel P. Berrangé wrote:
> On Wed, Jun 08, 2022 at 03:18:09PM -0300, Leonardo Bras wrote:
> > Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
> > part of the flushing mechanism got missing: incrementing zero_copy_queued.
> >
> > W
On 6/7/22 03:44, Cédric Le Goater wrote:
Also, the comment seems wrong to me. The qom parenting doesn't matter when building the device tree.
it does. See pnv_dt_xscom()
And this is the root cause of many headaches for user-created devices.
Could it be done differently ?
Just tried to do
On Tue, Jun 7, 2022 at 8:12 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > The callback allows SVQ users to know the VirtQueue requests and
> > responses. QEMU can use this to synchronize virtio device model state,
> > allowing to migrate it with minimum changes to the migrati
...
> With this patch series, it's actually even not possible for userspace VMM
> to allocate private page by a direct write, it's basically unmapped from
> there. If it really wants to, it should so something special, by intention,
> that's basically the conversion, which we should allow.
>
A VM
On Wed, Jun 8, 2022 at 7:51 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > Control virtqueue is used by networking device for accepting various
> > commands from the driver. It's a must to support multiqueue and other
> > configurations.
> >
> > Shadow VirtQueue (SVQ) already
The following changes since commit 9b1f58854959c5a9bdb347e3e04c252ab7fc9ef5:
Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu into staging
(2022-06-06 16:16:01 -0700)
are available in the Git repository at:
https://gitlab.com/alex.williamson/qemu.git tags/vfio-updates-2022060
From: Eric Auger
851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
warning") removed the warning on vfio_listener_region_add() path.
However the same warning also hits on region_del path. Let's remove
it and reword the dynamic trace as this can be called on both
map and unmap pa
On Wed, Jun 8, 2022 at 6:25 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > CVQ needs to be in its own group, not shared with any data vq. Enable
> > the checking of it here, before introducing address space id concepts.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> > inclu
On 6/8/22 11:08, Laurent Vivier wrote:
Le 08/06/2022 à 16:53, Richard Henderson a écrit :
On 6/8/22 02:36, Laurent Vivier wrote:
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
Based-on: <20220607204557.658541-1-richard.hender...@linaro.org>
("[PATCH v4 00/53] semihosting cleanup")
Changes
On Wed, Jun 8, 2022 at 6:21 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > To restore the device in the destination of a live migration we send the
> > commands through control virtqueue. For a device to read CVQ it must
> > have received DRIVER_OK status bit.
> >
> > However
On Wed, Jun 8, 2022 at 6:19 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > Signed-off-by: Eugenio Pérez
> > ---
>
>
> It's better to use the helpers in scripts/ and mentioned to which
> version is this synced.
>
Right, I should have written somewhere this was in the meantime
On Wed, Jun 8, 2022 at 6:14 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > Enable SVQ to not to forward the descriptor translating its address to
> > qemu's IOVA but copying to a region outside of the guest.
> >
> > Virtio-net control VQ will use this mode, so we don't need to
On Wed, Jun 08, 2022 at 03:18:09PM -0300, Leonardo Bras wrote:
> Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
> part of the flushing mechanism got missing: incrementing zero_copy_queued.
>
> Without that, the flushing interface becomes a no-op, and there is no
> garante
Please ignore, I have missed the commit message, will resend a v3.
Sorry about that.
Dao
On Tue, Jun 7, 2022 at 8:44 PM Dao Lu wrote:
>
> Tested-by: Heiko Stuebner
> Signed-off-by: Dao Lu
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
part of the flushing mechanism got missing: incrementing zero_copy_queued.
Without that, the flushing interface becomes a no-op, and there is no
garantee the buffer is really sent.
This can go as bad as causing a corruption
On Wed, Jun 8, 2022 at 8:41 AM Peter Xu wrote:
>
> On Wed, Jun 08, 2022 at 02:37:28AM -0300, Leonardo Bras Soares Passos wrote:
> > (1) is not an option, as the interface currently uses ret=1 to make
> > sure MSG_ZEROCOPY is getting used,
> > I added that so the user of qio_channel can switch off
Le 08/06/2022 à 16:53, Richard Henderson a écrit :
On 6/8/22 02:36, Laurent Vivier wrote:
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
Based-on: <20220607204557.658541-1-richard.hender...@linaro.org>
("[PATCH v4 00/53] semihosting cleanup")
Changes for v4:
* Split out of v2.
* Conv
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> The QEMUFile 'save_hook' callback has a 'size_t size' parameter.
>
> The RDMA impl of this has logic that takes different actions
> depending on whether the value is zero or non-zero. It has
> commented out logic that would have taken further act
On 08/06/2022 12:54, Paolo Bonzini wrote:
> On 6/8/22 16:21, Matheus Kowalczuk Ferst wrote:
>> Also, we will not have this error at configure-time anymore, but I
>> suppose that *BSD users will identify the problem if they try to build
>> with non-gnu make.
>
> Yeah, my guess was that "try ./confi
Richard Henderson writes:
> The err parameter is non-zero if and only if an error occured.
> Use this instead of ret == -1 for determining if we need to
> update the saved errno.
>
> This fixes the errno setting of SYS_ISTTY, which returns 0 on
> error, not -1.
>
> Signed-off-by: Richard Hender
* Peter Xu (pet...@redhat.com) wrote:
> Allow cpu_synchronize_all_post_init() to fail with an errp when it's set.
> Modify both precopy and postcopy to try to detect such error.
>
> Signed-off-by: Peter Xu
> ---
> hw/core/machine.c | 2 +-
> include/sysemu/cpus.h | 2 +-
> migration/savevm
On 6/8/22 09:06, Daniel P. Berrangé wrote:
The GitLab variable comparisons don't have shell like semantics where
an unset variable compares equal to empty string. We need to explicitly
test against 'null' to detect an unset variable.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/base.yml
On 6/8/22 09:14, Anup Patel wrote:
+struct isa_ext_data isa_edata_arr[] = {
static const?
r~
On Tue, Jun 7, 2022 at 7:02 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/7/22 16:35, Warner Losh wrote:
> >
> >
> >> On Jun 7, 2022, at 3:23 PM, Richard Henderson <
> richard.hender...@linaro.org> wrote:
> >>
> >> On 6/7/22 14:51, Warner Losh wrote:
> >>> void unlock_iove
On Tue, Jun 7, 2022 at 8:05 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > Introduce the control virtqueue support for vDPA shadow virtqueue. This
> > is needed for advanced networking features like multiqueue.
> >
> > To demonstrate command handling, VIRTIO_NET_F_CTRL_MACADDR
On Tue, Jun 7, 2022 at 8:13 AM Jason Wang wrote:
>
>
> 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > This allows external vhost-net devices to modify the state of the
> > VirtIO device model once vhost-vdpa device has acknowledge the control
> > commands.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
>
On 07/06/2022 07:49, Paolo Bonzini wrote:
> INSTALL and LIBTOOL are not used anymore, but OBJCFLAGS is new and
> was not listed.
>
> Signed-off-by: Paolo Bonzini
> ---
> configure | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/configure b/configure
> index f35847c3
* Peter Xu (pet...@redhat.com) wrote:
> Four tests are added for preempt mode:
>
> - Postcopy plain
> - Postcopy recovery
> - Postcopy tls
> - Postcopy tls+recovery
>
> Signed-off-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
> ---
> tests/qtest/migration-test.c | 58 +
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> On 6/8/22 18:01, Dr. David Alan Gilbert wrote:
> > 'Find descriptors for 'target', either that have already been read or
> > query 'stats_fd' to read them from kvm'
>
> /*
> * Return the descriptors for 'target', that either have already been
> *
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 3 +
target/riscv/cpu_helper.c | 231 +
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v4 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required hyperviso
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
the CSR ops.")
Signed-off-by: Anup Patel
Reviewed-by:
The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.
Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.
To fix this issue, we set latest priv s
On 6/8/22 18:01, Dr. David Alan Gilbert wrote:
'Find descriptors for 'target', either that have already been read or
query 'stats_fd' to read them from kvm'
/*
* Return the descriptors for 'target', that either have already been
* read or are retrieved from 'stats_fd'.
*/
Paolo
Richard Henderson writes:
> We are not currently bounding the search to the 1024 bytes
> that we allocated, possibly overrunning the buffer.
> Use softmmu_strlen_user to find the length and allocate the
> correct size from the beginning.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard
The GitLab variable comparisons don't have shell like semantics where
an unset variable compares equal to empty string. We need to explicitly
test against 'null' to detect an unset variable.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/base.yml | 2 +-
1 file changed, 1 insertion(+), 1 del
On 6/7/22 4:57 PM, Marc-André Lureau wrote:
> Hi Cole,
>
>
> On Sun, Jun 5, 2022 at 6:46 PM Cole Robinson wrote:
>>
>> Hi Marc-André,
>>
>> dbus-display-test seems flakey. I'm occasionally seeing:
>>
>> ▶ 692/746
>> ERROR:../tests/qtest/dbus-display-test.c:68:test_dbus_display_vm:
>> assertion f
On Wed, Jun 08, 2022 at 08:48:48AM -0700, Richard Henderson wrote:
> Commit 00125414ba1 is not working as intended. E.g.
>
> https://gitlab.com/rth7680/qemu/-/jobs/2558862885
>
> where I have neither CIRRUS_GITHUB_REPO nor CIRRUS_API_TOKEN set, but the
> job tries to run anyway. Then fails, pre
On Fri, Jun 03, 2022 at 10:59:20AM +0200, Gerd Hoffmann wrote:
> The pcie host bridge has no io window on microvm,
> so io reservations will not work.
>
> Signed-off-by: Gerd Hoffmann
I don't much like overriding user like this. We end up users
setting it to silly values and then if we do want t
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> On 6/8/22 16:52, Dr. David Alan Gilbert wrote:
> > > If you mean why not some other source, each source has a different file
> > > descriptor:
> > >
> > > +int stats_fd = kvm_vcpu_ioctl(cpu, KVM_GET_STATS_FD, NULL);
> > >
> > > but the descriptor
On 6/8/22 16:52, Dr. David Alan Gilbert wrote:
If you mean why not some other source, each source has a different file
descriptor:
+int stats_fd = kvm_vcpu_ioctl(cpu, KVM_GET_STATS_FD, NULL);
but the descriptors are consistent every time KVM_GET_STATS_FD is called, so
basically "ident" can
On 6/8/22 16:21, Matheus Kowalczuk Ferst wrote:
On a clean build on FreeBSD with this patch, I got:
../meson.build:3641:0: ERROR: Key MAKE is not in dict
So it seems that we need to remove the use of MAKE in meson.build too.
Oops, yes. That's the typical "forget git commit --amend before sen
On 6/3/22 19:35, Thomas Huth wrote:
On 03/06/2022 19.26, Claudio Fontana wrote:
On 6/3/22 18:42, Thomas Huth wrote:
The disassembly via capstone should be superiour to our old vixl
sources nowadays, so let's finally cut this old disassembler out
of the QEMU source tree.
Signed-off-by: Thomas H
Commit 00125414ba1 is not working as intended. E.g.
https://gitlab.com/rth7680/qemu/-/jobs/2558862885
where I have neither CIRRUS_GITHUB_REPO nor CIRRUS_API_TOKEN set, but the job tries to run
anyway. Then fails, predictably, with "token not defined".
r~
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