The new CPU model mostly inherits features from Icelake-Server, while
adding new features:
- AMX (Advance Matrix eXtensions)
- Bus Lock Debug Exception
and new instructions:
- AVX VNNI (Vector Neural Network Instruction):
- VPDPBUS: Multiply and Add Unsigned and Signed Bytes
-
On 11/08/2022 23.38, Pierre Muller wrote:
I am using qemu to check code generated by Free Pascal compiler
for various CPUs.
Recently, this allowed me to find out that Free Pascal was generating
wrong instructions, leading to SIGBUS errors using qemu-mips.
The same binaries worked
On 11/08/22 19:02, Chao Peng wrote:
> On Thu, Aug 11, 2022 at 01:30:06PM +0200, Gupta, Pankaj wrote:
>>>
>>> While debugging an issue with SEV+UPM, found that fallocate() returns
>>> an error in QEMU which is not handled (EINTR). With the below handling
>>> of EINTR subsequent fallocate()
On 2022/8/11 21:11, Peter Maydell wrote:
The newly added neoverse-n1 CPU has ID register values which indicate
the presence of the Statistical Profiling Extension, because the real
hardware has this feature. QEMU's TCG emulation does not yet
implement SPE, though (not even as a minimal stub
CC: Huacai Chen
On 2022/8/11 下午9:24, Waldemar Brodkorb wrote:
Hi Qemu developers,
I am trying to bootup a loongarch64 Linux kernel in Qemu 7.1.0-rc2.
The problem is I get no output when using following command:
qemu-system-loongarch64 -M virt -nographic -kernel vmlinux
You can find my
On Thu, 2022-08-11 at 10:55 +0800, Bin Meng wrote:
> On Thu, Aug 11, 2022 at 8:58 AM Wilfred Mallawa
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > This patch addresses the coverity issues specified in [1],
> > as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
> > implemented to
With the introduction of the new TCG GICv4, build_madt() is badly broken
as we do not present any GIC Redistributor structure in MADT for GICv4
guests, so that they have no idea about where the Redistributor
register frames are. This fixes a Linux guest crash at boot time with
ACPI enabled and
On 8/11/22 11:02, Daniel P. Berrangé wrote:
[...]
Hmm, I was hoping you could just use SIGKILL to guarantee that this
gets killed off. Is SIGKILL delivered too soon to allow for the
main QEMU process to have exited quickly ?
yes, I tried. qemu has not finished exiting when the signal is
On Tue, Aug 2, 2022 at 4:33 PM Atish Patra wrote:
>
> The latest version of the SBI specification includes a Performance Monitoring
> Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
> various PMU events. The Sscofpmf ('Ss' for Privileged arch and
> Supervisor-level
>
On Wed, 10 Aug 2022 at 19:12, Shivi Fotedar wrote:
>
> Cedric, Joel
>
> Thanks so much for the pointers. This definitely helps. We will get back to
> you with any further questions once we have looked them over.
Great! We look forward to your contributions. I am particularly
interested in
On Thu, Aug 11, 2022 at 5:02 AM Atish Patra wrote:
>
> This series implements Sstc extension[1] which was ratified recently.
>
> The first patch is a prepartory patches while PATCH 2 adds stimecmp
> support while PATCH 3 adds vstimecmp support. This series is based on
> on top of upstream commit
From: Wilfred Mallawa
The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies
Dan Williams wrote:
> Bobo WL wrote:
> > Hi Dan,
> >
> > Thanks for your reply!
> >
> > On Mon, Aug 8, 2022 at 11:58 PM Dan Williams
> > wrote:
> > >
> > > What is the output of:
> > >
> > > cxl list -MDTu -d decoder0.0
> > >
> > > ...? It might be the case that mem1 cannot be mapped by
On 11/8/22 15:11, Peter Maydell wrote:
The newly added neoverse-n1 CPU has ID register values which indicate
the presence of the Statistical Profiling Extension, because the real
hardware has this feature. QEMU's TCG emulation does not yet
implement SPE, though (not even as a minimal stub
On 11/8/22 17:14, Alex Bennée wrote:
On some systems the test can hang. At least defining a timeout stops
it from hanging forever.
Signed-off-by: Alex Bennée
---
tests/avocado/machine_aspeed.py | 2 ++
1 file changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 11/8/22 17:14, Alex Bennée wrote:
We removed the ability to do vcpu tcg tracing between:
d9a6bad542 (docs: remove references to TCG tracing)
and
126d4123c5 (tracing: excise the tcg related from tracetool)
but missed a bunch of other code. Lets continue the clean-up by
removing the
On 11/8/22 17:14, Alex Bennée wrote:
Investigating why some BMC models are so slow compared to a plain ARM
virt machines I did some profiling of:
./qemu-system-arm -M romulus-bmc -nic user \
-drive
file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \
-nographic
On 11/8/22 17:14, Alex Bennée wrote:
Before: 35.912 s ± 0.168 s
After: 35.565 s ± 0.087 s
Signed-off-by: Alex Bennée
---
accel/tcg/cputlb.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
s/used/use/ in subject (also previous patch).
Reviewed-by: Philippe
On 11/8/22 17:14, Alex Bennée wrote:
This is a heavily used function so lets avoid the cost of
CPU_GET_CLASS. On the romulus-bmc run it has a modest effect:
Before: 36.812 s ± 0.506 s
After: 35.912 s ± 0.168 s
Signed-off-by: Alex Bennée
---
hw/core/cpu-sysemu.c | 5 ++---
1 file
On 11/8/22 17:14, Alex Bennée wrote:
The class cast checkers are quite expensive and always on (unlike the
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
avoid the overhead of repeatedly checking something which should never
change we cache the CPUClass reference for use in
Cc'ing qemu-windows@ team
On 10/8/22 23:42, Peter Butler wrote:
In x64 win10 I today I d/l QEMU into new directory. Then navigated to
that dir and…
qemu-system-aarch64 -boot d -cdrom
f:\Downloads\debian-11.4.0-arm64-netinst.iso -m 2048
Error message:…libncursesw6.dll not found…
Please
On 9/8/22 11:38, Daniel P. Berrangé wrote:
The property name parameter is ignored when visiting a top
level type, but the obvious typo should be fixed to avoid
confusion. A few indentation issues were tidied up. We
can break out of the loop when finding the RNG device.
Finally, close the temp FD
On 11/8/22 22:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the
On 8/11/2022 7:18 PM, Nikunj A. Dadhania wrote:
On 11/08/22 17:00, Gupta, Pankaj wrote:
This is the v7 of this series which tries to implement the fd-based KVM
guest private memory. The patches are based on latest kvm/queue branch
commit:
b9b71f43683a (kvm/queue) KVM: x86/mmu: Buffer
Define a QEMU special key constant for the tab key and add an entry for
it in the qcode_to_keysym table. This allows tab completion to work again
in the SDL monitor virtual console, which has been broken ever since the
migration from SDL1 to SDL2.
Signed-off-by: Cal Peake
---
Le 11/08/2022 à 23:38, Pierre Muller a écrit :
I am using qemu to check code generated by Free Pascal compiler
for various CPUs.
Recently, this allowed me to find out that Free Pascal was generating
wrong instructions, leading to SIGBUS errors using qemu-mips.
The same binaries
On Thu, 11 Aug 2022, Cédric Le Goater wrote:
Don't drop Ppc4xxDcrDeviceState, that simplifies it a lot. If you don't
want to make mote changes, let me take your series and make a version with
my proposed changes.
Patch 1-7 are already merged. You can grab the rest here :
I am using qemu to check code generated by Free Pascal compiler
for various CPUs.
Recently, this allowed me to find out that Free Pascal was generating
wrong instructions, leading to SIGBUS errors using qemu-mips.
The same binaries worked without troubles on mips test machines,
probably
Le 11/08/2022 à 19:11, Peter Maydell a écrit :
On Thu, 11 Aug 2022 at 14:35, Pierre Muller wrote:
I don't know if this is the right place to submit this report,
but I have a problem with my attempt to check the 7.1.0 release candidate
for linux user powerpc CPU.
I am testing a
Sorry for the top-posting. I noticed that the patch appears really
weird in patchwork [1] where part of the diff is above the PATCH
section. It looks fine in the archives[2] though.
[1]
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the RISC-V
privilege specification[1], ebreak
On Wed, Jul 27, 2022 at 09:33:40PM +0200, Kevin Wolf wrote:
> Am 08.07.2022 um 06:17 hat Stefan Hajnoczi geschrieben:
> > libblkio (https://gitlab.com/libblkio/libblkio/) is a library for
> > high-performance disk I/O. It currently supports io_uring and
> > virtio-blk-vhost-vdpa with additional
On Thu, 11 Aug 2022 at 18:48, Richard Henderson
wrote:
> You can use |= for bool as well. You don't need the short-circuting of ||
> here.
That seems like the kind of thing that -Wbool-operation is likely to
warn about either now or in future, though...
-- PMM
On Wed, Jul 13, 2022 at 02:05:18PM +0200, Hanna Reitz wrote:
> On 08.07.22 06:17, Stefan Hajnoczi wrote:
> > libblkio (https://gitlab.com/libblkio/libblkio/) is a library for
> > high-performance disk I/O. It currently supports io_uring and
> > virtio-blk-vhost-vdpa with additional drivers under
On 8/11/22 18:39, Daniel Henrique Barboza wrote:
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is
On 8/11/22 18:39, Daniel Henrique Barboza wrote:
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-phbs,
On 8/11/22 18:39, Daniel Henrique Barboza wrote:
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by:
On 8/11/22 18:39, Daniel Henrique Barboza wrote:
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that was
Peter Maydell writes:
> On Thu, 11 Aug 2022 at 16:24, Alex Bennée wrote:
>>
>> Hi,
>>
>> I've been collecting a number of small fixes since the tree was
>> frozen. I've been mostly focusing on improving the reliability of the
>> avocado tests and seeing if there are any low hanging fruit for
On 8/11/22 10:16, Peter Maydell wrote:
In pmccntr_op_finish() and pmevcntr_op_finish() we calculate the next
point at which we will get an overflow and need to fire the PMU
interrupt or set the overflow flag. We do this by calculating the
number of nanoseconds to the overflow event and then
On 8/11/22 10:16, Peter Maydell wrote:
The architecture requires that if PMCR.LC is set (for a 64-bit cycle
counter) then PMCR.D (which enables the clock divider so the counter
ticks every 64 cycles rather than every cycle) should be ignored. We
were always honouring PMCR.D; fix the bug so we
On 8/11/22 10:16, Peter Maydell wrote:
Our feature test functions that check the PMU version are named
isar_feature_{aa32,aa64,any}_pmu_8_{1,4}. This doesn't match the
current Arm ARM official feature names, which are FEAT_PMUv3p1 and
FEAT_PMUv3p4. Rename these functions to _pmuv3p1 and
On 8/11/22 10:16, Peter Maydell wrote:
pmu_counter_mask() accidentally returns a value with bits [63:32]
set, because the expression it returns is evaluated as a signed value
that gets sign-extended to 64 bits. Force the whole expression to be
evaluated with 64-bit arithmetic with ULL suffixes.
On 8/11/22 10:16, Peter Maydell wrote:
The logic in pmu_counter_enabled() for handling the 'prohibit event
counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way
that assumes that EL2 is never Secure. This used to be true, but the
architecture now permits Secure EL2, and QEMU can
On 8/11/22 10:16, Peter Maydell wrote:
+static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+/*
+ * Some MDCR_EL3 bits affect whether PMU counters are running:
Typo el3.
Otherwise,
Reviewed-by: Richard Henderson
r~
+
On 11/08/22 19:02, Chao Peng wrote:
> On Thu, Aug 11, 2022 at 01:30:06PM +0200, Gupta, Pankaj wrote:
>>
Test
To test the new functionalities of this patch TDX patchset is needed.
Since TDX patchset has not been merged so I did two kinds of test:
- Regresion
On 8/11/22 10:16, Peter Maydell wrote:
When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
to indicate this. However a missing ULL suffix means that we end up
setting all of bits 63-31. Fix the bug.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 2 +-
1 file
On Thu, 11 Aug 2022 at 18:16, Peter Maydell wrote:
>
> Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
> compliant PMU.
>
> Signed-off-by: Peter Maydell
Oops, forgot the docs update:
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -52,6 +52,7 @@
On 8/11/22 18:40, Nicholas Piggin wrote:
The chiptod is a pervasive facility which can keep a time, synchronise
it across multiple chips, and can move that time to or from the core
timebase units.
This adds a very basic initial emulation of chiptod registers. The
interesting thing about chiptod
On 11/08/22 17:00, Gupta, Pankaj wrote:
>
>>> This is the v7 of this series which tries to implement the fd-based KVM
>>> guest private memory. The patches are based on latest kvm/queue branch
>>> commit:
>>>
>>> b9b71f43683a (kvm/queue) KVM: x86/mmu: Buffer nested MMU
>>> split_desc_cache
On 8/11/22 08:14, Alex Bennée wrote:
Before: 35.912 s ± 0.168 s
After: 35.565 s ± 0.087 s
Signed-off-by: Alex Bennée
---
accel/tcg/cputlb.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/11/22 09:58, Richard Henderson wrote:
On 8/11/22 02:55, Ilya Leoshkevich wrote:
Right now translator stops right *after* the end of a page, which
breaks reporting of fault locations when the last instruction of a
multi-insn translation block crosses a page boundary.
An implementation,
On 8/11/22 08:14, Alex Bennée wrote:
The class cast checkers are quite expensive and always on (unlike the
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
avoid the overhead of repeatedly checking something which should never
change we cache the CPUClass reference for use in
With FEAT_PMUv3p5, the event counters are now 64 bit, rather than 32
bit. (Previously, only the cycle counter could be 64 bit, and other
event counters were always 32 bits). For any given event counter,
whether the overflow event is noted for overflow from bit 31 or from
bit 63 is controlled by
Our feature test functions that check the PMU version are named
isar_feature_{aa32,aa64,any}_pmu_8_{1,4}. This doesn't match the
current Arm ARM official feature names, which are FEAT_PMUv3p1 and
FEAT_PMUv3p4. Rename these functions to _pmuv3p1 and _pmuv3p4.
This commit was created with:
sed
On 8/11/22 08:14, Alex Bennée wrote:
This is a heavily used function so lets avoid the cost of
CPU_GET_CLASS. On the romulus-bmc run it has a modest effect:
Before: 36.812 s ± 0.506 s
After: 35.912 s ± 0.168 s
Signed-off-by: Alex Bennée
---
hw/core/cpu-sysemu.c | 5 ++---
1 file
FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD,
which disable the cycle counter from counting at EL2 and EL3.
Add the code to support these bits.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 20
target/arm/helper.c | 20
2
The architecture requires that if PMCR.LC is set (for a 64-bit cycle
counter) then PMCR.D (which enables the clock divider so the counter
ticks every 64 cycles rather than every cycle) should be ignored. We
were always honouring PMCR.D; fix the bug so we correctly ignore it
in this situation.
Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
compliant PMU.
Signed-off-by: Peter Maydell
---
target/arm/cpu64.c | 2 +-
target/arm/cpu_tcg.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
pmu_counter_mask() accidentally returns a value with bits [63:32]
set, because the expression it returns is evaluated as a signed value
that gets sign-extended to 64 bits. Force the whole expression to be
evaluated with 64-bit arithmetic with ULL suffixes.
The main effect of this bug was that a
The PMU cycle and event counter infrastructure design requires that
operations on the PMU register fields are wrapped in pmu_op_start()
and pmu_op_finish() calls (or their more specific pmmcntr and
pmevcntr equivalents). This includes any changes to registers which
affect whether the counter
In pmccntr_op_finish() and pmevcntr_op_finish() we calculate the next
point at which we will get an overflow and need to fire the PMU
interrupt or set the overflow flag. We do this by calculating the
number of nanoseconds to the overflow event and then adding it to
When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
to indicate this. However a missing ULL suffix means that we end up
setting all of bits 63-31. Fix the bug.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This patchset implements the Armv8.5 feature FEAT_PMUv3p5, which is
a set of minor enhancements to the PMU:
* EL2 and EL3 can now prohibit the cycle counter from counting
when in EL2 or when Secure, using new MDCR_EL2.HCCD and
MDCR_EL3.SCCD bits
* event counters are now 64 bits, with the
The logic in pmu_counter_enabled() for handling the 'prohibit event
counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way
that assumes that EL2 is never Secure. This used to be true, but the
architecture now permits Secure EL2, and QEMU can emulate this.
Refactor the prohibit logic
On Thu, 11 Aug 2022 at 14:35, Pierre Muller wrote:
>I don't know if this is the right place to submit this report,
> but I have a problem with my attempt to check the 7.1.0 release candidate
> for linux user powerpc CPU.
>
>I am testing a simple executable, compiled with Free Pacal
On Tue, 9 Aug 2022 17:08:25 +0100
Jonathan Cameron wrote:
> On Tue, 9 Aug 2022 21:07:06 +0800
> Bobo WL wrote:
>
> > Hi Jonathan
> >
> > Thanks for your reply!
> >
> > On Mon, Aug 8, 2022 at 8:37 PM Jonathan Cameron
> > wrote:
> > >
> > > Probably not related to your problem, but there is
On 8/11/22 06:11, Peter Maydell wrote:
The newly added neoverse-n1 CPU has ID register values which indicate
the presence of the Statistical Profiling Extension, because the real
hardware has this feature. QEMU's TCG emulation does not yet
implement SPE, though (not even as a minimal stub
On Thu, 11 Aug 2022 at 16:24, Alex Bennée wrote:
>
> Hi,
>
> I've been collecting a number of small fixes since the tree was
> frozen. I've been mostly focusing on improving the reliability of the
> avocado tests and seeing if there are any low hanging fruit for
> improving the performance.
>
On 8/11/22 02:55, Ilya Leoshkevich wrote:
Right now translator stops right *after* the end of a page, which
breaks reporting of fault locations when the last instruction of a
multi-insn translation block crosses a page boundary.
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Richard Henderson
The gluster protocol driver used to parse URIs (filenames) but was
extended with a richer JSON syntax in commit 6c7189bb29de
("block/gluster: add support for multiple gluster servers"). The gluster
drivers that have JSON parsing set .bdrv_needs_filename to false.
The gluster+unix and gluster+rdma
On 8/11/22 02:55, Ilya Leoshkevich wrote:
Introduce a function that checks whether a given address is on the same
page as where disassembly started. Having it improves readability of
the following patches.
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Richard Henderson
r~
The chiptod is a pervasive facility which can keep a time, synchronise
it across multiple chips, and can move that time to or from the core
timebase units.
This adds a very basic initial emulation of chiptod registers. The
interesting thing about chiptod is that it targets cores and interacts
On 8/11/22 02:55, Ilya Leoshkevich wrote:
Right now translator stops right *after* the end of a page, which
breaks reporting of fault locations when the last instruction of a
multi-insn translation block crosses a page boundary.
An implementation, like the one arm and s390x have, would require
pxb/pxb-pcie/pxb-cxl devices currently doesn't have vmstate description
So the state of device is not preserved during migration and
guest can notice that as change of PCI_COMMAND_* registers state.
The diff of lspci output before and after migration:
00:03.0 Host bridge [0600]: Red Hat, Inc.
On Tue, Jul 12, 2022 at 04:23:32PM +0200, Stefano Garzarella wrote:
> On Fri, Jul 08, 2022 at 05:17:30AM +0100, Stefan Hajnoczi wrote:
> > libblkio (https://gitlab.com/libblkio/libblkio/) is a library for
> > high-performance disk I/O. It currently supports io_uring and
> > virtio-blk-vhost-vdpa
User creatable root ports are being parented by the 'peripheral' or the
'peripheral-anon' container. This happens because this is the regular
QOM schema for sysbus devices that are added via the command line.
Let's make this QOM hierarchy similar to what we have with default root
ports, i.e. the
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 2 ++
1 file changed, 2 insertions(+)
On 8/11/22 09:10, Janosch Frank wrote:
It's always better to convey the type of a pointer if at all
possible. So let's add the DumpState typedef to typedefs.h and move
the dump note functions from the opaque pointers to DumpState
pointers.
Signed-off-by: Janosch Frank
CC: Peter Maydell
CC:
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb4_pec.c | 6 --
hw/ppc/pnv.c | 2 ++
3 files changed, 7
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 17
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that was
reverted by commit 9c10d86fee "ppc/pnv: Remove
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-phbs, matching them with default
pnv-phbs.
A new helper
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is assigned during pnv_chip_power8_realize(),
while the
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 9 +++--
hw/ppc/pnv.c | 32
For default root ports we have a way of accessing chassis and slot,
before root_port_realize(), via pnv_phb_attach_root_port(). For the
future user created root ports this won't be the case: we can't use
this helper because we don't have access to the PHB phb-id/chip-id
values.
In earlier patches
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofold:
- there's not user side advantage in doing so.
We rely on the phb-id and chip-id, which are PHB properties, to assign
chassis and slot to the root port. For default devices this is no big
deal: the root port is being created under pnv_phb_realize() and the
values are being passed on via the 'index' and 'chip-id' of the
Hi,
This version contains changes based on Cedric's v3 feedback. The biggest
change was made in patch 4, where a new helper was added to handle the
logic where a PHB is added to a chip.
Changes from v3:
- patch 4:
- added Error **errp parameter to pnv_parent_bus_fixup() and
On 05.08.22 15:01, Jason A. Donenfeld wrote:
> Hi David,
>
> On Fri, Aug 05, 2022 at 01:28:18PM +0200, David Hildenbrand wrote:
>> On 03.08.22 19:15, Jason A. Donenfeld wrote:
>>> In order to fully support MSA_EXT_5, we have to also support the SHA-512
>>> special instructions. So implement
Hello Pierre,
On 8/11/22 15:31, Pierre Muller wrote:
Hello,
I don't know if this is the right place to submit this report,
Here is a good place :
https://gitlab.com/qemu-project/qemu/-/issues/
but I have a problem with my attempt to check the 7.1.0 release candidate
for linux
On 8/11/22 02:28, Ilya Leoshkevich wrote:
How is qemu-user's get_page_addr_code() involved here?
I tried to experiment with it, and while I agree that it looks buggy,
it's called only from translation code paths. If we already have a
translation block, these code paths are not used.
It's
When irqfd is enabled, we bypass QEMU's irq emulation and let KVM to
directly assert the irq. However, KVM is not aware of the device's MSI-x
masking status. Add MSI-x mask bookkeeping in NVMe emulation and
detach the corresponding irqfd when the certain vector is masked.
Signed-off-by: Jinhao
Use KVM's irqfd to send interrupts when possible. This approach is
thread safe. Moreover, it does not have the inter-thread communication
overhead of plain event notifiers since handler callback are called
in the same system call as irqfd write.
Signed-off-by: Jinhao Fan
---
hw/nvme/ctrl.c | 50
When the new option 'irq-eventfd' is turned on, the IO emulation code
signals an eventfd when it want to (de)assert an irq. The main loop
eventfd handler does the actual irq (de)assertion. This paves the way
for iothread support since QEMU's interrupt emulation is not thread
safe.
Asserting and
nvme_irq_assert() only does useful work when cq->irq_enabled is true.
nvme_irq_deassert() only works for pin-based interrupts. Avoid calls
into these functions if we are sure they will not do useful work.
This will be most useful when we use eventfd to send interrupts. We
can avoid the
This patch series changes qemu-nvme's interrupt emulation to use event
notifiers, which can ensure thread-safe interrupt delivery when iothread
is used. In the first two patches, I convert qemu-nvme's IO emulation
logic to send irq via eventfd, so that the actual assertion and
deassertion is
On 8/11/22 17:14, Alex Bennée wrote:
Investigating why some BMC models are so slow compared to a plain ARM
virt machines I did some profiling of:
./qemu-system-arm -M romulus-bmc -nic user \
-drive
file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \
-nographic
Hi,
I'm looking into making NVME device "migratable".
Following previous discussion on
https://lists.gnu.org/archive/html/qemu-devel/2017-08/msg05091.html, I would
like to implement the VMStateDescription to save and restore the entire
controller state, including all the queues.
"NvmeCtrl"
Laurent Vivier writes:
> Le 11/08/2022 à 13:54, Peter Maydell a écrit :
>> On Thu, 11 Aug 2022 at 09:29, Laurent Vivier wrote:
>>>
>>> Le 10/08/2022 à 22:47, Richard Henderson a écrit :
On 8/10/22 13:32, Vitaly Buka wrote:
> Sorry, I only noticed today that it's not submitted.
>
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