Add support for vIOMMU. Register a memory listener to dma_as in
dev_start
- during region_add register a specific IOMMU notifier, and store all notifiers
in a list.
- during region_del, compare and delete the IOMMU notifier from the list
Verified in vp_vdpa and vdpa_sim_net driver
Signed-off-by:
On Wed, Oct 19, 2022 at 8:29 AM Ani Sinha wrote:
>
> This introduces QEMU acpi/smbios biosbits avocado test which is run
> from within the python virtual environment. When the bits tests are run, bits
> binaries are downloaded from an external repo/location, bios bits iso is
> regenerated containi
On Wed, Oct 19, 2022 at 11:52 AM Thomas Huth wrote:
>
> On 18/10/2022 17.34, Ani Sinha wrote:
> > On Tue, Oct 18, 2022 at 9:01 PM Alex Bennée wrote:
> >>
> >>
> >> Ani Sinha writes:
> >>
> >>> Please see the README file in patch 9 for more details.
> >>> Sample runs are as follows:
> >>>
> >>> P
On 18/10/2022 17.34, Ani Sinha wrote:
On Tue, Oct 18, 2022 at 9:01 PM Alex Bennée wrote:
Ani Sinha writes:
Please see the README file in patch 9 for more details.
Sample runs are as follows:
Passed tests:
$ ./tests/venv/bin/avocado run -t acpi tests/avocado
Fetching asset from
tests/avo
+Daniel,
On Tue, Oct 11, 2022 at 8:04 PM Bin Meng wrote:
>
> +more people
>
> On Mon, Oct 3, 2022 at 6:21 AM Bin Meng wrote:
> >
> > Hi Paolo,
> >
> > On Sun, Sep 25, 2022 at 9:07 AM Bin Meng wrote:
> > >
> > > Hi Paolo,
> > >
> > > On Tue, Sep 13, 2022 at 5:52 PM Marc-André Lureau
> > > wrote
在 2022/10/19 05:54, Peter Xu 写道:
All x86 IOMMUs need to fail DEVIOTLB notification registrations if DT is
not supported. Otherwise any device (e.g. vhost) can register with
DEVIOTLB but it'll never receive the notifications, causing device not
operational.
Fixes: b68ba1ca57 ("memory: Add IOMM
在 2022/10/19 05:56, Peter Xu 写道:
On Tue, Oct 18, 2022 at 05:08:19PM +0200, Eric Auger wrote:
Hi Peter,
On 10/18/22 16:25, Peter Xu wrote:
Hi, Eric,
On Tue, Oct 18, 2022 at 02:28:52PM +0200, Eric Auger wrote:
Since b68ba1ca5767 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
IOMMUTLBNotificatio
Add a README file that describes the purpose of the various test files and gives
guidance to developers on where and how to make changes.
Cc: Daniel P. Berrange"
Cc: Paolo Bonzini
Cc: Maydell Peter
Cc: John Snow
Cc: Thomas Huth
Cc: Alex Bennée
Cc: Igor Mammedov
Cc: Michael Tsirkin
Signed-o
This change adds initial biosbits config file that instructs biosbits to run
bios test suits in batch mode. Additionally acpi and smbios structures are also
dumped.
Cc: Daniel P. Berrangé
Cc: Paolo Bonzini
Cc: Maydell Peter
Cc: John Snow
Cc: Thomas Huth
Cc: Alex Bennée
Cc: Igor Mammedov
Cc:
I wrote the biosbits avocado tests for testing QEMU's ACPI/SMBIOS implementation
and all the related changes including fixes in biosbits software itself. Making
myself as the maintainer for QEMU's biosbits related files and test scripts.
Cc: Daniel P. Berrangé
Cc: Paolo Bonzini
Cc: Maydell Peter
This introduces QEMU acpi/smbios biosbits avocado test which is run
from within the python virtual environment. When the bits tests are run, bits
binaries are downloaded from an external repo/location, bios bits iso is
regenerated containing the acpi/smbios bits tests that are maintained as a part
smilatency tests does not reliably pass every time it is run from QEMU. This
change adds the test file unchanged from bits so that the next change can
disable the test.
The test has an extension .py2 just like other tests so that they are excluded
from loading by avocado framework.
Cc: Daniel P.
smilatency test is latency sensitive and does not pass deterministically when
run in QEMU environment under biosbits. Disable the test suite for now.
Example failure:
SMI latency test
Warning: touching the keyboard can affect the results of this test.
Starting test. Wait here, I will be
Added the SPDX license identifier for smilatency tests.
Also added a comment indicating that smilatency test is run from within the
biosbits environment/VM and hence is not subjected to QEMU build/test
environment dependency fulfilments or QEMU maintanance activities.
Cc: Daniel P. Berrangé
Cc: P
This is initial commit of cpuid, acpi and smbios python test scripts for
biosbits to execute. No change has been made to them from the original code
written by the biosbits author Josh Triplett. They are required to be installed
into the bits iso file and then run from within the virtual machine bo
PSS tests in acpi test suite seems to be failing in biosbits. This is because
the test is unable to find PSS support in QEMU bios. Let us disable
them for now so that make check does not fail. We can fix the tests and
re-enable them later.
Example failure:
ACPI _PSS (Pstate) table conformanc
Added the SPDX license identifiers for biosbits tests.
Also added a comment on each of the test scripts to indicate that they run
from within the biosbits environment and hence are not subjected to the regular
maintanance acivities for QEMU and is excluded from the dependency management
challenges
Please see the README file in patch 9 for more details.
Sample runs are as follows:
Passed tests:
$ ./tests/venv/bin/avocado run -t acpi tests/avocado
Fetching asset from
tests/avocado/acpi-bits.py:AcpiBitsTest.test_acpi_smbios_bits
JOB ID : e95c7413e996bfb59389839e5ca5105464ef098f
JOB LOG
On Tue, 18 Oct 2022, Julien Grall wrote:
> On 18/10/2022 02:26, Stefano Stabellini wrote:
> > On Sun, 16 Oct 2022, Julien Grall wrote:
> > > Hi,
> > >
> > > There seem to be some missing patches on xen-devel (including the cover
> > > letter). Is that expected?
> > >
> > > On 15/10/2022 06:07, Vi
On 10/18/22 19:22, Alex Bennée wrote:
I'm not wedded to the idea - but it could be a super simple processor
with a lot less extra baggage than a full ISA - purely for throwing TCG
ops at rather than decoding any machine code.
I'd be surprised if you don't wind up with a similar amount of code a
On Tue, Oct 18, 2022 at 05:08:19PM +0200, Eric Auger wrote:
> Hi Peter,
>
> On 10/18/22 16:25, Peter Xu wrote:
> > Hi, Eric,
> >
> > On Tue, Oct 18, 2022 at 02:28:52PM +0200, Eric Auger wrote:
> >> Since b68ba1ca5767 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
> >> IOMMUTLBNotificationType"), vhos
All x86 IOMMUs need to fail DEVIOTLB notification registrations if DT is
not supported. Otherwise any device (e.g. vhost) can register with
DEVIOTLB but it'll never receive the notifications, causing device not
operational.
Fixes: b68ba1ca57 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
IOMMUTLBNo
Hi Jonathan,
> On Oct 13, 2022, at 8:09 AM, Jonathan Cameron
> wrote:
>
>> So, I would like to contribute to QEMU emulation of CXL memory
>> support. And I would like to see a TODO list. I hope this list could
>> be useful not only for me. As far as I can see, we can summarize:
>
> Absolute
These defines aren't used outside of sdhci.c, so can be defined there.
Signed-off-by: Bernhard Beschow
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-internal.h | 20
hw/sd/sdhci.c | 19 +++
2 files changed, 19 insertions
Will allow e500 boards to access SD cards using just their own devices.
Signed-off-by: Bernhard Beschow
---
hw/sd/sdhci.c | 120 +-
include/hw/sd/sdhci.h | 3 ++
2 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/hw/sd/sdhci.c b/hw/s
Cover letter:
~
This series adds support for -pflash and direct SD card access to the
PPC e500 boards. The idea is to increase compatibility with "real" firmware
images where only the bare minimum of drivers is compiled in.
The series is structured as follows:
Patches 1-4 perform som
Adds missing functionality to e500plat machine which increases the
chance of given "real" firmware images to access SD cards.
Signed-off-by: Bernhard Beschow
---
docs/system/ppc/ppce500.rst | 12
hw/ppc/Kconfig | 1 +
hw/ppc/e500.c | 35 ++
Allows e500 boards to have their root file system reside on flash using
only builtin devices located in the eLBC memory region.
Note that the flash memory area is only created when a -pflash argument is
given, and that the size is determined by the given file. The idea is to
put users into control
The documentation suggests that there is a qemu-system-ppc32 binary
while the 32 bit version is actually just named qemu-system-ppc. Settle
on qemu-system-ppc64 which also works for 32 bit machines and causes
less clutter in the documentation.
Found-by: BALATON Zoltan
Suggested-by: Bin Meng
Sign
On Tue, Oct 18, 2022 at 10:51:12AM -0400, Peter Xu wrote:
> On Tue, Oct 18, 2022 at 09:18:28AM +0100, Daniel P. Berrangé wrote:
> > On Mon, Oct 17, 2022 at 05:15:35PM -0400, Peter Xu wrote:
> > > On Mon, Oct 17, 2022 at 12:38:30PM +0100, Daniel P. Berrangé wrote:
> > > > On Mon, Oct 17, 2022 at 01:
The device model's functions start with "usdhc_", so rename the defines
accordingly for consistency.
Signed-off-by: Bernhard Beschow
Reviewed-by: Bin Meng
---
hw/sd/sdhci.c | 66 +--
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/
According to the JEDEC standard the device length is communicated to an
OS as an exponent (power of two).
Signed-off-by: Bernhard Beschow
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 8 ++--
hw/block/pflash_cfi02.c | 5 +
2 files changed, 11 i
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On Tue, Oct 18, 2022 at 06:55:08PM +0100, Peter Maydell wrote:
> I've been looking at a (long-standing) bug where an avocado test
> intermittently fails.
>
> This happens because at the avocado end we write "halt\r" to the
> serial console, which is wired up to a Unix socket; but at the UART
> mod
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target/
This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments
Not only does this simplify the code, it improves the translation time
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h| 4 +-
targe
On 10/12/22 18:21, Pierre Morel wrote:
S390 CPU topology is only allowed for s390-virtio-ccw-7.3 and
newer S390 machines.
We keep the possibility to disable the topology on these newer
machines with the property topology-disable.
Isn't 'topology' enough for the property ? I don't think the
'-di
I've been looking at a (long-standing) bug where an avocado test
intermittently fails.
This happens because at the avocado end we write "halt\r" to the
serial console, which is wired up to a Unix socket; but at the UART
model we only ever see the 'h' character and no further data. As far
as I can
On Sun, Sep 18, 2022 at 12:35 PM Nir Soffer wrote:
> ping
>
> Kevin, Hanna, I hope you have time to take a look.
>
> https://lists.nongnu.org/archive/html/qemu-block/2022-09/msg00021.html
Ping again, hopefully someone has time to look at this :-)
>
>
>
> On Thu, Sep 1, 2022 at 5:32 PM Nir Sof
On 10/12/22 18:21, Pierre Morel wrote:
The S390 CPU topology accepts the smp.threads argument while
in reality it does not effectively allow multthreading.
Let's keep this behavior for machines older than 7.3 and
refuse to use threads in newer machines until multithreading
is really proposed to
On 10/12/22 18:21, Pierre Morel wrote:
S390 CPU topology is only allowed for s390-virtio-ccw-7.3 and
newer S390 machines.
We keep the possibility to disable the topology on these newer
machines with the property topology-disable.
Signed-off-by: Pierre Morel
---
include/hw/boards.h
On 10/12/22 18:21, Pierre Morel wrote:
The guest can use the STSI instruction to get a buffer filled
with the CPU topology description.
Let us implement the STSI instruction for the basis CPU topology
level, level 2.
Signed-off-by: Pierre Morel
---
include/hw/s390x/cpu-topology.h | 3 +
t
On 10/12/22 18:21, Pierre Morel wrote:
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case of a subsystem reset.
Signed-off-by: Pierre Morel
Reviewed-by: Nico Boehr
Reviewe
*** Changes in v2 ***
Update test case to use both true and false predicates
Add fix for .cur
Here are example instructions with a predicated .tmp/.cur assignment
if (p1) v12.tmp = vmem(r7 + #0)
if (p0) v12.cur = vmem(r9 + #0)
The .tmp/.cur indicates that references to v12 in the same pack
On Tue, Oct 18, 2022 at 06:09:28PM +0100, Peter Maydell wrote:
> On Thu, 6 Oct 2022 at 17:20, Bin Meng wrote:
> >
> > From: Xuzhou Cheng
> >
> > Socket communication in the libqtest and libqmp codes uses read()
> > and write() which work on any file descriptor on *nix, and sockets
> > in *nix are
On Thu, 6 Oct 2022 at 17:20, Bin Meng wrote:
>
> From: Xuzhou Cheng
>
> Socket communication in the libqtest and libqmp codes uses read()
> and write() which work on any file descriptor on *nix, and sockets
> in *nix are an example of a file descriptor.
>
> However sockets on Windows do not use *
There are still a lot of old files in the QEMU UI, graphics, audio and USB code
base that use TABs for indentation instead of using 4 spaces in these files.
The TABs should be replaced with spaces, to make sure that we have a consistent
coding style with an indentation of 4 spaces everywhere.
Ama
On Tue, Oct 18, 2022 at 06:17:55PM +0200, Philippe Mathieu-Daudé wrote:
> On 18/10/22 17:25, Julia Suvorova wrote:
> > In the ACPI specification [1], the 'unarmed' bit is set when a device
> > cannot accept a persistent write. This means that when a memdev is
> > read-only, the 'unarmed' flag must
Bin Meng writes:
> From: Xuzhou Cheng
>
> Socket communication in the libqtest and libqmp codes uses read()
> and write() which work on any file descriptor on *nix, and sockets
> in *nix are an example of a file descriptor.
>
> However sockets on Windows do not use *nix-style file descriptors,
Hello Pierre,
On 10/12/22 18:20, Pierre Morel wrote:
In the S390x CPU topology the core_id specifies the CPU address
and the position of the core withing the topology.
Let's build the topology based on the core_id.
s390x/cpu topology: core_id sets s390x CPU topology
In the S390x CPU topology t
On 17/10/22 21:12, Eric Blake wrote:
Assigning strlen() to a uint32_t and then asserting that it isn't too
large doesn't catch the case of an input string 4G in length.
Thankfully, the incoming strings can never be that large: if the
export name or query is reflecting a string the client got from
On 18/10/22 17:25, Julia Suvorova wrote:
In the ACPI specification [1], the 'unarmed' bit is set when a device
cannot accept a persistent write. This means that when a memdev is
read-only, the 'unarmed' flag must be turned on. The logic is correct,
just changing the error message.
[1] ACPI NFIT
The TABs should be replaced with spaces, to make sure that we have a
consistent coding style with an indentation of 4 spaces everywhere.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370
Signed-off-by: Amarjargal Gundjalam
---
hw/usb/dev-hub.c | 86 +-
hw/usb/dev-network.c
The TABs should be replaced with spaces, to make sure that we have a
consistent coding style with an indentation of 4 spaces everywhere.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370
Signed-off-by: Amarjargal Gundjalam
---
hw/audio/fmopl.c | 1664 ++---
Bin Meng writes:
> Hi Alex,
>
> On Fri, Oct 7, 2022 at 1:31 PM Bin Meng wrote:
>>
>> On Fri, Oct 7, 2022 at 4:35 AM Alex Bennée wrote:
>> >
>> >
>> > Bin Meng writes:
>> >
>> > > In preparation to adding virtio-9p support on Windows, this series
>> > > enables running qtest on Windows, so th
The guest will see undefined behavior if it issue not negotiate
commands, bit it is expected somehow.
Simplify code deleting this check.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 48
1 file changed, 48 deletions(-)
diff --git a/net/vho
A gratuitous ARP is recommended after a live migration to reduce the amount of
time needed by the network links to be aware of the new location. A hypervisor
may not have the knowledge of the guest network configuration, and this is
especially true on passthrough devices, so its simpler to ask the
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 2a52672b44..14a265e30a 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -564,6 +564,9 @@ static NetClientState *net_vhost_vdpa_init(NetClientSt
Temporal, as this affects other vhost backends and we must check status
feature first.
Signed-off-by: Eugenio Pérez
---
hw/net/vhost_net.c | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
index d28f8b974b..
At this moment only _F_LOG is added there.
However future patches add features that depend on the kind of device.
In particular, only net devices can add VIRTIO_F_GUEST_ANNOUNCE. So
let's allow vhost_vdpa creator to set custom emulated device features.
Signed-off-by: Eugenio Pérez
---
include/h
Since this capability is emulated by qemu shadowed CVQ cannot forward it
to the device. Process all that command within qemu.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
Ani Sinha writes:
> I wrote the biosbits avocado tests for testing QEMU's ACPI/SMBIOS
> implementation
> and all the related changes including fixes in biosbits software itself.
> Making
> myself as the maintainer for QEMU's biosbits related files and test scripts.
>
> Cc: Daniel P. Berrangé
On Tue, Oct 18, 2022 at 9:01 PM Alex Bennée wrote:
>
>
> Ani Sinha writes:
>
> > Please see the README file in patch 9 for more details.
> > Sample runs are as follows:
> >
> > Passed tests:
> >
> > $ ./tests/venv/bin/avocado run -t acpi tests/avocado
> > Fetching asset from
> > tests/avocado/ac
On Tue, Oct 18, 2022 at 9:10 PM Alex Bennée wrote:
>
>
> Ani Sinha writes:
>
> > This introduces QEMU acpi/smbios biosbits avocado test which is run
> > from within the python virtual environment. When the bits tests are run,
> > bits
> > binaries are downloaded from an external repo/location, b
Ani Sinha writes:
> Please see the README file in patch 9 for more details.
> Sample runs are as follows:
>
> Passed tests:
>
> $ ./tests/venv/bin/avocado run -t acpi tests/avocado
> Fetching asset from
> tests/avocado/acpi-bits.py:AcpiBitsTest.test_acpi_smbios_bits
> JOB ID : e95c7413e996
Ani Sinha writes:
> This introduces QEMU acpi/smbios biosbits avocado test which is run
> from within the python virtual environment. When the bits tests are run, bits
> binaries are downloaded from an external repo/location, bios bits iso is
> regenerated containing the acpi/smbios bits tests
In the ACPI specification [1], the 'unarmed' bit is set when a device
cannot accept a persistent write. This means that when a memdev is
read-only, the 'unarmed' flag must be turned on. The logic is correct,
just changing the error message.
[1] ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM Sta
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Hi Peter,
On 10/18/22 16:25, Peter Xu wrote:
> Hi, Eric,
>
> On Tue, Oct 18, 2022 at 02:28:52PM +0200, Eric Auger wrote:
>> Since b68ba1ca5767 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
>> IOMMUTLBNotificationType"), vhost attempts to register DEVIOTLB_UNMAP
>> notifier. This latter is supported
+Gerd Hoffmann
On Tue, Oct 18, 2022 at 8:16 PM Gregory Price wrote:
>
> This patch does not resolve the issue, reserved entries are still created.
>
> [0.00] BIOS-e820: [mem 0x00028000-0x0002800f] reserved
> [0.00] BIOS-e820: [mem 0x00029000-0x00029
> > -e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
> > memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
> > memory_region_add_subregion(system_memory, cxl_base, mr);
> > cxl_resv_end = cxl_base + cxl_size;
> > @@ -1077,7 +1076,6 @@ void p
On Tue, Oct 18, 2022 at 09:18:28AM +0100, Daniel P. Berrangé wrote:
> On Mon, Oct 17, 2022 at 05:15:35PM -0400, Peter Xu wrote:
> > On Mon, Oct 17, 2022 at 12:38:30PM +0100, Daniel P. Berrangé wrote:
> > > On Mon, Oct 17, 2022 at 01:06:00PM +0530, manish.mishra wrote:
> > > > Hi Daniel,
> > > >
>
These are exactly the same as the non-VEX version, but one has to be careful
that only VEX.L=0 is allowed.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 25 +
target/i386/tcg/emit.c.inc | 20
This patch does not resolve the issue, reserved entries are still created.
[0.00] BIOS-e820: [mem 0x00028000-0x0002800f]
reserved
[0.00] BIOS-e820: [mem 0x00029000-0x00029fff]
reserved
# cat /proc/iomem
29000-29fff : CXL Window 0
29000
On Tue, Oct 18, 2022 at 3:27 AM Kirill A . Shutemov
wrote:
>
> On Mon, Oct 17, 2022 at 06:39:06PM +0200, Gupta, Pankaj wrote:
> > On 10/17/2022 6:19 PM, Kirill A . Shutemov wrote:
> > > On Mon, Oct 17, 2022 at 03:00:21PM +0200, Vlastimil Babka wrote:
> > > > On 9/15/22 16:29, Chao Peng wrote:
> >
REX.W can be used even in 32-bit mode by AVX instructions, where it is
retroactively
renamed to VEX.W. Make the field available even in 32-bit mode but keep the
REX_W()
macro as it was; this way, that the handling of dflag does not use it by
mistake and
the AVX code more clearly points at the s
Hi, Eric,
On Tue, Oct 18, 2022 at 02:28:52PM +0200, Eric Auger wrote:
> Since b68ba1ca5767 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
> IOMMUTLBNotificationType"), vhost attempts to register DEVIOTLB_UNMAP
> notifier. This latter is supported by the intel-iommu which supports
> device-iotlb if th
Extracted from a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/Makefile.target | 2 +-
tests/tcg/i386/test-avx.c | 201 ++---
tests/tcg/i386/test-avx.py | 5 +-
3 files changed, 113 insertions(+), 95
There are several special cases here:
1) extending moves have different widths for the helpers vs. for the
memory loads, and the width for memory loads depends on VEX.L too.
This is represented by X86_SPECIAL_AVXExtMov.
2) some instructions, such as variable-width shifts, select the vector elemen
These are more simple integer instructions present in both MMX and SSE/AVX,
with no holes that were later occupied by newer instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 28
target/i386/tcg/emit.c.in
Here the code is a bit uglier due to the truncation and extension
of registers to and from 32-bit. There is also a mistake in the
manual with respect to the size of the memory operand of CVTPS2PI
and CVTTPS2PI, reported by Ricky Zhou.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
The more complicated operations here are insertions and extractions.
Otherwise, there are just more entries than usual because the PS/PD/SS/SD
variations are encoded in the opcode rater than in the prefixes.
These three-byte opcodes also include AVX new instructions, whose
implementation in the he
From: Paul Brook
Include AVX, AVX2 and VAES in the guest cpuid features supported by TCG.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-40-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 10 +-
1 file changed, 5 inser
Add to the helpers all the operands that are needed to implement AVX.
Extracted from a patch by Paul Brook .
Message-Id: <20220424220204.2493824-26-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 173 +---
On 18/10/22 11:58, Michael Tokarev wrote:
10.10.2022 11:53, Helge Deller wrote:
On 10/9/22 08:08, WANG Xuerui wrote:
User space has been preferring this syscall for a while, due to its
closer match with C semantics, and newer platforms such as LoongArch
apparently have libc implementations that
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
helpers to provide this functionality.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 16 ++
These are mostly moves, and yet are a total pain. The main issue
is that:
1) some instructions are selected by mod==11 (register operand)
vs. mod=00/01/10 (memory operand)
2) stores to memory are two-operand operations, while the 3-register
and load-from-memory versions operate on the entire con
This includes shifts by immediate, which use bits 3-5 of the ModRM byte
as an opcode extension. With the exception of 128-bit shifts, they are
implemented using gvec.
This also covers VZEROALL and VZEROUPPER, which use the same opcode
as EMMS. If we were wanting to optimize out gen_clear_ymmh th
This adds another kind of weirdness when you thought you had seen it all:
an opcode byte that comes _after_ the address, not before. It's not
worth adding a new X86_SPECIAL_* constant for it, but it's actually
not unlike VCMP; so, forgive me for exploiting the similarity and just
deciding to dispa
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 164 ++-
target/i386/tcg/decode-new.h | 32 ++
target/i386/tcg/emit.c.inc | 37 ++-
target/i386/tcg/translate.c | 18 ++--
4 files changed, 239
TCG will shortly implement VAES instructions, so add the relevant feature
word to the DisasContext.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/tra
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 37 +
From: "Maciej S. Szmigiero"
Resetting a guest that has Hyper-V VMBus support enabled triggers a QEMU
assertion failure:
hw/hyperv/hyperv.c:131: synic_reset: Assertion
`QLIST_EMPTY(&synic->sint_routes)' failed.
This happens both on normal guest reboot or when using "system_reset" HMP
command.
T
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/fpu_helper.c | 78 ++--
1 file changed, 75 insertions(+), 3 deletions(-)
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 5f3f7a1085..7670739abe 100644
-
These are mostly floating-point SSE operations. The odd ones out
are MOVMSK and CVTxx2yy, the others are straightforward.
Unary operations are a bit special in AVX because they have 2 operands
for PD/PS operands (VEX. must be b), and 3 operands for SD/SS.
They are handled using X86_OP_GRO
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
old SSE decoder to be compatible with new-style helpers.
The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx.
Reviewed
These are a mixed batch, including the first two horizontal
(66 and F2 only) operations, more moves, and SSE4a extract/insert.
Because SSE4a is pretty rare, I chose to leave the helper as they are,
but it is possible to unify them by loading index and length from the
source XMM register and genera
From: Richard Henderson
This will be used for emission and endian adjustments of gvec operations.
Signed-off-by: Richard Henderson
Message-Id: <2022083722.1697758-2-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 56 --
From: Richard Henderson
These new mmu indexes will be helpful for improving
paging and code throughout the target.
Signed-off-by: Richard Henderson
Message-Id: <20221002172956.265735-6-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu-param.h | 2 +-
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